From 44c057e40dc19c34cc63750a8ed4d46de75d0b98 Mon Sep 17 00:00:00 2001
From: WilliamMiceli <git@williammiceli.me>
Date: Fri, 29 Mar 2019 16:16:11 -0400
Subject: [PATCH] Simplified testbench a little

---
 lab2CA.srcs/sources_1/new/dataMemory.v | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/lab2CA.srcs/sources_1/new/dataMemory.v b/lab2CA.srcs/sources_1/new/dataMemory.v
index a39032f..cc065ff 100644
--- a/lab2CA.srcs/sources_1/new/dataMemory.v
+++ b/lab2CA.srcs/sources_1/new/dataMemory.v
@@ -253,12 +253,8 @@ module dataMemory_tb();
     reg [8:0] address, writeData;
     wire [8:0] readData;
     
-        initial begin
-        clk = 1'b0;
-    end
-    always begin
+    always
         #5 clk = ~clk; // Period to be determined
-    end
     
     dataMemory dM0(
         .clk(clk),
@@ -268,7 +264,9 @@ module dataMemory_tb();
         .readData(readData)
     );
     
-    initial begin
+    initial
+    begin
+        clk = 1'b0;
         writeEnable = 1'b0;
         address = 9'b000000000;
         writeData = 9'b010101010;