diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index 5cdafdd..718a158 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -1,6 +1,6 @@
 `timescale 1ns / 1ps
 
-module adder_1bit(
+module add_1bit(
     input wire A,
     input wire B,
     input wire Cin,
@@ -12,7 +12,7 @@ module adder_1bit(
 
 endmodule
 
-module adder_9bit(
+module add_9bit(
     input wire [8:0] A,
     input wire [8:0] B,
     input wire Cin,
@@ -28,63 +28,63 @@ module adder_9bit(
     wire C_add6;
     wire C_add7;
 
-    adder_1bit add0(
+    add_1bit add0(
         .A(A[0]),
         .B(B[0]),
         .Cin(Cin),
         .S(Sum[0]),
         .Cout(C_add0));
 
-    adder_1bit add1(
+    add_1bit add1(
         .A(A[1]),
         .B(B[1]),
         .Cin(C_add0),
         .S(Sum[1]),
         .Cout(C_add1));
         
-    adder_1bit add2(
+    add_1bit add2(
         .A(A[2]),
         .B(B[2]),
         .Cin(C_add1),
         .S(Sum[2]),
         .Cout(C_add2));
         
-    adder_1bit add3(
+    add_1bit add3(
         .A(A[3]),
         .B(B[3]),
         .Cin(C_add2),
         .S(Sum[3]),
         .Cout(C_add3));
         
-    adder_1bit add4(
+    add_1bit add4(
         .A(A[4]),
         .B(B[4]),
         .Cin(C_add3),
         .S(Sum[4]),
         .Cout(C_add4));
         
-    adder_1bit add5(
+    add_1bit add5(
         .A(A[5]),
         .B(B[5]),
         .Cin(C_add4),
         .S(Sum[5]),
         .Cout(C_add5));
         
-    adder_1bit add6(
+    add_1bit add6(
         .A(A[6]),
         .B(B[6]),
         .Cin(C_add5),
         .S(Sum[6]),
         .Cout(C_add6));
         
-    adder_1bit add7(
+    add_1bit add7(
         .A(A[7]),
         .B(B[7]),
         .Cin(C_add6),
         .S(Sum[7]),
         .Cout(C_add7));
         
-    adder_1bit add8(
+    add_1bit add8(
         .A(A[8]),
         .B(B[8]),
         .Cin(C_add7),
@@ -425,20 +425,55 @@ module register(input wire clk, reset,
 
 endmodule
 
-module twos_compliment_9bit(
+module shift_logical_left(
     input wire [8:0] A,
+    output wire [8:0] B);
+    
+    assign B = {A[7:0],A[8]};
+
+endmodule
+
+module shift_logical_right(
+    input wire [8:0] A,
+    output wire [8:0] B);
+    
+    assign B = {A[0],A[8:1]};
+
+endmodule
+
+module sub_9bit(
+    input wire [8:0] A,
+    input wire [8:0] B,
     output wire [8:0] C);
     
-    wire [8:0] B;
+    wire [8:0] D;
+    
+    twos_compliment_9bit two_comp0(
+        .A(B),
+        .C(D));
+    
+    add_9bit add0(
+        .A(A),
+        .B(D),
+        .Cin(1'b0),
+        .Sum(C));
+
+endmodule
+
+module twos_compliment_9bit(
+    input wire [8:0] A,
+    output wire [8:0] B);
+    
+    wire [8:0] C;
     
     not_9bit not0(
         .A(A),
-        .B(B));
+        .B(C));
         
-    adder_9bit adder0(
-        .A(B),
+    add_9bit add0(
+        .A(C),
         .B(9'b000000000),
         .Cin(1'b1),
-        .Sum(C));
+        .Sum(B));
 
 endmodule
\ No newline at end of file
diff --git a/lab2CA.xpr b/lab2CA.xpr
index 837e719..66cc1de 100644
--- a/lab2CA.xpr
+++ b/lab2CA.xpr
@@ -104,8 +104,7 @@
       <Filter Type="Srcs"/>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="adder_9bit"/>
-        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopModule" Val="ALU"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
         <Option Name="SrcSet" Val="sources_1"/>