diff --git a/lab2CA.runs/synth_1/CPU9bits.tcl b/lab2CA.runs/synth_1/CPU9bits.tcl deleted file mode 100644 index 0ff5867..0000000 --- a/lab2CA.runs/synth_1/CPU9bits.tcl +++ /dev/null @@ -1,63 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param synth.incrementalSynthesisCache C:/Users/willi/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-18452-WM-G75VW/incrSyn -set_msg_config -id {Synth 8-256} -limit 10000 -set_msg_config -id {Synth 8-638} -limit 10000 -create_project -in_memory -part xc7k160tifbg484-2L - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_property webtalk.parent_dir {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/wt} [current_project] -set_property parent.project_path {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo {c:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/ip} [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_verilog -library xil_defaultlib { - {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v} - {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v} - {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v} - {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v} - {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v} - {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v} - {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v} - {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v} -} -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 -close [open __synthesis_is_running__ w] - -synth_design -top CPU9bits -part xc7k160tifbg484-2L - - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef CPU9bits.dcp -create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb" -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt deleted file mode 100644 index eb83468..0000000 --- a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt +++ /dev/null @@ -1,183 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sun Mar 24 16:58:30 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb -| Design : CPU9bits -| Device : 7k160tifbg484-2L -| Design State : Synthesized ------------------------------------------------------------------------------------------------------------ - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 578 | 0 | 101400 | 0.57 | -| LUT as Logic | 578 | 0 | 101400 | 0.57 | -| LUT as Memory | 0 | 0 | 35000 | 0.00 | -| Slice Registers | 235 | 0 | 202800 | 0.12 | -| Register as Flip Flop | 81 | 0 | 202800 | 0.04 | -| Register as Latch | 154 | 0 | 202800 | 0.08 | -| F7 Muxes | 6 | 0 | 50700 | 0.01 | -| F8 Muxes | 0 | 0 | 25350 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 154 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 81 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 325 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | -| RAMB18 | 0 | 0 | 650 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 600 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 3 | 0 | 285 | 1.05 | -| Bonded IPADs | 0 | 0 | 14 | 0.00 | -| Bonded OPADs | 0 | 0 | 8 | 0.00 | -| PHY_CONTROL | 0 | 0 | 8 | 0.00 | -| PHASER_REF | 0 | 0 | 8 | 0.00 | -| OUT_FIFO | 0 | 0 | 32 | 0.00 | -| IN_FIFO | 0 | 0 | 32 | 0.00 | -| IDELAYCTRL | 0 | 0 | 8 | 0.00 | -| IBUFDS | 0 | 0 | 275 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 1 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | -| ILOGIC | 0 | 0 | 285 | 0.00 | -| OLOGIC | 0 | 0 | 285 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 2 | 0 | 32 | 6.25 | -| BUFIO | 0 | 0 | 32 | 0.00 | -| MMCME2_ADV | 0 | 0 | 8 | 0.00 | -| PLLE2_ADV | 0 | 0 | 8 | 0.00 | -| BUFMRCE | 0 | 0 | 16 | 0.00 | -| BUFHCE | 0 | 0 | 120 | 0.00 | -| BUFR | 0 | 0 | 32 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| LUT6 | 439 | LUT | -| LDCE | 154 | Flop & Latch | -| FDRE | 81 | Flop & Latch | -| LUT5 | 69 | LUT | -| LUT4 | 51 | LUT | -| LUT3 | 50 | LUT | -| LUT2 | 45 | LUT | -| MUXF7 | 6 | MuxFx | -| IBUF | 2 | IO | -| BUFG | 2 | Clock | -| OBUF | 1 | IO | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/lab2CA.runs/synth_1/vivado.pb b/lab2CA.runs/synth_1/vivado.pb index 336cc57..02439a4 100644 Binary files a/lab2CA.runs/synth_1/vivado.pb and b/lab2CA.runs/synth_1/vivado.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou deleted file mode 100644 index 9df8652..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 11:08:04 2019 -# Process ID: 15032 -# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/JoseIgnacio/CA -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_37516.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_37516.backup.jou deleted file mode 100644 index 89ee5b3..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_37516.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Fri Mar 22 17:31:53 2019 -# Process ID: 37516 -# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/REPOSITORIES/Educational/Western -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_4720.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_4720.backup.jou deleted file mode 100644 index 482b2a6..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_4720.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 11:07:22 2019 -# Process ID: 4720 -# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/JoseIgnacio/CA -notrace diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v index f04a2f4..03caacc 100644 --- a/lab2CA.srcs/sources_1/new/CPU9bits.v +++ b/lab2CA.srcs/sources_1/new/CPU9bits.v @@ -186,7 +186,7 @@ module CPU9bits_tb(); .done(done)); initial begin - #10 + #5 reset = 1'b1; #10 reset = 1'b0; @@ -216,4 +216,4 @@ module CPU9bits_tb(); $finish; end -endmodule \ No newline at end of file +endmodule diff --git a/lab2CA.srcs/sources_1/new/dataMemory.v b/lab2CA.srcs/sources_1/new/dataMemory.v index 7c55a60..04644fd 100644 --- a/lab2CA.srcs/sources_1/new/dataMemory.v +++ b/lab2CA.srcs/sources_1/new/dataMemory.v @@ -9,6 +9,10 @@ module dataMemory( reg [8:0] memory [23:0]; initial begin + //Equation Solver Memory + memory[0] <= 9'b000000001; + memory[1] <= 9'b000000010; + // String Compare Memory // memory[0] <= 9'b000000100; // memory[1] <= 9'b000001000; @@ -16,10 +20,10 @@ module dataMemory( // memory[3] <= 9'b010101010; // memory[4] <= 9'b000001111; // memory[5] <= 9'b000000100; -// memory[6] <= 9'b000000011; +// memory[6] <= 9'b000000000; // memory[7] <= 9'b000000111; // memory[8] <= 9'b000001111; -// memory[9] <= 9'b000000100; +// memory[9] <= 9'b000000110; // memory[10] <= 9'b000000010; // memory[11] <= 9'b000000000; // memory[12] <= 9'b000000000; diff --git a/lab2CA.srcs/sources_1/new/instructionMemory.v b/lab2CA.srcs/sources_1/new/instructionMemory.v index d0b7019..c7cc954 100644 --- a/lab2CA.srcs/sources_1/new/instructionMemory.v +++ b/lab2CA.srcs/sources_1/new/instructionMemory.v @@ -10,12 +10,15 @@ module instructionMemory( initial begin //Equation Solver -// memory[0] <= 9'b000000000; -// memory[1] <= 9'b000100000; //load -// memory[2] <= 9'b000101000; //load -// memory[3] <= 9'b010100010; //add -// memory[4] <= 9'b111100000; //shift left -// memory[5] <= 9'b111100000; //shift left + memory[0] <= 9'b000000000; + memory[1] <= 9'b011000000; //add0 + memory[1] <= 9'b011001001; //add1 + memory[1] <= 9'b000100000; //load + memory[2] <= 9'b000101000; //load + memory[3] <= 9'b010100010; //add + memory[4] <= 9'b111100000; //shift left + memory[5] <= 9'b111100000; //shift left + memory[6] <= 9'b000000000; //halt // //Testing all instructions // memory[6] <= 9'b010100011; //sub @@ -74,7 +77,7 @@ module instructionMemory( // memory[37] <= 9'b101000000; // memory[38] <= 9'b101110111; // memory[39] <= 9'b000000000; - + // Bubble Sort memory[0] <= 9'b000000001; // nop @@ -210,8 +213,10 @@ module instructionMemory( end - always@(address)begin - readData <= memory[address]; + always@(address, clk)begin + if(clk == 1'b1)begin + readData <= memory[address]; + end end endmodule