From 54cccd419fa8f70152cdc221016edb75a818e15d Mon Sep 17 00:00:00 2001 From: goochey Date: Sat, 16 Feb 2019 17:40:18 -0500 Subject: [PATCH] Lots Lots --- lab2CA.cache/wt/webtalk_pa.xml | 81 +- lab2CA.runs/.jobs/vrs_config_17.xml | 11 + lab2CA.runs/.jobs/vrs_config_18.xml | 11 + lab2CA.runs/.jobs/vrs_config_19.xml | 11 + lab2CA.runs/.jobs/vrs_config_20.xml | 8 + lab2CA.runs/impl_1/FetchUnit.tcl | 153 +++ lab2CA.runs/impl_1/FetchUnit.vdi | 451 +++++++++ .../impl_1/FetchUnit_bus_skew_routed.pb | Bin 0 -> 30 bytes .../impl_1/FetchUnit_bus_skew_routed.rpt | 15 + .../FetchUnit_clock_utilization_routed.rpt | 154 +++ .../impl_1/FetchUnit_control_sets_placed.rpt | 65 ++ lab2CA.runs/impl_1/FetchUnit_drc_opted.pb | Bin 0 -> 37 bytes lab2CA.runs/impl_1/FetchUnit_drc_opted.rpt | 61 ++ lab2CA.runs/impl_1/FetchUnit_drc_routed.pb | Bin 0 -> 37 bytes lab2CA.runs/impl_1/FetchUnit_drc_routed.rpt | 61 ++ lab2CA.runs/impl_1/FetchUnit_io_placed.rpt | 526 ++++++++++ .../FetchUnit_methodology_drc_routed.pb | Bin 0 -> 52 bytes .../FetchUnit_methodology_drc_routed.rpt | 80 ++ lab2CA.runs/impl_1/FetchUnit_opt.dcp | Bin 0 -> 14153 bytes lab2CA.runs/impl_1/FetchUnit_placed.dcp | Bin 0 -> 131858 bytes lab2CA.runs/impl_1/FetchUnit_power_routed.rpt | 145 +++ .../impl_1/FetchUnit_power_summary_routed.pb | Bin 0 -> 722 bytes lab2CA.runs/impl_1/FetchUnit_route_status.pb | Bin 0 -> 43 bytes lab2CA.runs/impl_1/FetchUnit_route_status.rpt | 11 + lab2CA.runs/impl_1/FetchUnit_routed.dcp | Bin 0 -> 137423 bytes .../impl_1/FetchUnit_timing_summary_routed.pb | 2 + .../FetchUnit_timing_summary_routed.rpt | 173 ++++ .../impl_1/FetchUnit_utilization_placed.pb | Bin 0 -> 289 bytes .../impl_1/FetchUnit_utilization_placed.rpt | 208 ++++ lab2CA.runs/impl_1/gen_run.xml | 134 +++ lab2CA.runs/impl_1/htr.txt | 9 + lab2CA.runs/impl_1/init_design.pb | Bin 0 -> 1623 bytes lab2CA.runs/impl_1/opt_design.pb | Bin 0 -> 10568 bytes lab2CA.runs/impl_1/place_design.pb | Bin 0 -> 11931 bytes lab2CA.runs/impl_1/route_design.pb | Bin 0 -> 12048 bytes lab2CA.runs/impl_1/vivado.jou | 12 + lab2CA.runs/impl_1/vivado.pb | Bin 0 -> 149 bytes lab2CA.runs/synth_1/FetchUnit.dcp | Bin 13983 -> 13821 bytes lab2CA.runs/synth_1/FetchUnit.tcl | 1 + lab2CA.runs/synth_1/FetchUnit.vds | 78 +- .../synth_1/FetchUnit_utilization_synth.rpt | 2 +- lab2CA.runs/synth_1/gen_run.xml | 3 +- lab2CA.runs/synth_1/vivado.jou | 4 +- lab2CA.runs/synth_1/vivado.pb | Bin 27090 -> 26826 bytes lab2CA.sim/sim_1/behav/xsim/alu_tb.tcl | 11 + lab2CA.sim/sim_1/behav/xsim/alu_tb_vlog.prj | 10 + lab2CA.sim/sim_1/behav/xsim/regFile_tb.tcl | 11 + .../sim_1/behav/xsim/regFile_tb_vlog.prj | 10 + lab2CA.sim/sim_1/behav/xsim/webtalk.jou | 8 +- ...20.backup.jou => webtalk_12116.backup.jou} | 8 +- ...56.backup.jou => webtalk_14280.backup.jou} | 8 +- ...392.backup.jou => webtalk_5360.backup.jou} | 8 +- ...276.backup.jou => webtalk_5680.backup.jou} | 8 +- lab2CA.sim/sim_1/behav/xsim/xelab.pb | Bin 2008 -> 1748 bytes .../xsim.dir/alu_tb_behav/Compile_Options.txt | 1 + .../alu_tb_behav/TempBreakPointFile.txt | 1 + .../xsim/xsim.dir/alu_tb_behav/obj/xsim_1.c | 119 +++ .../webtalk/usage_statistics_ext_xsim.xml | 44 + .../alu_tb_behav/webtalk/xsim_webtalk.tcl | 42 + .../behav/xsim/xsim.dir/alu_tb_behav/xsim.mem | Bin 0 -> 8546 bytes .../regFile_tb_behav/Compile_Options.txt | 1 + .../regFile_tb_behav/TempBreakPointFile.txt | 1 + .../xsim.dir/regFile_tb_behav/obj/xsim_1.c | 124 +++ .../webtalk/usage_statistics_ext_xsim.xml | 44 + .../regFile_tb_behav/webtalk/xsim_webtalk.tcl | 42 + .../xsim/xsim.dir/regFile_tb_behav/xsim.mem | Bin 0 -> 4296 bytes .../webtalk/xsim_webtalk.tcl | 28 +- .../xsim/xsim.dir/register_tb_behav/xsim.mem | Bin 3190 -> 3218 bytes lab2CA.sim/sim_1/behav/xsim/xvlog.pb | Bin 2134 -> 435 bytes lab2CA.sim/sim_1/impl/func/xsim/alu_tb.tcl | 11 + .../sim_1/impl/func/xsim/alu_tb_func_impl.v | 927 +++++++++++++++++ .../sim_1/impl/func/xsim/alu_tb_vlog.prj | 8 + lab2CA.sim/sim_1/impl/func/xsim/webtalk.jou | 12 + lab2CA.sim/sim_1/impl/func/xsim/xelab.pb | Bin 0 -> 3142 bytes .../alu_tb_func_impl/Compile_Options.txt | 1 + .../alu_tb_func_impl/TempBreakPointFile.txt | 1 + .../xsim.dir/alu_tb_func_impl/obj/xsim_1.c | 119 +++ .../webtalk/usage_statistics_ext_xsim.xml | 54 + .../xsim/xsim.dir/alu_tb_func_impl/xsim.mem | Bin 0 -> 8605 bytes lab2CA.sim/sim_1/impl/func/xsim/xvlog.pb | Bin 0 -> 3680 bytes lab2CA.sim/sim_1/impl/timing/xsim/alu_tb.tcl | 11 + .../sim_1/impl/timing/xsim/alu_tb_time_impl.v | 931 ++++++++++++++++++ .../sim_1/impl/timing/xsim/alu_tb_vlog.prj | 8 + .../sim_1/impl/timing/xsim/regFile_tb.tcl | 11 + .../impl/timing/xsim/regFile_tb_time_impl.v | 463 +++++++++ .../impl/timing/xsim/regFile_tb_vlog.prj | 8 + lab2CA.sim/sim_1/impl/timing/xsim/webtalk.jou | 14 +- .../impl/timing/xsim/webtalk_12684.backup.jou | 12 + .../impl/timing/xsim/webtalk_17624.backup.jou | 12 + .../impl/timing/xsim/webtalk_6004.backup.jou | 12 + lab2CA.sim/sim_1/impl/timing/xsim/xelab.pb | Bin 1977 -> 1826 bytes .../alu_tb_time_impl/Compile_Options.txt | 1 + .../alu_tb_time_impl/TempBreakPointFile.txt | 1 + .../xsim.dir/alu_tb_time_impl/obj/xsim_1.c | 119 +++ .../webtalk/usage_statistics_ext_xsim.xml | 44 + .../alu_tb_time_impl/webtalk/xsim_webtalk.tcl | 42 + .../xsim/xsim.dir/alu_tb_time_impl/xsim.mem | Bin 0 -> 8557 bytes .../regFile_tb_time_impl/Compile_Options.txt | 1 + .../TempBreakPointFile.txt | 1 + .../regFile_tb_time_impl/obj/xsim_1.c | 124 +++ .../webtalk/usage_statistics_ext_xsim.xml | 54 + .../xsim.dir/regFile_tb_time_impl/xsim.mem | Bin 0 -> 4303 bytes lab2CA.sim/sim_1/impl/timing/xsim/xvlog.pb | Bin 447 -> 3248 bytes lab2CA.srcs/sources_1/new/ALU.v | 45 + lab2CA.srcs/sources_1/new/BasicModules.v | 2 +- lab2CA.srcs/sources_1/new/RegFile.v | 79 ++ lab2CA.xpr | 26 +- 107 files changed, 6032 insertions(+), 121 deletions(-) create mode 100644 lab2CA.runs/.jobs/vrs_config_17.xml create mode 100644 lab2CA.runs/.jobs/vrs_config_18.xml create mode 100644 lab2CA.runs/.jobs/vrs_config_19.xml create mode 100644 lab2CA.runs/.jobs/vrs_config_20.xml create mode 100644 lab2CA.runs/impl_1/FetchUnit.tcl create mode 100644 lab2CA.runs/impl_1/FetchUnit.vdi create mode 100644 lab2CA.runs/impl_1/FetchUnit_bus_skew_routed.pb create mode 100644 lab2CA.runs/impl_1/FetchUnit_bus_skew_routed.rpt create mode 100644 lab2CA.runs/impl_1/FetchUnit_clock_utilization_routed.rpt create mode 100644 lab2CA.runs/impl_1/FetchUnit_control_sets_placed.rpt create mode 100644 lab2CA.runs/impl_1/FetchUnit_drc_opted.pb create mode 100644 lab2CA.runs/impl_1/FetchUnit_drc_opted.rpt create mode 100644 lab2CA.runs/impl_1/FetchUnit_drc_routed.pb create mode 100644 lab2CA.runs/impl_1/FetchUnit_drc_routed.rpt create mode 100644 lab2CA.runs/impl_1/FetchUnit_io_placed.rpt create mode 100644 lab2CA.runs/impl_1/FetchUnit_methodology_drc_routed.pb create mode 100644 lab2CA.runs/impl_1/FetchUnit_methodology_drc_routed.rpt create mode 100644 lab2CA.runs/impl_1/FetchUnit_opt.dcp create mode 100644 lab2CA.runs/impl_1/FetchUnit_placed.dcp create mode 100644 lab2CA.runs/impl_1/FetchUnit_power_routed.rpt create mode 100644 lab2CA.runs/impl_1/FetchUnit_power_summary_routed.pb create mode 100644 lab2CA.runs/impl_1/FetchUnit_route_status.pb create mode 100644 lab2CA.runs/impl_1/FetchUnit_route_status.rpt create mode 100644 lab2CA.runs/impl_1/FetchUnit_routed.dcp create mode 100644 lab2CA.runs/impl_1/FetchUnit_timing_summary_routed.pb create mode 100644 lab2CA.runs/impl_1/FetchUnit_timing_summary_routed.rpt create mode 100644 lab2CA.runs/impl_1/FetchUnit_utilization_placed.pb create mode 100644 lab2CA.runs/impl_1/FetchUnit_utilization_placed.rpt create mode 100644 lab2CA.runs/impl_1/gen_run.xml create mode 100644 lab2CA.runs/impl_1/htr.txt create mode 100644 lab2CA.runs/impl_1/init_design.pb create mode 100644 lab2CA.runs/impl_1/opt_design.pb create mode 100644 lab2CA.runs/impl_1/place_design.pb create mode 100644 lab2CA.runs/impl_1/route_design.pb create mode 100644 lab2CA.runs/impl_1/vivado.jou create mode 100644 lab2CA.runs/impl_1/vivado.pb create mode 100644 lab2CA.sim/sim_1/behav/xsim/alu_tb.tcl create mode 100644 lab2CA.sim/sim_1/behav/xsim/alu_tb_vlog.prj create mode 100644 lab2CA.sim/sim_1/behav/xsim/regFile_tb.tcl create mode 100644 lab2CA.sim/sim_1/behav/xsim/regFile_tb_vlog.prj rename lab2CA.sim/sim_1/behav/xsim/{webtalk_1120.backup.jou => webtalk_12116.backup.jou} (71%) rename lab2CA.sim/sim_1/behav/xsim/{webtalk_6756.backup.jou => webtalk_14280.backup.jou} (73%) rename lab2CA.sim/sim_1/behav/xsim/{webtalk_13392.backup.jou => webtalk_5360.backup.jou} (73%) rename lab2CA.sim/sim_1/behav/xsim/{webtalk_1276.backup.jou => webtalk_5680.backup.jou} (71%) create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/Compile_Options.txt create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/TempBreakPointFile.txt create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/obj/xsim_1.c create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/usage_statistics_ext_xsim.xml create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/xsim_webtalk.tcl create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/xsim.mem create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/Compile_Options.txt create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/TempBreakPointFile.txt create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/obj/xsim_1.c create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/xsim.mem create mode 100644 lab2CA.sim/sim_1/impl/func/xsim/alu_tb.tcl create mode 100644 lab2CA.sim/sim_1/impl/func/xsim/alu_tb_func_impl.v create mode 100644 lab2CA.sim/sim_1/impl/func/xsim/alu_tb_vlog.prj create mode 100644 lab2CA.sim/sim_1/impl/func/xsim/webtalk.jou create mode 100644 lab2CA.sim/sim_1/impl/func/xsim/xelab.pb create mode 100644 lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/Compile_Options.txt create mode 100644 lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/TempBreakPointFile.txt create mode 100644 lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/obj/xsim_1.c create mode 100644 lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/webtalk/usage_statistics_ext_xsim.xml create mode 100644 lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/xsim.mem create mode 100644 lab2CA.sim/sim_1/impl/func/xsim/xvlog.pb create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/alu_tb.tcl create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_time_impl.v create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_vlog.prj create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb.tcl create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_time_impl.v create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_vlog.prj create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/webtalk_12684.backup.jou create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/webtalk_17624.backup.jou create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/webtalk_6004.backup.jou create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/Compile_Options.txt create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/TempBreakPointFile.txt create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/obj/xsim_1.c create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/usage_statistics_ext_xsim.xml create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/xsim_webtalk.tcl create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/xsim.mem create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/regFile_tb_time_impl/Compile_Options.txt create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/regFile_tb_time_impl/TempBreakPointFile.txt create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/regFile_tb_time_impl/obj/xsim_1.c create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/regFile_tb_time_impl/webtalk/usage_statistics_ext_xsim.xml create mode 100644 lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/regFile_tb_time_impl/xsim.mem diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 04ee3a5..5991027 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -19,47 +19,72 @@ This means code written to parse this file will need to be revisited each subseq - + + - - + + + + + + - - - - - - - - - + + + + + + + + + + + + + + + + + + + + - + - + + + + + + - - - - - + + + + + + + + + - - + + + + - - - - - + + +
diff --git a/lab2CA.runs/.jobs/vrs_config_17.xml b/lab2CA.runs/.jobs/vrs_config_17.xml new file mode 100644 index 0000000..b013dc9 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_18.xml b/lab2CA.runs/.jobs/vrs_config_18.xml new file mode 100644 index 0000000..b013dc9 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_19.xml b/lab2CA.runs/.jobs/vrs_config_19.xml new file mode 100644 index 0000000..b013dc9 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_20.xml b/lab2CA.runs/.jobs/vrs_config_20.xml new file mode 100644 index 0000000..ef5f93d --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/impl_1/FetchUnit.tcl b/lab2CA.runs/impl_1/FetchUnit.tcl new file mode 100644 index 0000000..39826c5 --- /dev/null +++ b/lab2CA.runs/impl_1/FetchUnit.tcl @@ -0,0 +1,153 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {Common 17-41} -limit 10000000 +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + create_project -in_memory -part xc7k160tifbg484-2L + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project] + set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project] + set_property ip_output_repo C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.dcp + link_design -top FetchUnit -part xc7k160tifbg484-2L + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force FetchUnit_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force FetchUnit_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file FetchUnit_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file FetchUnit_utilization_placed.rpt -pb FetchUnit_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force FetchUnit_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file FetchUnit_route_status.rpt -pb FetchUnit_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file FetchUnit_timing_summary_routed.rpt -pb FetchUnit_timing_summary_routed.pb -rpx FetchUnit_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file FetchUnit_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file FetchUnit_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file FetchUnit_bus_skew_routed.rpt -pb FetchUnit_bus_skew_routed.pb -rpx FetchUnit_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force FetchUnit_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + diff --git a/lab2CA.runs/impl_1/FetchUnit.vdi b/lab2CA.runs/impl_1/FetchUnit.vdi new file mode 100644 index 0000000..6d11f21 --- /dev/null +++ b/lab2CA.runs/impl_1/FetchUnit.vdi @@ -0,0 +1,451 @@ +#----------------------------------------------------------- +# Vivado v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Feb 16 17:35:59 2019 +# Process ID: 3548 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1 +# Command line: vivado.exe -log FetchUnit.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FetchUnit.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit.vdi +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source FetchUnit.tcl -notrace +Command: link_design -top FetchUnit -part xc7k160tifbg484-2L +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Project 1-479] Netlist was created with Vivado 2018.3 +INFO: [Device 21-403] Loading part xc7k160tifbg484-2L +INFO: [Project 1-570] Preparing netlist for logic optimization +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 578.453 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 584.031 ; gain = 333.246 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.760 . Memory (MB): peak = 598.289 ; gain = 14.258 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 3da38fa8 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1160.113 ; gain = 561.824 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 3da38fa8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1256.469 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 3da38fa8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1256.469 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 3da38fa8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1256.469 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 3da38fa8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1256.469 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 3da38fa8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1256.469 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 3da38fa8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1256.469 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1256.469 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 3da38fa8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.098 . Memory (MB): peak = 1256.469 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 3da38fa8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1256.469 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 3da38fa8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 3da38fa8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1256.469 ; gain = 672.438 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx +Command: report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2dee624c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1256.469 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: c3ac8419 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 17eb8b195 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 17eb8b195 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563 +Phase 1 Placer Initialization | Checksum: 17eb8b195 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 17eb8b195 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1261.789 ; gain = 5.320 +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: c93401db + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: c93401db + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 13d5628d5 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1566ae30c + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1566ae30c + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 179d3e6f9 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 179d3e6f9 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 179d3e6f9 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 +Phase 3 Detail Placement | Checksum: 179d3e6f9 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 179d3e6f9 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 179d3e6f9 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 179d3e6f9 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1280.449 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 1f8cde3fa + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f8cde3fa + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 +Ending Placer Task | Checksum: 12070b279 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 +INFO: [Common 17-83] Releasing license: Implementation +37 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1280.449 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 1280.449 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file FetchUnit_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1280.449 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_placed.rpt -pb FetchUnit_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1280.449 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 80d46943 ConstDB: 0 ShapeSum: 9f9c4936 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: c942aae2 + +Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1491.852 ; gain = 211.402 +Post Restoration Checksum: NetGraph: 96738515 NumContArr: 32cf25cd Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: c942aae2 + +Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1496.797 ; gain = 216.348 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: c942aae2 + +Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1496.797 ; gain = 216.348 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: a27c41a8 + +Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1520.801 ; gain = 240.352 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 15301da77 + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: af31d432 + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 +Phase 4 Rip-up And Reroute | Checksum: af31d432 + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: af31d432 + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: af31d432 + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 +Phase 6 Post Hold Fix | Checksum: af31d432 + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00297689 % + Global Horizontal Routing Utilization = 0.00221654 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 25.2252%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: af31d432 + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: af31d432 + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 4b1641fa + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +49 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 1520.801 ; gain = 240.352 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1520.801 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1520.801 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx +Command: report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx +Command: report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx +Command: report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +60 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file FetchUnit_route_status.rpt -pb FetchUnit_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file FetchUnit_timing_summary_routed.rpt -pb FetchUnit_timing_summary_routed.pb -rpx FetchUnit_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file FetchUnit_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file FetchUnit_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file FetchUnit_bus_skew_routed.rpt -pb FetchUnit_bus_skew_routed.pb -rpx FetchUnit_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 17:37:11 2019... diff --git a/lab2CA.runs/impl_1/FetchUnit_bus_skew_routed.pb b/lab2CA.runs/impl_1/FetchUnit_bus_skew_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..3390588d5da71a6f6866045d7ae5646edfab7b0e GIT binary patch literal 30 lcmd;LGcqu=&@-IGEZ|gHtWcbtTCPx(T3nh_Qapp10RVJW2(bVF literal 0 HcmV?d00001 diff --git a/lab2CA.runs/impl_1/FetchUnit_bus_skew_routed.rpt b/lab2CA.runs/impl_1/FetchUnit_bus_skew_routed.rpt new file mode 100644 index 0000000..327c37c --- /dev/null +++ b/lab2CA.runs/impl_1/FetchUnit_bus_skew_routed.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Sat Feb 16 17:37:11 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file FetchUnit_bus_skew_routed.rpt -pb FetchUnit_bus_skew_routed.pb -rpx FetchUnit_bus_skew_routed.rpx +| Design : FetchUnit +| Device : 7k160ti-fbg484 +| Speed File : -2L PRODUCTION 1.12 2017-02-17 +------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Bus Skew Report + +No bus skew constraints + diff --git a/lab2CA.runs/impl_1/FetchUnit_clock_utilization_routed.rpt b/lab2CA.runs/impl_1/FetchUnit_clock_utilization_routed.rpt new file mode 100644 index 0000000..6bb5cc8 --- /dev/null +++ b/lab2CA.runs/impl_1/FetchUnit_clock_utilization_routed.rpt @@ -0,0 +1,154 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Sat Feb 16 17:37:11 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file FetchUnit_clock_utilization_routed.rpt +| Design : FetchUnit +| Device : 7k160ti-fbg484 +| Speed File : -2L PRODUCTION 1.12 2017-02-17 +| Temperature Grade : I +-------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 120 | 0 | 0 | 0 | +| BUFIO | 0 | 32 | 0 | 0 | 0 | +| BUFMR | 0 | 16 | 0 | 0 | 0 | +| BUFR | 0 | 32 | 0 | 0 | 0 | +| MMCM | 0 | 8 | 0 | 0 | 0 | +| PLL | 0 | 8 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 9 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | None | IOB_X0Y78 | X0Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 9 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 | +| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y4 | 0 | 0 | +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 1 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | | | | 9 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y4 | 0 | 0 | +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 9 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 9 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y78 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1} +#endgroup diff --git a/lab2CA.runs/impl_1/FetchUnit_control_sets_placed.rpt b/lab2CA.runs/impl_1/FetchUnit_control_sets_placed.rpt new file mode 100644 index 0000000..73f98a5 --- /dev/null +++ b/lab2CA.runs/impl_1/FetchUnit_control_sets_placed.rpt @@ -0,0 +1,65 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Sat Feb 16 17:36:37 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt +| Design : FetchUnit +| Device : xc7k160ti +-------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 1 | +| Unused register locations in slices containing registers | 7 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 9 | 1 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 9 | 2 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++----------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------+---------------+------------------+------------------+----------------+ +| clk_IBUF_BUFG | | reset_IBUF | 2 | 9 | ++----------------+---------------+------------------+------------------+----------------+ + + diff --git a/lab2CA.runs/impl_1/FetchUnit_drc_opted.pb b/lab2CA.runs/impl_1/FetchUnit_drc_opted.pb new file mode 100644 index 0000000000000000000000000000000000000000..0158a2ad826bcd75c8436a6a29252340aee67559 GIT binary patch literal 37 scmd;LGcqtV(KDRH% + Ruledeck: default + Max violations: + Violations found: 3 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +21 out of 21 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], clk, op_idx, reset. +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +21 out of 21 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], clk, op_idx, reset. +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/lab2CA.runs/impl_1/FetchUnit_drc_routed.pb b/lab2CA.runs/impl_1/FetchUnit_drc_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..0158a2ad826bcd75c8436a6a29252340aee67559 GIT binary patch literal 37 scmd;LGcqtV(KDRH% + Ruledeck: default + Max violations: + Violations found: 3 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +21 out of 21 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], clk, op_idx, reset. +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +21 out of 21 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], clk, op_idx, reset. +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/lab2CA.runs/impl_1/FetchUnit_io_placed.rpt b/lab2CA.runs/impl_1/FetchUnit_io_placed.rpt new file mode 100644 index 0000000..4c071d9 --- /dev/null +++ b/lab2CA.runs/impl_1/FetchUnit_io_placed.rpt @@ -0,0 +1,526 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Sat Feb 16 17:36:37 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_io -file FetchUnit_io_placed.rpt +| Design : FetchUnit +| Device : xc7k160ti +| Speed File : -2L +| Package : fbg484 +| Package Version : FINAL 2012-06-26 +| Package Pin Delay Version : VERS. 2.0 2012-06-26 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 21 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| A3 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | | +| A4 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L4P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L4N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L9N_T1_DQS_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD4N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A19 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| A20 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| A21 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA1 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA3 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA4 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA5 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA6 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AA8 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA9 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA10 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA11 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA13 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA14 | AddrOut[3] | High Range | IO_L18P_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA15 | AddrOut[2] | High Range | IO_L18N_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA16 | AddrOut[5] | High Range | IO_L17P_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| AA18 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA19 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA20 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA21 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB1 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB2 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB3 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AB5 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB6 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB7 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB8 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB10 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB11 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB12 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB13 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| AB15 | AddrOut[7] | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB16 | AddrOut[6] | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB17 | AddrOut[4] | High Range | IO_L17N_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB18 | AddrOut[8] | High Range | IO_L15N_T2_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB20 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB21 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB22 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| B1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | | +| B2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B5 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | | +| B6 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B8 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B10 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B11 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L5N_T0_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| B15 | | High Range | IO_L9P_T1_DQS_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L8P_T1_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L10P_T1_AD4P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B20 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| B21 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B22 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | | +| C4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | | +| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C8 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| C9 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C12 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | IO_L5P_T0_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C14 | | High Range | IO_L7P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L7N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C17 | | High Range | IO_L12P_T1_MRCC_AD5P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | High Range | IO_L12N_T1_MRCC_AD5N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C19 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| C20 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| C21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C22 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| D1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | | +| D2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | | +| D6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | | +| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| D9 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D12 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D14 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L11P_T1_SRCC_AD12P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | IO_L11N_T1_SRCC_AD12N_15 | User IO | | 15 | | | | | | | | | | | | | | +| D17 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D19 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| D20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| D21 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| D22 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| E3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | | +| E4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | | High Range | IO_24_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E9 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E11 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E12 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| E13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| E14 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| E15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| E16 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| E22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| F1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | | +| F2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | | +| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | | +| F6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F9 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F10 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| F11 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| F12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| F13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| F14 | | High Range | IO_6_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| F19 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| F20 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| F21 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| F22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| G3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | | +| G4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| G7 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| G8 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| G9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| G11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| G12 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| G13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| G19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| G20 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| G21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| G22 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| H1 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | | +| H2 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H6 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| H7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| H8 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| H9 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| H10 | | High Range | IO_18_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| H13 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| H14 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| H15 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| H17 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| H19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| H20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H22 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J4 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | | +| J5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| J6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| J7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J16 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| J17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J19 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| J20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| J21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| J22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| K1 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K2 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K3 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| K7 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K16 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| K20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| K21 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| K22 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| L7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| L12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| L13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L16 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| L19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| L20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| L21 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Performance | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| M5 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| M6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| M7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| M12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M20 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| M21 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| M22 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| N2 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| N4 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N5 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N20 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| N21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| N22 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| P1 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| P2 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P4 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P5 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| P6 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P7 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P16 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| P19 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| P20 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| P21 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| P22 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| R2 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| R6 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| R7 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R16 | reset | High Range | IO_L20P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| R17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R21 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| R22 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| T3 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| T9 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| T10 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| T11 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | | +| T15 | AddrIn[2] | High Range | IO_L24P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| T16 | op_idx | High Range | IO_L20N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T19 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | +| T20 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| T21 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| T22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| U1 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U5 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| U7 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| U8 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| U9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| U10 | | High Performance | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| U11 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| U12 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| U13 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U15 | AddrIn[1] | High Range | IO_L24N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| U16 | AddrOut[1] | High Range | IO_L19P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U17 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| U19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| U20 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| U21 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| U22 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V2 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| V7 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| V8 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| V9 | | High Performance | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| V10 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V12 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| V13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| V14 | AddrIn[0] | High Range | IO_25_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| V15 | AddrIn[4] | High Range | IO_L23P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| V17 | AddrOut[0] | High Range | IO_L19N_T3_VREF_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V18 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| V19 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V20 | clk | High Range | IO_L11P_T1_SRCC_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V22 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| W1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| W2 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| W3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| W4 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| W7 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W9 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| W10 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| W11 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| W12 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| W14 | AddrIn[6] | High Range | IO_L22P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| W15 | AddrIn[3] | High Range | IO_L23N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| W16 | AddrIn[8] | High Range | IO_L21P_T3_DQS_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| W17 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W19 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W20 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W21 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| W22 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y1 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y2 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y3 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y4 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y6 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y7 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y8 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y9 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| Y11 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y12 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y13 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y14 | AddrIn[5] | High Range | IO_L22N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y16 | AddrIn[7] | High Range | IO_L21N_T3_DQS_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| Y17 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y18 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y19 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| Y21 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y22 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/lab2CA.runs/impl_1/FetchUnit_methodology_drc_routed.pb b/lab2CA.runs/impl_1/FetchUnit_methodology_drc_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..c491e055003f7fef7517f3da4b3dd24b80e4cad8 GIT binary patch literal 52 zcmd;LGcqtV(=(jJEajV8l98X1pOc?nso + Max violations: + Violations found: 9 ++-----------+----------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------+------------+ +| TIMING-17 | Warning | Non-clocked sequential cell | 9 | ++-----------+----------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin PC/Dout_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin PC/Dout_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin PC/Dout_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Warning +Non-clocked sequential cell +The clock pin PC/Dout_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Warning +Non-clocked sequential cell +The clock pin PC/Dout_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Warning +Non-clocked sequential cell +The clock pin PC/Dout_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#7 Warning +Non-clocked sequential cell +The clock pin PC/Dout_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#8 Warning +Non-clocked sequential cell +The clock pin PC/Dout_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#9 Warning +Non-clocked sequential cell +The clock pin PC/Dout_reg[8]/C is not reached by a timing clock +Related violations: + + diff --git a/lab2CA.runs/impl_1/FetchUnit_opt.dcp b/lab2CA.runs/impl_1/FetchUnit_opt.dcp new file mode 100644 index 0000000000000000000000000000000000000000..f714e82c22656a144575ccd3aff9209b065eae54 GIT binary patch literal 14153 zcmZ{r1CS+6_ov(Lp0;h*0003H6Dcpt8jAyO4F~|>1`GfI{#|QiXh-X2Z55R;X5-I~9K7^E zA*2Cnvz}0I^juc10uJ-o0Ajv`#rO);Cbb8O%w4cO|4dL3TvsPbkS|ki$XH1>vyg3yn>svGL1P+Rx zU8p6z|@`oYYN)PDrjDnFa3Q{*HXFHKA=+HOuOXf!F*Gl9o=KGkNJ z#a@MEkoy;;R~;;piMb`-D>Sx*6C8M;*DWq+UXN&aaXSWb?Y|TYG%ld!|1~3e+aVO* zKL7xpk^lf;zh^|$*vZgL*~Z+7*4W78LfhJQjUDkbTbE$JZ{VdSil)1X9ebK{vg&EJ zFoSdeD1xV_Hc42u8>BA2iGAINFN$2Dkduk{fY{jqD>q7)efJJV%#$5?gt=GU=>R8a z5VJOnNi|$ zkxOS!3Y$ct1tfx4BM>iPWOwl{qjE`S?n#5Edf{o6r+Q?E`s3&ZJzs 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Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 2.5 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.2 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. 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All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Sat Feb 16 17:37:11 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file FetchUnit_timing_summary_routed.rpt -pb FetchUnit_timing_summary_routed.pb -rpx FetchUnit_timing_summary_routed.rpx -warn_on_violation +| Design : FetchUnit +| Device : 7k160ti-fbg484 +| Speed File : -2L PRODUCTION 1.12 2017-02-17 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 9 register/latch pins with no clock driven by root clock pin: clk (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 18 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 11 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 9 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/lab2CA.runs/impl_1/FetchUnit_utilization_placed.pb b/lab2CA.runs/impl_1/FetchUnit_utilization_placed.pb new file mode 100644 index 0000000000000000000000000000000000000000..83594ed8df17e7fa073bd7f04af44fe9cf4897b3 GIT binary patch literal 289 zcmd;LGcqu=&@-OItPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- z*UdI;M^hz=S!Cgs)9USgUr9kYp z@(c_s9RJEQH1s(iRggOM+TpA!NPMmuL&GBHr)nT}uMvp63nax{mKuZDYb_WU8tnf9 zNd~8*mJAFY4wI}noI>5)okN0r&f0;L%(Vv+j!!`(!&?^+xz`m)IJUZh*uCB$@-C2U ua9HXCVt?|Hau11cHHvrk_x1Jn(}8k49R2)Uebxqol>7yf4faQaKx_bBPE4r) literal 0 HcmV?d00001 diff --git a/lab2CA.runs/impl_1/FetchUnit_utilization_placed.rpt b/lab2CA.runs/impl_1/FetchUnit_utilization_placed.rpt new file mode 100644 index 0000000..9a51d91 --- /dev/null +++ b/lab2CA.runs/impl_1/FetchUnit_utilization_placed.rpt @@ -0,0 +1,208 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Sat Feb 16 17:36:37 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_utilization -file FetchUnit_utilization_placed.rpt -pb FetchUnit_utilization_placed.pb +| Design : FetchUnit +| Device : 7k160tifbg484-2L +| Design State : Fully Placed +--------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 15 | 0 | 101400 | 0.01 | +| LUT as Logic | 15 | 0 | 101400 | 0.01 | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 9 | 0 | 202800 | <0.01 | +| Register as Flip Flop | 9 | 0 | 202800 | <0.01 | +| Register as Latch | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 9 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------------------------------------+------+-------+-----------+-------+ +| Slice | 4 | 0 | 25350 | 0.02 | +| SLICEL | 4 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 15 | 0 | 101400 | 0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 10 | | | | +| using O5 and O6 | 5 | | | | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 9 | 0 | 202800 | <0.01 | +| Register driven from within the Slice | 9 | | | | +| Register driven from outside the Slice | 0 | | | | +| Unique Control Sets | 1 | | 25350 | <0.01 | ++------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 325 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | +| RAMB18 | 0 | 0 | 650 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 21 | 0 | 285 | 7.37 | +| IOB Master Pads | 10 | | | | +| IOB Slave Pads | 10 | | | | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 275 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 1 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| IBUF | 12 | IO | +| OBUF | 9 | IO | +| FDRE | 9 | Flop & Latch | +| LUT6 | 6 | LUT | +| LUT5 | 5 | LUT | +| LUT4 | 5 | LUT | +| LUT3 | 2 | LUT | +| LUT2 | 1 | LUT | +| LUT1 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..a0355da --- /dev/null +++ b/lab2CA.runs/impl_1/gen_run.xml @@ -0,0 +1,134 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lab2CA.runs/impl_1/htr.txt b/lab2CA.runs/impl_1/htr.txt new file mode 100644 index 0000000..b9acc33 --- /dev/null +++ b/lab2CA.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. 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directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1 +# Command line: vivado.exe -log FetchUnit.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FetchUnit.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit.vdi +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source FetchUnit.tcl -notrace diff --git a/lab2CA.runs/impl_1/vivado.pb b/lab2CA.runs/impl_1/vivado.pb new file mode 100644 index 0000000000000000000000000000000000000000..98152f96397f3beb8ff6ec2385bed8b4a4ed22da GIT binary patch literal 149 zcmd;TVB`{Ut;j6N%u82LEmlY@0g`%pdRzjmQp`pMW?F2?`MJ6Ic}7xPY+;#Yi7EL; z>?x^fiKRIuRxpN<4wpnQP@`LFl7gX`f}y#UvALC@p@NZtp(Up3C^kcLU7*Ps3a+1emz^xVT*NQWSzxlks3?aZdf9yVG~Jt1Mx#g@FQX0r|a~O!@BoT6{wP+h9VLw zrPk}YCEb3J^K_oYQ1*!~yuT7!qUG$F6)GJEB+IPJ>JmkfXeU(Rpoo}^&~iy2ef&S+ znw%;(EC7}+Y4o@=sLhV^6SgqzpyHe<2PfdLF{wKA{nph=8;GCe3JkjeJTDK`TFRVI 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zLq}hyHlt6j03WZsg^O>anMYQ>EBEMvcGY`e1e+KP!1SJ$2F7;@S14SZ8@J1fZhuU< z=uXH`QU@)i&I3@!DW%<E7(5q9+ygn1|1tE zEIE^H=ssR^D;8M2OZ3KWiG8jd#C&|oX@XXutKf8_`pleTkv_dE>H2x5dEKgqh%7|_%o!GUE4OIOa#IS5 zDg0k^t$$ z**2}bVKnyi8M?EIMBNhhMDAXJs(!ly8A+*9+k{(!g;rX_N~KYhK1aN-9`6Ya{^-NI zWxM{b7%CA-JYK4b7Y7LFIhFv73n+U+S)gYAK9IRStvrMq`qz22A$HuOGip~?$*7{l zbB>waM!<3@Wv~t00zSM}M*pEsbIQWev4W7Znqre5H_i-zREP;HD?xxQ#OLVT4@yVn z0@c$Rd@bHd0WDEvUO9kgFtp|z6r;sJRsXG=EBKR}Kfv5$92VK^z(D3_t{ohjw|0ziL zA1nEudJhbQZsOY*1opoUG5iz$*VG=#x2(ATS>FGftNUm3ueAi)CeyIt{Kw}1ebN5i z|1Up{$!2T>|FQXhze)es<{`O=jht146$pqPNQ}i)U0z+%mRZPCRKtVOO;ui9NYhr+ c$ynLLQ%2K~na13lL!QOfRZ_{*QH}3^0nOgDUH||9 diff --git a/lab2CA.runs/synth_1/FetchUnit.tcl b/lab2CA.runs/synth_1/FetchUnit.tcl index 90d7f1b..90a441d 100644 --- a/lab2CA.runs/synth_1/FetchUnit.tcl +++ b/lab2CA.runs/synth_1/FetchUnit.tcl @@ -18,6 +18,7 @@ proc create_report { reportName command } { } } set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2460-DESKTOP-8QFGS52/incrSyn +set_msg_config -id {Common 17-41} -limit 10000000 set_msg_config -id {Synth 8-256} -limit 10000 set_msg_config -id {Synth 8-638} -limit 10000 create_project -in_memory -part xc7k160tifbg484-2L diff --git a/lab2CA.runs/synth_1/FetchUnit.vds b/lab2CA.runs/synth_1/FetchUnit.vds index 76d3558..9af85e5 100644 --- a/lab2CA.runs/synth_1/FetchUnit.vds +++ b/lab2CA.runs/synth_1/FetchUnit.vds @@ -2,8 +2,8 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 13:26:21 2019 -# Process ID: 8540 +# Start of session at: Sat Feb 16 17:27:36 2019 +# Process ID: 2948 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1 # Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds @@ -15,40 +15,39 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 11484 +INFO: Helper process launched with PID 2932 --------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 360.121 ; gain = 102.227 +Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.449 ; gain = 101.293 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] -INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:419] -INFO: [Synth 8-6155] done synthesizing module 'register' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:419] -INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15] +INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6155] done synthesizing module 'register' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:53] INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] -INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15] -WARNING: [Synth 8-350] instance 'PCAdder' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:18] -INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:167] -INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:172] -INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:167] +INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:53] +WARNING: [Synth 8-350] instance 'PCAdder' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:17] +INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:312] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317] +INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:312] INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] -WARNING: [Synth 8-3331] design FetchUnit has unconnected port write_index[1] -WARNING: [Synth 8-3331] design FetchUnit has unconnected port write_index[0] --------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.043 ; gain = 158.148 +Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.078 ; gain = 156.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.043 ; gain = 158.148 +Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.078 ; gain = 156.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k160tifbg484-2L --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.043 ; gain = 158.148 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.078 ; gain = 156.922 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7k160tifbg484-2L +INFO: [Synth 8-5544] ROM "Dout" won't be mapped to Block RAM because address size (2) smaller than threshold (5) --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.043 ; gain = 158.148 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.078 ; gain = 156.922 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -66,7 +65,8 @@ Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 +---Muxes : - 2 Input 9 Bit Muxes := 2 + 2 Input 9 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -79,7 +79,7 @@ Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 +---Muxes : - 2 Input 9 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 Module add_1bit Detailed RTL Component Info : +---XORs : @@ -105,10 +105,8 @@ No constraint files found. Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met -WARNING: [Synth 8-3331] design FetchUnit has unconnected port write_index[1] -WARNING: [Synth 8-3331] design FetchUnit has unconnected port write_index[0] --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 579.223 ; gain = 321.328 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.293 ; gain = 323.137 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -121,7 +119,7 @@ No constraint files found. Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 579.223 ; gain = 321.328 +Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.293 ; gain = 323.137 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -133,7 +131,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 579.223 ; gain = 321.328 +Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.293 ; gain = 323.137 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -157,7 +155,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +Finished IO Insertion : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 --------------------------------------------------------------------------------- Report Check Netlist: @@ -170,7 +168,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -182,25 +180,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -236,25 +234,25 @@ Report Instance Areas: |2 | PC |register | 29| +------+---------+---------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 -Synthesis Optimization Complete : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 +Synthesis Optimization Complete : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 677.328 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 680.656 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -18 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +19 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 677.328 ; gain = 419.434 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 677.328 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 680.656 ; gain = 430.656 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 680.656 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 13:26:46 2019... +INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 17:28:01 2019... diff --git a/lab2CA.runs/synth_1/FetchUnit_utilization_synth.rpt b/lab2CA.runs/synth_1/FetchUnit_utilization_synth.rpt index 7135af6..7d1befd 100644 --- a/lab2CA.runs/synth_1/FetchUnit_utilization_synth.rpt +++ b/lab2CA.runs/synth_1/FetchUnit_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Feb 16 13:26:46 2019 +| Date : Sat Feb 16 17:28:01 2019 | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Command : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb | Design : FetchUnit diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml index 7b1581b..e2dd59d 100644 --- a/lab2CA.runs/synth_1/gen_run.xml +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -44,6 +44,7 @@ diff --git a/lab2CA.runs/synth_1/vivado.jou b/lab2CA.runs/synth_1/vivado.jou index 432a836..07d2955 100644 --- a/lab2CA.runs/synth_1/vivado.jou +++ b/lab2CA.runs/synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 13:26:21 2019 -# Process ID: 8540 +# Start of session at: Sat Feb 16 17:27:36 2019 +# Process ID: 2948 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1 # Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds diff --git a/lab2CA.runs/synth_1/vivado.pb b/lab2CA.runs/synth_1/vivado.pb index 314ae08ed277bfaff70e9610c86e183c436f32d8..cfaa4efa3307c50e6044a2532156e2524a001736 100644 GIT binary patch delta 1022 zcmaiy&ubG=5XX6&O=C8RiAIwU8}mqwtx~u9Bb#Jf#h(YEsY(i7RO&XnO`~bH>24_6 zgQz$0pv+BATEUZ`J``FI?4ceM5hI>N(0@Rvpa-ewCMg(%Y%Y(P`F>{JmwB)L0lj{Y z9&1!slG#*B#v{0>lq&cD<~g1fWD(ZJ<#BuQYeQ@8oLP=sn zBDZ^jj#k{1NZpMQeDOrV>!~|LUa+7gO5__Q^4#k~8?_ev-Pe!cC)x%_17|}L%Vn}{ zW~4ML3xZ|l9-Q8?&_O0^<9&!QL7D0RH2Z&TKX+vnF=z58$8aKPB=Edm={NDDhG&%7 zSxv>Jj*pb}!bO}vJZ6;(O3l!)qN;P6VPK-GYaNJ4)L%uvDlHi+8c*E=NIgBGOBDwaDD1+PnKiTQW~D1Ae4$M zsTTGlBsWvm9fqOF5WG}r_@oAjQCC8tMIsSF6N$p#0DMRxFgY)TR@uFPDwHzIB5v!T}0p zQgI6?4OQ4Jb_Wgd4EN8@xZ~{YcZTmM3h|MJup;7w+}FKiN+gMt*}bQ5iLcwpw8<|x zY_!hNuc1Zi2_s~~(7EIh1MO^t2BYs7Bmq7%33&D{{d{)J3EHFv*M$hxCLWyl-`YAi zwGFf9?~kf8<|FLut1J;wmQtO*!_`l+3DR&w6lly z_D%jA0)Bpsx-Rb>LmdPHl)L)=7>d6Zppm)#!4&1^pAW1GDoa;T684vN?P`N@J_e7M z>w|QfUGXCXa9e-j7dS7*>CO@{2I3BJr@3K8Rjp~kYZRo~>P_n}FheMEQ4n)MXrFSL zdk9wYPRislVtY6#gjw^q5fd`p;et>vgrKf}`m0(F+Nww&7Ji{&IV~yagaSLI^dA?a BT$ca< diff --git a/lab2CA.sim/sim_1/behav/xsim/alu_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/alu_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/alu_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/alu_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/alu_tb_vlog.prj new file mode 100644 index 0000000..1efb11b --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/alu_tb_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ +"../../../../lab2CA.srcs/sources_1/new/ALU.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/regFile_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/regFile_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/regFile_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/regFile_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/regFile_tb_vlog.prj new file mode 100644 index 0000000..1d8aabe --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/regFile_tb_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ +"../../../../lab2CA.srcs/sources_1/new/RegFile.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou index c42d9ad..783e38b 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 16:27:58 2019 -# Process ID: 12116 +# Start of session at: Sat Feb 16 17:37:48 2019 +# Process ID: 11820 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_1120.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_12116.backup.jou similarity index 71% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_1120.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_12116.backup.jou index 5d7c550..c42d9ad 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_1120.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_12116.backup.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 16:08:33 2019 -# Process ID: 1120 +# Start of session at: Sat Feb 16 16:27:58 2019 +# Process ID: 12116 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_6756.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_14280.backup.jou similarity index 73% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_6756.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_14280.backup.jou index 970f9c6..0e82537 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_6756.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_14280.backup.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 16:24:44 2019 -# Process ID: 6756 +# Start of session at: Sat Feb 16 16:49:53 2019 +# Process ID: 14280 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_13392.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_5360.backup.jou similarity index 73% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_13392.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_5360.backup.jou index 0805a63..9fdaf29 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_13392.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_5360.backup.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 16:22:35 2019 -# Process ID: 13392 +# Start of session at: Sat Feb 16 16:36:59 2019 +# Process ID: 5360 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_1276.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_5680.backup.jou similarity index 71% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_1276.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_5680.backup.jou index 51fb553..1450c74 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_1276.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_5680.backup.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 16:09:25 2019 -# Process ID: 1276 +# Start of session at: Sat Feb 16 17:35:22 2019 +# Process ID: 5680 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index 20a959c83e03dd32e28b708fcac0068101419c7d..4ca6d1de278756b312edea22648470ff68feaa19 100644 GIT binary patch delta 194 zcmcb?e}#9#3&s}{Un;R|X5yMRnV<12dr@k-TV_t`g eP*=p4B!P^Y{FW^ps5F$_h)ab_0OrD(?DhZ?gF=A- delta 287 zcmcb@dxL+%3&tN4Un;R2X5v~mnV<2jc}aPGaeQ)qZb43FZfaghd`VJ#QffwGnLx9-6w%%uKaR9C`UA@rFs6C6f) +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_79(char*, char *); +extern void execute_181(char*, char *); +extern void execute_182(char*, char *); +extern void execute_183(char*, char *); +extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_180(char*, char *); +extern void execute_84(char*, char *); +extern void execute_85(char*, char *); +extern void execute_129(char*, char *); +extern void execute_102(char*, char *); +extern void execute_150(char*, char *); +extern void execute_159(char*, char *); +extern void execute_168(char*, char *); +extern void execute_177(char*, char *); +extern void execute_178(char*, char *); +extern void execute_78(char*, char *); +extern void execute_81(char*, char *); +extern void execute_82(char*, char *); +extern void execute_83(char*, char *); +extern void execute_184(char*, char *); +extern void execute_185(char*, char *); +extern void execute_186(char*, char *); +extern void execute_187(char*, char *); +extern void execute_188(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[25] = {(funcp)execute_79, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_180, (funcp)execute_84, (funcp)execute_85, (funcp)execute_129, (funcp)execute_102, (funcp)execute_150, (funcp)execute_159, (funcp)execute_168, (funcp)execute_177, (funcp)execute_178, (funcp)execute_78, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_184, (funcp)execute_185, (funcp)execute_186, (funcp)execute_187, (funcp)execute_188, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 25; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/alu_tb_behav/xsim.reloc", (void **)funcTab, 25); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/alu_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/alu_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/alu_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/alu_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/alu_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..c05fb8f --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +

+
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..9584e84 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,42 @@ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Feb 16 16:50:02 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "3" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key File_Counter -value "3" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Simulation_Image_Code -value "71 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Data -value "8 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Processes -value "113" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Instances -value "78" -context "xsim\\usage" +webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Time -value "0.67_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Memory -value "38660_KB" -context "xsim\\usage" +webtalk_transmit -clientid 746518105 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/alu_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


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+extern int main(int, char**); +extern void execute_2(char*, char *); +extern void execute_3(char*, char *); +extern void execute_17(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void execute_33(char*, char *); +extern void execute_34(char*, char *); +extern void execute_35(char*, char *); +extern void execute_36(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_6(char*, char *); +extern void execute_14(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_37(char*, char *); +extern void execute_38(char*, char *); +extern void execute_39(char*, char *); +extern void execute_40(char*, char *); +extern void execute_41(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +extern void transaction_10(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[30] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_17, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_6, (funcp)execute_14, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_10}; +const int NumRelocateId= 30; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/regFile_tb_behav/xsim.reloc", (void **)funcTab, 30); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/regFile_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/regFile_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/regFile_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/regFile_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/regFile_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..2c39c13 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..bb479d5 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,42 @@ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Feb 16 17:37:59 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "3" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key File_Counter -value "3" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Simulation_Image_Code -value "73 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Data -value "4 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Processes -value "37" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Instances -value "9" -context "xsim\\usage" +webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Time -value "0.70_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Memory -value "38824_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1475637981 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/xsim.mem new file mode 100644 index 0000000000000000000000000000000000000000..56b8140400972e86f51a8246d7f6ec648b197307 GIT binary patch literal 4296 zcmeHHX*iU97bg`)wz4EWGc7Wt8d5?SvKEGlw9t4`mUu`Q%PllnNGt9jARL^z2&->;5@_y{TuKPOw^FPb)+`s#r!^ii}r~1}Uz3`W` zcKxUQxAvQX-wga_;5P&RUj|aRTrThZJFCFohhI_x%Eu=NoMnM`^*{Xn%k6)vHox|H zJBW`jfPcZ>-D9tvbS);bTi+fedQ_^av(N42KtfFw!gXH3&*EHs;vs25vfL1 zp7Egl#QR3MTQbk=vr!sYHMWtq<-baMc9j3*whSYoH=8b;7aLn&o-^3E^0|T$TwyQVhYA~z?32EiBaL(x>DHs2 z1LqVz5R6>pnY7Zu?Yb(xt#9QuKHz;TPwae zoLz4fTlFO9k;B*=c`&(14ZBDW7%k`cdA9Ub4R(}`k@N`-3CD>#haDgADxc^vJ)$CmUn#bI003t|g$=tS#b-Ck9=dPK2hwP3?>sU99^m4?P zgo4QlH&cMO@Bh@Z(`}reHGUW7-rDJ1aFE*hzZjp#kA1ws$PFvrPPekHjTw(0x36m z_Um&&eS2{E{OEJZuzlm+M7jC?3a?{mS03y6Cd^(kxf-v1hBNwbGe<8jZi=OpeoUaN za&q=iWz6#`&sZn`$ zJPH!j0XNuFh*jS~POp2vV4vYl>?!@~n=~ZU=-pBAd7<;o@B#Ht`cFcY1YX`6g})V( zrlRJ?k6n#oDQOeSP)B#_yb~DIzfAZF6FQ83*TjvGF}z*>g1TDRbIO7hsbnJf*QNAP z4G&lN9pCI&>LJ&(?*iLHrm1&Xiw8p>nGG8*`ha~&JX?I0eGjC~a7lnW>Rg~;&ov4- zab&*1RdiIRylktXfIv&bl>kwuRC_JJv3(^(oUj4ShU{J`3(vru2X3&|G#_4+Ar2-i z9vxV*bw20HSg2Z^EfWn~>t(GQ02;(DxNNCD(MqXy1D6a}or=dHrNFyals}SqF|}!3 zJm6Z00=<|QLkO?}61zzK04~N+WdK(J9E{u50pJcv)%~bP1%u$BU#1-b@?*2dT_OaV zHpD*iKrz;|aGo%uedUSl@iq}pPJJRJbKRI%*|nbqAN!ba9|$SrMMlyI>mE&dr^>om zYiIY64ll42%R!R4t<6f^eYdqwGjdvpwe!nch4!xMtr;0pHAR={AhEhaG{N6!8_VTJleUilk$Zy}xh*1f;J94Sj@gz^j0lsiQ1)L@YPTwB&k&ZH~1iAtBwVQxPNE4)f8G38HDC zU^5{pOB$M(x!LbNNA60}&u@RV!$__?OkEWw-nSB4$?o^_g$LlK=HOUiuqS98A?2}A z9S|P&c|$RPyG5{ub`e3vXE2PHSLmREGZBt`eQdBabDS6+)L=mE1dJUSj9Ub|JJN@@ z7MG3yB!~luEtZ(o>S89~%P~)@ssMkwO5LLu%TTI;VkO&Qn%{NV5Avdd&4)cQ z;wOJ)DTqq8nY6=#djVR|pKVsJ6MvL^`*sc0E)Jcydb~MZ@`Y?VM58+hrLrxsY8l_Y zUGA}XW$c1KHQi+PFifXeq8 zXl%Bpx;W0$WIl3NvSWZovciJL(9Y0 zv=C8n@JrvrQFC3p@ZN&>vfRhApDVTbn!t7{7z3c6=dgV~CIL<5GP!e;if77tw$9{{ z3u+|D!WYix!M*EWuCT-W8j(**fkKW_PQ{Rc6mRbNz{<7xo4~9quM~hu-9!rw6gR3j zl~_AKujL?6om*#A77A*1e)WHhQ)Tx+e7Y9lqqFW=hdfaiMktnr1X#m+oh&r&jnR>R zwbI8Zr(4!A^RptmS2)iN)?NTp%W#jF_XGyVitAbL^=;ZA7+3?vdk0@FMSDljvZCV$ zL!RtgPp&heKOBx25DytPp3~l)Pnr`hr7H&{Hs{-=Z|sQDV5Hpqs7_b$>?l;$6%?n`Z%XxNaY(tKo2ZEmMcg$Iqs*LqN| zRJCg8OE>kNku2wvQa%N$PmBaCK5`OoI-bcLZ ze=&?$y_dk3Vi|a)c-oa?Uh!TTmXwotR*hYKGxx@tZ97JdU2}6!^P}X=iX^npE~kjb z$q#WiyUi8Ch5pcz*1zBe3w<#V`XoXBa#j2@r!T3|BQ#@|@#{DA6QvduCKO{IIt!Ym zv_dV?Fj?&`*&@+dGVntN#-AldQ5xtZ|rn~B?()+fX^H%Hn_i2 zOTvg%ZKHbfVRXW|#IHj)1Vt)>_dh%RBzcc~tSA+Xpu3Fw4;yMMK>ex1S6d*5KY&aj zEs#&r)kgDXiviKgZPS>!a7(5YqB+O4rQ`xsEe#dFXf9sop066{O6htpZt)Ey^XSIM Usage Report


" +webtalk_add_data -client xsim -key File_Counter -value "2" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Simulation_Image_Code -value "67 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Data -value "3 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Processes -value "18" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Instances -value "3" -context "xsim\\usage" +webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Time -value "0.70_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Memory -value "37616_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1179807410 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/xsim.mem index 8d9f00e1af024b1eb95ead92b8fc9128f5e6e987..8bd610b2c1d56ff87d386d28471a1617931bac1b 100644 GIT binary patch delta 1711 zcmV;g22lC-7?K&V_yvEK1^@tf0qt2`Y!p=#p0>7VMJfK(e*s0LO839p;!CkXB=J8n zeehx2w&SvK+mfAyf8 zH+!abySp&d6z3+h_ssX*bLN|G=I-p=wXDY4Mb&gB;A;rv_&R^;n`8j>2z5#zM*c+_ z$=l^Nza9m;7I5g~L*a1LU#rJ179(HhEjF%R4E4CzIl!yvgk+r(h>^eCI-5xa#8Hnh zpiS>UXA6P6U2a1??sYBT@H6cD^Fo_GTKzF}Ev2`g#OmwV)MRzmIs)qIJe_kT_5OJU z^lI((#5n(@d}V)5-=Gxh-9-eTDj|W$V-PW1K$^tU1`vsve*o{KH7>SMjsvp;0%|X&jCG#GTbx zkNXJzAsc`D(ftWW>gyvvjRVp5lDS`^c~sxLSvcyyo<~PWK&g-$VqF`xIA^%*jBIT` zx!!>DH103j-frozx(Md#P8C4>!DKo z`^1}bf?rzoYFU-#0ghVLuC~PnAd-j&j}BVdA%ku zD?Bjf+i62PEIcsg>2D*yO$ZN+dHS2iZ-c@EWBvx8wXCf0z?i>L@twj0V_vV5&!0Ev z4~+Q^l|LsuFy_}PepYy3%-^K=!@>h&{$|Bb2oH?;TNFPiJTT^OReV->V9ej9_)g)0 zF|U9BT%MmZ=MRke+g1LY@W7bAL-Di117rS9#UByu1bX(YP}m&W&8V}zu=(v^!rBd8>H9OdIeXdLJhUv`&H!=-v#wD z$77*)o@oAkdWiH+63*+`UTZqyJx8${^+5;rJ!1A>`qlj2m?Zz+B#57f?5`y_hv9!U z{uZsYDGC|U=&5hb^#;bhe@!WVPk3O=V-1HwYf^Z|cnscS_#VN1@($ssZ?*3nTUXu{ zy~mIzQHvai9Eco<9Qgk^F#VSI)b~$(y4!>Ye=)xgdaZTVA%b{4z#A#JpAbsmKb5`b z^FylU%va`j0Wco9S@8#i2gW?FSE7IAg$Ks`!yu{OAv`dg|LIT6@8Nzr|7jY>>mAc|I#2L}DSXN>+X(tn)B^LmV@UvO0-gfOT-rYin^ z*60VuBjbucD?Bjf6N;Y^9vJgU#UBtJ81pH`=YWljbwaPI;Hp#z;o^E9RFzjP z&nR7CYmkDWx^leSZc(@8rmMG`%BB5pnHl%IF{{a*dwuU>b}^pq{Dv35;0oeB6B0y(~o`X+xFKs`d85{Qw1jYjfu zz0I#jfvyD{I{8w#9QC*AvE^dq>%4N~>cvoxdz}Nkf=)=*DS;UIYpt`HR6rc{2m{*m z33Rp)$j9|I)Z<>)0uDdJem<|Z>8sTrLsvDueI!=j$EGH$v(^<*SLf-R)zo`s74&ND z^~9KeHD8(24=8`d`n2q2P?yPagICkneRr&{=iu-E>fKn@R04Tja)ZC@?OOZ$<%aP6 z^(NK8AIzV7odz7AU)mdr^{GztW8^bXbFiOPIY2$`^(f$xPVGwV7{1l=6YGR4HhSMH zF236G{1G>sPQ4Zy^;75i1~nMe>!-d}q_eWgk)Or^c1V9eGnE~y&Q$Z0Gx2$(uSLHB z+N)Qs{XJhReEz#0XcX&Hz=0m~UyI*Sd|}*o{vCzZh|ab6ozJ?~o6cw*;c2Sg z<9X*^kHk6d`#SYg%huELW6Yli)*S3-RSr-O{$V7}EBIOS(x@BhG>%4o;>l{P$8!Y# zkd5=``GkKX_4SdT#)0T_$viL7I;wBotQ>Wt*U{%B0GhTTQ2m*$=46@1{Yl5iEgjYl zg8VP;S9jXa`zIGbl<>fqzgO{t!UJReKE-E+2gdyUitiL281wp{%gc*q{=k@jK; zynf%M_1jP5*#&R?3a(0o8uB$}=xDau+8$GtCoY@&00|X2L zqKcpUIj9#L^nN;E^u9;_zD{|*UcptVP(y#McdM$rafM!R(A#m)=zX8`=CoeHRjE)z zt@m+N+5Rc$FF5G^O>})gdfgkO_X(x<>mP%9nd7-Z?=sQ+etL@ZP7}`i*j{rc^Ujo0 zz-iP69XRo}7jXy<8ZH7WdGO z81vY}q0pKZo-rPS-!c4*;5qq(aMZWX{^PxG5frt^fyjZ#fyjZ#f&ZNYb02x%`u@D< zx=eWGf_Xpav9?&J2;%(!Z=~RULMVa%t?Ye2KdoxcUo!6nzO(FwEb2(Y(L+(fsFV9PfX3c=H#WPD5RW`_4zh5-^f$_+=;x7shjQND(=Yt?N3ccW<_pNEDyeWaGPDrkKu?{kyx|!iXDlCyp0J9M?|7#+|9y3qx*x*++M80KIu`-zEW>_MsNZkai$6BqkV-piy1<4#uOP-Bdm_)&{Xj*F`Z KqGYlhhXnwrKonyD literal 2134 zcmcJQ$xg#C6h$de3PwT|uwsy+N)&|DhNNX^ccpX(8zjb!l{ijn;n0d zul;VPE(MaV2Dt*(#)QHzMQ!r$GmjSn6 zT8-Npo!7JlPKZ=kn4O!@{76>8y6lr!LA^T&3MiyFHvH2fbCrFtF|8s<(l?Z`i>1s$ ui|9n=EgXPNHR2K?o(?EUF|&!N-3R%tqh{^Z8LMv%fF6sSYmB&v%7r(88*{e+ diff --git a/lab2CA.sim/sim_1/impl/func/xsim/alu_tb.tcl b/lab2CA.sim/sim_1/impl/func/xsim/alu_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/impl/func/xsim/alu_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/impl/func/xsim/alu_tb_func_impl.v b/lab2CA.sim/sim_1/impl/func/xsim/alu_tb_func_impl.v new file mode 100644 index 0000000..0063fe7 --- /dev/null +++ b/lab2CA.sim/sim_1/impl/func/xsim/alu_tb_func_impl.v @@ -0,0 +1,927 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +// Date : Sat Feb 16 16:48:37 2019 +// Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +// Command : write_verilog -mode funcsim -nolib -force -file +// C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim/alu_tb_func_impl.v +// Design : RegFile +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k160tifbg484-2L +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* ECO_CHECKSUM = "b4d7812f" *) +(* NotValidForBitStream *) +module RegFile + (clk, + reset, + write_index, + op0_idx, + op1_idx, + write_data, + op0, + op1); + input clk; + input reset; + input [1:0]write_index; + input [1:0]op0_idx; + input [1:0]op1_idx; + input [8:0]write_data; + output [8:0]op0; + output [8:0]op1; + + wire clk; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire [8:0]op0; + wire [8:0]op0_OBUF; + wire \op0_OBUF[8]_inst_i_10_n_0 ; + wire \op0_OBUF[8]_inst_i_11_n_0 ; + wire \op0_OBUF[8]_inst_i_12_n_0 ; + wire \op0_OBUF[8]_inst_i_6_n_0 ; + wire \op0_OBUF[8]_inst_i_7_n_0 ; + wire \op0_OBUF[8]_inst_i_8_n_0 ; + wire \op0_OBUF[8]_inst_i_9_n_0 ; + wire [1:0]op0_idx; + wire [1:0]op0_idx_IBUF; + wire [8:0]op1; + wire [8:0]op1_OBUF; + wire [1:0]op1_idx; + wire [1:0]op1_idx_IBUF; + wire \r0/_n_0 ; + wire [8:0]r0_out; + wire [8:0]r1_out; + wire [8:0]r2_out; + wire [8:0]r3_out; + wire reset; + wire reset_IBUF; + wire [8:0]write_data; + wire [8:0]write_data_IBUF; + wire [1:0]write_index; + wire [1:0]write_index_IBUF; + + BUFG clk_IBUF_BUFG_inst + (.I(clk_IBUF), + .O(clk_IBUF_BUFG)); + IBUF clk_IBUF_inst + (.I(clk), + .O(clk_IBUF)); + mux_4_1 m0 + (.op0_OBUF(op0_OBUF), + .op0_idx_IBUF(op0_idx_IBUF), + .r0_out(r0_out), + .r1_out(r1_out), + .r2_out(r2_out), + .r3_out(r3_out)); + mux_4_1_0 m1 + (.op1_OBUF(op1_OBUF), + .op1_idx_IBUF(op1_idx_IBUF), + .r0_out(r0_out), + .r1_out(r1_out), + .r2_out(r2_out), + .r3_out(r3_out)); + OBUF \op0_OBUF[0]_inst + (.I(op0_OBUF[0]), + .O(op0[0])); + OBUF \op0_OBUF[1]_inst + (.I(op0_OBUF[1]), + .O(op0[1])); + OBUF \op0_OBUF[2]_inst + (.I(op0_OBUF[2]), + .O(op0[2])); + OBUF \op0_OBUF[3]_inst + (.I(op0_OBUF[3]), + .O(op0[3])); + OBUF \op0_OBUF[4]_inst + (.I(op0_OBUF[4]), + .O(op0[4])); + OBUF \op0_OBUF[5]_inst + (.I(op0_OBUF[5]), + .O(op0[5])); + OBUF \op0_OBUF[6]_inst + (.I(op0_OBUF[6]), + .O(op0[6])); + OBUF \op0_OBUF[7]_inst + (.I(op0_OBUF[7]), + .O(op0[7])); + OBUF \op0_OBUF[8]_inst + (.I(op0_OBUF[8]), + .O(op0[8])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT2 #( + .INIT(4'h4)) + \op0_OBUF[8]_inst_i_10 + (.I0(write_index_IBUF[0]), + .I1(write_index_IBUF[1]), + .O(\op0_OBUF[8]_inst_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[8]_inst_i_11 + (.I0(write_index_IBUF[0]), + .I1(write_index_IBUF[1]), + .O(\op0_OBUF[8]_inst_i_11_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h4)) + \op0_OBUF[8]_inst_i_12 + (.I0(write_index_IBUF[1]), + .I1(write_index_IBUF[0]), + .O(\op0_OBUF[8]_inst_i_12_n_0 )); + FDSE #( + .INIT(1'b1)) + \op0_OBUF[8]_inst_i_6 + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(\op0_OBUF[8]_inst_i_10_n_0 ), + .Q(\op0_OBUF[8]_inst_i_6_n_0 ), + .S(reset_IBUF)); + FDSE #( + .INIT(1'b1)) + \op0_OBUF[8]_inst_i_7 + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(\r0/_n_0 ), + .Q(\op0_OBUF[8]_inst_i_7_n_0 ), + .S(reset_IBUF)); + FDSE #( + .INIT(1'b1)) + \op0_OBUF[8]_inst_i_8 + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(\op0_OBUF[8]_inst_i_11_n_0 ), + .Q(\op0_OBUF[8]_inst_i_8_n_0 ), + .S(reset_IBUF)); + FDSE #( + .INIT(1'b1)) + \op0_OBUF[8]_inst_i_9 + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(\op0_OBUF[8]_inst_i_12_n_0 ), + .Q(\op0_OBUF[8]_inst_i_9_n_0 ), + .S(reset_IBUF)); + IBUF \op0_idx_IBUF[0]_inst + (.I(op0_idx[0]), + .O(op0_idx_IBUF[0])); + IBUF \op0_idx_IBUF[1]_inst + (.I(op0_idx[1]), + .O(op0_idx_IBUF[1])); + OBUF \op1_OBUF[0]_inst + (.I(op1_OBUF[0]), + .O(op1[0])); + OBUF \op1_OBUF[1]_inst + (.I(op1_OBUF[1]), + .O(op1[1])); + OBUF \op1_OBUF[2]_inst + (.I(op1_OBUF[2]), + .O(op1[2])); + OBUF \op1_OBUF[3]_inst + (.I(op1_OBUF[3]), + .O(op1[3])); + OBUF \op1_OBUF[4]_inst + (.I(op1_OBUF[4]), + .O(op1[4])); + OBUF \op1_OBUF[5]_inst + (.I(op1_OBUF[5]), + .O(op1[5])); + OBUF \op1_OBUF[6]_inst + (.I(op1_OBUF[6]), + .O(op1[6])); + OBUF \op1_OBUF[7]_inst + (.I(op1_OBUF[7]), + .O(op1[7])); + OBUF \op1_OBUF[8]_inst + (.I(op1_OBUF[8]), + .O(op1[8])); + IBUF \op1_idx_IBUF[0]_inst + (.I(op1_idx[0]), + .O(op1_idx_IBUF[0])); + IBUF \op1_idx_IBUF[1]_inst + (.I(op1_idx[1]), + .O(op1_idx_IBUF[1])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT2 #( + .INIT(4'h1)) + \r0/ + (.I0(write_index_IBUF[0]), + .I1(write_index_IBUF[1]), + .O(\r0/_n_0 )); + register r3 + (.clk_IBUF_BUFG(clk_IBUF_BUFG), + .\op0_OBUF[8]_inst_i_1 (\op0_OBUF[8]_inst_i_7_n_0 ), + .\op0_OBUF[8]_inst_i_1_0 (\op0_OBUF[8]_inst_i_6_n_0 ), + .\op0_OBUF[8]_inst_i_1_1 (\op0_OBUF[8]_inst_i_9_n_0 ), + .\op0_OBUF[8]_inst_i_1_2 (\op0_OBUF[8]_inst_i_8_n_0 ), + .r0_out(r0_out), + .r1_out(r1_out), + .r2_out(r2_out), + .r3_out(r3_out), + .reset_IBUF(reset_IBUF), + .write_data_IBUF(write_data_IBUF)); + IBUF reset_IBUF_inst + (.I(reset), + .O(reset_IBUF)); + IBUF \write_data_IBUF[0]_inst + (.I(write_data[0]), + .O(write_data_IBUF[0])); + IBUF \write_data_IBUF[1]_inst + (.I(write_data[1]), + .O(write_data_IBUF[1])); + IBUF \write_data_IBUF[2]_inst + (.I(write_data[2]), + .O(write_data_IBUF[2])); + IBUF \write_data_IBUF[3]_inst + (.I(write_data[3]), + .O(write_data_IBUF[3])); + IBUF \write_data_IBUF[4]_inst + (.I(write_data[4]), + .O(write_data_IBUF[4])); + IBUF \write_data_IBUF[5]_inst + (.I(write_data[5]), + .O(write_data_IBUF[5])); + IBUF \write_data_IBUF[6]_inst + (.I(write_data[6]), + .O(write_data_IBUF[6])); + IBUF \write_data_IBUF[7]_inst + (.I(write_data[7]), + .O(write_data_IBUF[7])); + IBUF \write_data_IBUF[8]_inst + (.I(write_data[8]), + .O(write_data_IBUF[8])); + IBUF \write_index_IBUF[0]_inst + (.I(write_index[0]), + .O(write_index_IBUF[0])); + IBUF \write_index_IBUF[1]_inst + (.I(write_index[1]), + .O(write_index_IBUF[1])); +endmodule + +module mux_4_1 + (op0_OBUF, + r1_out, + r0_out, + r3_out, + op0_idx_IBUF, + r2_out); + output [8:0]op0_OBUF; + input [8:0]r1_out; + input [8:0]r0_out; + input [8:0]r3_out; + input [1:0]op0_idx_IBUF; + input [8:0]r2_out; + + wire [8:0]op0_OBUF; + wire [1:0]op0_idx_IBUF; + wire [8:0]r0_out; + wire [8:0]r1_out; + wire [8:0]r2_out; + wire [8:0]r3_out; + + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[0]_inst_i_1 + (.I0(r1_out[0]), + .I1(r0_out[0]), + .I2(r3_out[0]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[0]), + .O(op0_OBUF[0])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[1]_inst_i_1 + (.I0(r1_out[1]), + .I1(r0_out[1]), + .I2(r3_out[1]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[1]), + .O(op0_OBUF[1])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[2]_inst_i_1 + (.I0(r1_out[2]), + .I1(r0_out[2]), + .I2(r3_out[2]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[2]), + .O(op0_OBUF[2])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[3]_inst_i_1 + (.I0(r1_out[3]), + .I1(r0_out[3]), + .I2(r3_out[3]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[3]), + .O(op0_OBUF[3])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[4]_inst_i_1 + (.I0(r1_out[4]), + .I1(r0_out[4]), + .I2(r3_out[4]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[4]), + .O(op0_OBUF[4])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[5]_inst_i_1 + (.I0(r1_out[5]), + .I1(r0_out[5]), + .I2(r3_out[5]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[5]), + .O(op0_OBUF[5])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[6]_inst_i_1 + (.I0(r1_out[6]), + .I1(r0_out[6]), + .I2(r3_out[6]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[6]), + .O(op0_OBUF[6])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[7]_inst_i_1 + (.I0(r1_out[7]), + .I1(r0_out[7]), + .I2(r3_out[7]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[7]), + .O(op0_OBUF[7])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[8]_inst_i_1 + (.I0(r1_out[8]), + .I1(r0_out[8]), + .I2(r3_out[8]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[8]), + .O(op0_OBUF[8])); +endmodule + +(* ORIG_REF_NAME = "mux_4_1" *) +module mux_4_1_0 + (op1_OBUF, + r1_out, + r0_out, + r3_out, + op1_idx_IBUF, + r2_out); + output [8:0]op1_OBUF; + input [8:0]r1_out; + input [8:0]r0_out; + input [8:0]r3_out; + input [1:0]op1_idx_IBUF; + input [8:0]r2_out; + + wire [8:0]op1_OBUF; + wire [1:0]op1_idx_IBUF; + wire [8:0]r0_out; + wire [8:0]r1_out; + wire [8:0]r2_out; + wire [8:0]r3_out; + + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[0]_inst_i_1 + (.I0(r1_out[0]), + .I1(r0_out[0]), + .I2(r3_out[0]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[0]), + .O(op1_OBUF[0])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[1]_inst_i_1 + (.I0(r1_out[1]), + .I1(r0_out[1]), + .I2(r3_out[1]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[1]), + .O(op1_OBUF[1])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[2]_inst_i_1 + (.I0(r1_out[2]), + .I1(r0_out[2]), + .I2(r3_out[2]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[2]), + .O(op1_OBUF[2])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[3]_inst_i_1 + (.I0(r1_out[3]), + .I1(r0_out[3]), + .I2(r3_out[3]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[3]), + .O(op1_OBUF[3])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[4]_inst_i_1 + (.I0(r1_out[4]), + .I1(r0_out[4]), + .I2(r3_out[4]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[4]), + .O(op1_OBUF[4])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[5]_inst_i_1 + (.I0(r1_out[5]), + .I1(r0_out[5]), + .I2(r3_out[5]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[5]), + .O(op1_OBUF[5])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[6]_inst_i_1 + (.I0(r1_out[6]), + .I1(r0_out[6]), + .I2(r3_out[6]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[6]), + .O(op1_OBUF[6])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[7]_inst_i_1 + (.I0(r1_out[7]), + .I1(r0_out[7]), + .I2(r3_out[7]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[7]), + .O(op1_OBUF[7])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[8]_inst_i_1 + (.I0(r1_out[8]), + .I1(r0_out[8]), + .I2(r3_out[8]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[8]), + .O(op1_OBUF[8])); +endmodule + +module register + (r0_out, + r1_out, + r2_out, + r3_out, + reset_IBUF, + write_data_IBUF, + clk_IBUF_BUFG, + \op0_OBUF[8]_inst_i_1 , + \op0_OBUF[8]_inst_i_1_0 , + \op0_OBUF[8]_inst_i_1_1 , + \op0_OBUF[8]_inst_i_1_2 ); + output [8:0]r0_out; + output [8:0]r1_out; + output [8:0]r2_out; + output [8:0]r3_out; + input reset_IBUF; + input [8:0]write_data_IBUF; + input clk_IBUF_BUFG; + input \op0_OBUF[8]_inst_i_1 ; + input \op0_OBUF[8]_inst_i_1_0 ; + input \op0_OBUF[8]_inst_i_1_1 ; + input \op0_OBUF[8]_inst_i_1_2 ; + + wire \Dout_tristate_oe_reg_n_0_[0] ; + wire \Dout_tristate_oe_reg_n_0_[1] ; + wire \Dout_tristate_oe_reg_n_0_[2] ; + wire \Dout_tristate_oe_reg_n_0_[3] ; + wire \Dout_tristate_oe_reg_n_0_[4] ; + wire \Dout_tristate_oe_reg_n_0_[5] ; + wire \Dout_tristate_oe_reg_n_0_[6] ; + wire \Dout_tristate_oe_reg_n_0_[7] ; + wire \Dout_tristate_oe_reg_n_0_[8] ; + wire clk_IBUF_BUFG; + wire \op0_OBUF[8]_inst_i_1 ; + wire \op0_OBUF[8]_inst_i_1_0 ; + wire \op0_OBUF[8]_inst_i_1_1 ; + wire \op0_OBUF[8]_inst_i_1_2 ; + wire [8:0]r0_out; + wire [8:0]r1_out; + wire [8:0]r2_out; + wire [8:0]r3_out; + wire reset_IBUF; + wire [8:0]write_data_IBUF; + + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[0] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[0]), + .Q(\Dout_tristate_oe_reg_n_0_[0] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[1] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[1]), + .Q(\Dout_tristate_oe_reg_n_0_[1] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[2] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[2]), + .Q(\Dout_tristate_oe_reg_n_0_[2] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[3] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[3]), + .Q(\Dout_tristate_oe_reg_n_0_[3] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[4] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[4]), + .Q(\Dout_tristate_oe_reg_n_0_[4] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[5] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[5]), + .Q(\Dout_tristate_oe_reg_n_0_[5] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[6] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[6]), + .Q(\Dout_tristate_oe_reg_n_0_[6] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[7] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[7]), + .Q(\Dout_tristate_oe_reg_n_0_[7] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[8] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[8]), + .Q(\Dout_tristate_oe_reg_n_0_[8] ), + .R(reset_IBUF)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[0]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[0] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[0])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[0]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[0] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[0])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[0]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[0] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[0])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[0]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[0] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[0])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[1]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[1] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[1]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[1] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[1])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[1]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[1] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[1])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[1]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[1] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[1])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[2]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[2] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[2])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[2]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[2] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[2])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[2]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[2] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[2])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[2]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[2] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[2])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[3]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[3] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[3])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[3]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[3] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[3])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[3]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[3] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[3])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[3]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[3] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[3])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[4]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[4] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[4])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[4]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[4] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[4])); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[4]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[4] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[4])); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[4]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[4] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[4])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[5]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[5] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[5])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[5]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[5] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[5])); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[5]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[5] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[5])); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[5]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[5] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[5])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[6]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[6] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[6])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[6]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[6] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[6])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[6]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[6] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[6])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[6]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[6] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[6])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[7]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[7] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[7])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[7]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[7] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[7])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[7]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[7] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[7])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[7]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[7] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[7])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[8]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[8] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[8])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[8]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[8] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[8])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[8]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[8] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[8])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[8]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[8] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[8])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/lab2CA.sim/sim_1/impl/func/xsim/alu_tb_vlog.prj b/lab2CA.sim/sim_1/impl/func/xsim/alu_tb_vlog.prj new file mode 100644 index 0000000..1388b93 --- /dev/null +++ b/lab2CA.sim/sim_1/impl/func/xsim/alu_tb_vlog.prj @@ -0,0 +1,8 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"alu_tb_func_impl.v" \ +"../../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ +"../../../../../lab2CA.srcs/sources_1/new/ALU.v" \ + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/impl/func/xsim/webtalk.jou b/lab2CA.sim/sim_1/impl/func/xsim/webtalk.jou new file mode 100644 index 0000000..81f53d6 --- /dev/null +++ b/lab2CA.sim/sim_1/impl/func/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Feb 16 16:48:49 2019 +# Process ID: 940 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/impl/func/xsim/xelab.pb b/lab2CA.sim/sim_1/impl/func/xsim/xelab.pb new file mode 100644 index 0000000000000000000000000000000000000000..4983d650ab2f723b1b2ae7db6e4522d35fc5ddc2 GIT binary patch literal 3142 zcmcgu+iue^7~V;nun?LwU}$2J1)DaFwauw*vMaWV3#7rt4hV4*If>I+a_ua3+U^y& z;thBy9tfxDikDGHRcTkLo#s3I2m1#MtnUlBFTm#7&Z=V?M^6OlXB0`ET6^^3vuCxB;tUI-ThX zyzlVjHYMGjgr?`VYNqFT$IvnivzDX7uY?jdI))!vScj*S!i)UB0$yN&(*cg^57~9n zUn}70MaCFm-IF`Fwr%Sgey)J;E1i=@!PF?6HwtTwfUri!hAB!C95sf7wVXO{j4(w( z9gi@q4JC&LYPyDv;|Mv9V>E-na)Tgt>;PF7b`2NSYJ`QUdPF$Lx=`LGBt%rLQw20q z&%T5ftewLVq5dS$lmz)s#)wLc@CR6Ze+~r>vlNp=eIpo3M2|~|Xy(hnk24nfq@U0d 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a/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/TempBreakPointFile.txt b/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/obj/xsim_1.c b/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/obj/xsim_1.c new file mode 100644 index 0000000..3366b7b --- /dev/null +++ b/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/obj/xsim_1.c @@ -0,0 +1,119 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_79(char*, char *); +extern void execute_181(char*, char *); +extern void execute_182(char*, char *); +extern void execute_183(char*, char *); +extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_180(char*, char *); +extern void execute_84(char*, char *); +extern void execute_85(char*, char *); +extern void execute_129(char*, char *); +extern void execute_102(char*, char *); +extern void execute_150(char*, char *); +extern void execute_159(char*, char *); +extern void execute_168(char*, char *); +extern void execute_177(char*, char *); +extern void execute_178(char*, char *); +extern void execute_78(char*, char *); +extern void execute_81(char*, char *); +extern void execute_82(char*, char *); +extern void execute_83(char*, char *); +extern void execute_184(char*, char *); +extern void execute_185(char*, char *); +extern void execute_186(char*, char *); +extern void execute_187(char*, char *); +extern void execute_188(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[25] = {(funcp)execute_79, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_180, (funcp)execute_84, (funcp)execute_85, (funcp)execute_129, (funcp)execute_102, (funcp)execute_150, (funcp)execute_159, (funcp)execute_168, (funcp)execute_177, (funcp)execute_178, (funcp)execute_78, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_184, (funcp)execute_185, (funcp)execute_186, (funcp)execute_187, (funcp)execute_188, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 25; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/alu_tb_func_impl/xsim.reloc", (void **)funcTab, 25); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/alu_tb_func_impl/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/alu_tb_func_impl/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/alu_tb_func_impl/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/alu_tb_func_impl/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/alu_tb_func_impl/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..9490939 --- /dev/null +++ b/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,54 @@ + + +
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+
+
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Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_time_impl.v b/lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_time_impl.v new file mode 100644 index 0000000..e03e300 --- /dev/null +++ b/lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_time_impl.v @@ -0,0 +1,931 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +// Date : Sat Feb 16 16:46:39 2019 +// Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file +// C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_time_impl.v +// Design : RegFile +// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or +// synthesized. Please ensure that this netlist is used with the corresponding SDF file. +// Device : xc7k160tifbg484-2L +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps +`define XIL_TIMING + +(* ECO_CHECKSUM = "b4d7812f" *) +(* NotValidForBitStream *) +module RegFile + (clk, + reset, + write_index, + op0_idx, + op1_idx, + write_data, + op0, + op1); + input clk; + input reset; + input [1:0]write_index; + input [1:0]op0_idx; + input [1:0]op1_idx; + input [8:0]write_data; + output [8:0]op0; + output [8:0]op1; + + wire clk; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire [8:0]op0; + wire [8:0]op0_OBUF; + wire \op0_OBUF[8]_inst_i_10_n_0 ; + wire \op0_OBUF[8]_inst_i_11_n_0 ; + wire \op0_OBUF[8]_inst_i_12_n_0 ; + wire \op0_OBUF[8]_inst_i_6_n_0 ; + wire \op0_OBUF[8]_inst_i_7_n_0 ; + wire \op0_OBUF[8]_inst_i_8_n_0 ; + wire \op0_OBUF[8]_inst_i_9_n_0 ; + wire [1:0]op0_idx; + wire [1:0]op0_idx_IBUF; + wire [8:0]op1; + wire [8:0]op1_OBUF; + wire [1:0]op1_idx; + wire [1:0]op1_idx_IBUF; + wire \r0/_n_0 ; + wire [8:0]r0_out; + wire [8:0]r1_out; + wire [8:0]r2_out; + wire [8:0]r3_out; + wire reset; + wire reset_IBUF; + wire [8:0]write_data; + wire [8:0]write_data_IBUF; + wire [1:0]write_index; + wire [1:0]write_index_IBUF; + +initial begin + $sdf_annotate("alu_tb_time_impl.sdf",,,,"tool_control"); +end + BUFG clk_IBUF_BUFG_inst + (.I(clk_IBUF), + .O(clk_IBUF_BUFG)); + IBUF clk_IBUF_inst + (.I(clk), + .O(clk_IBUF)); + mux_4_1 m0 + (.op0_OBUF(op0_OBUF), + .op0_idx_IBUF(op0_idx_IBUF), + .r0_out(r0_out), + .r1_out(r1_out), + .r2_out(r2_out), + .r3_out(r3_out)); + mux_4_1_0 m1 + (.op1_OBUF(op1_OBUF), + .op1_idx_IBUF(op1_idx_IBUF), + .r0_out(r0_out), + .r1_out(r1_out), + .r2_out(r2_out), + .r3_out(r3_out)); + OBUF \op0_OBUF[0]_inst + (.I(op0_OBUF[0]), + .O(op0[0])); + OBUF \op0_OBUF[1]_inst + (.I(op0_OBUF[1]), + .O(op0[1])); + OBUF \op0_OBUF[2]_inst + (.I(op0_OBUF[2]), + .O(op0[2])); + OBUF \op0_OBUF[3]_inst + (.I(op0_OBUF[3]), + .O(op0[3])); + OBUF \op0_OBUF[4]_inst + (.I(op0_OBUF[4]), + .O(op0[4])); + OBUF \op0_OBUF[5]_inst + (.I(op0_OBUF[5]), + .O(op0[5])); + OBUF \op0_OBUF[6]_inst + (.I(op0_OBUF[6]), + .O(op0[6])); + OBUF \op0_OBUF[7]_inst + (.I(op0_OBUF[7]), + .O(op0[7])); + OBUF \op0_OBUF[8]_inst + (.I(op0_OBUF[8]), + .O(op0[8])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT2 #( + .INIT(4'h4)) + \op0_OBUF[8]_inst_i_10 + (.I0(write_index_IBUF[0]), + .I1(write_index_IBUF[1]), + .O(\op0_OBUF[8]_inst_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[8]_inst_i_11 + (.I0(write_index_IBUF[0]), + .I1(write_index_IBUF[1]), + .O(\op0_OBUF[8]_inst_i_11_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h4)) + \op0_OBUF[8]_inst_i_12 + (.I0(write_index_IBUF[1]), + .I1(write_index_IBUF[0]), + .O(\op0_OBUF[8]_inst_i_12_n_0 )); + FDSE #( + .INIT(1'b1)) + \op0_OBUF[8]_inst_i_6 + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(\op0_OBUF[8]_inst_i_10_n_0 ), + .Q(\op0_OBUF[8]_inst_i_6_n_0 ), + .S(reset_IBUF)); + FDSE #( + .INIT(1'b1)) + \op0_OBUF[8]_inst_i_7 + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(\r0/_n_0 ), + .Q(\op0_OBUF[8]_inst_i_7_n_0 ), + .S(reset_IBUF)); + FDSE #( + .INIT(1'b1)) + \op0_OBUF[8]_inst_i_8 + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(\op0_OBUF[8]_inst_i_11_n_0 ), + .Q(\op0_OBUF[8]_inst_i_8_n_0 ), + .S(reset_IBUF)); + FDSE #( + .INIT(1'b1)) + \op0_OBUF[8]_inst_i_9 + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(\op0_OBUF[8]_inst_i_12_n_0 ), + .Q(\op0_OBUF[8]_inst_i_9_n_0 ), + .S(reset_IBUF)); + IBUF \op0_idx_IBUF[0]_inst + (.I(op0_idx[0]), + .O(op0_idx_IBUF[0])); + IBUF \op0_idx_IBUF[1]_inst + (.I(op0_idx[1]), + .O(op0_idx_IBUF[1])); + OBUF \op1_OBUF[0]_inst + (.I(op1_OBUF[0]), + .O(op1[0])); + OBUF \op1_OBUF[1]_inst + (.I(op1_OBUF[1]), + .O(op1[1])); + OBUF \op1_OBUF[2]_inst + (.I(op1_OBUF[2]), + .O(op1[2])); + OBUF \op1_OBUF[3]_inst + (.I(op1_OBUF[3]), + .O(op1[3])); + OBUF \op1_OBUF[4]_inst + (.I(op1_OBUF[4]), + .O(op1[4])); + OBUF \op1_OBUF[5]_inst + (.I(op1_OBUF[5]), + .O(op1[5])); + OBUF \op1_OBUF[6]_inst + (.I(op1_OBUF[6]), + .O(op1[6])); + OBUF \op1_OBUF[7]_inst + (.I(op1_OBUF[7]), + .O(op1[7])); + OBUF \op1_OBUF[8]_inst + (.I(op1_OBUF[8]), + .O(op1[8])); + IBUF \op1_idx_IBUF[0]_inst + (.I(op1_idx[0]), + .O(op1_idx_IBUF[0])); + IBUF \op1_idx_IBUF[1]_inst + (.I(op1_idx[1]), + .O(op1_idx_IBUF[1])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT2 #( + .INIT(4'h1)) + \r0/ + (.I0(write_index_IBUF[0]), + .I1(write_index_IBUF[1]), + .O(\r0/_n_0 )); + register r3 + (.clk_IBUF_BUFG(clk_IBUF_BUFG), + .\op0_OBUF[8]_inst_i_1 (\op0_OBUF[8]_inst_i_7_n_0 ), + .\op0_OBUF[8]_inst_i_1_0 (\op0_OBUF[8]_inst_i_6_n_0 ), + .\op0_OBUF[8]_inst_i_1_1 (\op0_OBUF[8]_inst_i_9_n_0 ), + .\op0_OBUF[8]_inst_i_1_2 (\op0_OBUF[8]_inst_i_8_n_0 ), + .r0_out(r0_out), + .r1_out(r1_out), + .r2_out(r2_out), + .r3_out(r3_out), + .reset_IBUF(reset_IBUF), + .write_data_IBUF(write_data_IBUF)); + IBUF reset_IBUF_inst + (.I(reset), + .O(reset_IBUF)); + IBUF \write_data_IBUF[0]_inst + (.I(write_data[0]), + .O(write_data_IBUF[0])); + IBUF \write_data_IBUF[1]_inst + (.I(write_data[1]), + .O(write_data_IBUF[1])); + IBUF \write_data_IBUF[2]_inst + (.I(write_data[2]), + .O(write_data_IBUF[2])); + IBUF \write_data_IBUF[3]_inst + (.I(write_data[3]), + .O(write_data_IBUF[3])); + IBUF \write_data_IBUF[4]_inst + (.I(write_data[4]), + .O(write_data_IBUF[4])); + IBUF \write_data_IBUF[5]_inst + (.I(write_data[5]), + .O(write_data_IBUF[5])); + IBUF \write_data_IBUF[6]_inst + (.I(write_data[6]), + .O(write_data_IBUF[6])); + IBUF \write_data_IBUF[7]_inst + (.I(write_data[7]), + .O(write_data_IBUF[7])); + IBUF \write_data_IBUF[8]_inst + (.I(write_data[8]), + .O(write_data_IBUF[8])); + IBUF \write_index_IBUF[0]_inst + (.I(write_index[0]), + .O(write_index_IBUF[0])); + IBUF \write_index_IBUF[1]_inst + (.I(write_index[1]), + .O(write_index_IBUF[1])); +endmodule + +module mux_4_1 + (op0_OBUF, + r1_out, + r0_out, + r3_out, + op0_idx_IBUF, + r2_out); + output [8:0]op0_OBUF; + input [8:0]r1_out; + input [8:0]r0_out; + input [8:0]r3_out; + input [1:0]op0_idx_IBUF; + input [8:0]r2_out; + + wire [8:0]op0_OBUF; + wire [1:0]op0_idx_IBUF; + wire [8:0]r0_out; + wire [8:0]r1_out; + wire [8:0]r2_out; + wire [8:0]r3_out; + + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[0]_inst_i_1 + (.I0(r1_out[0]), + .I1(r0_out[0]), + .I2(r3_out[0]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[0]), + .O(op0_OBUF[0])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[1]_inst_i_1 + (.I0(r1_out[1]), + .I1(r0_out[1]), + .I2(r3_out[1]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[1]), + .O(op0_OBUF[1])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[2]_inst_i_1 + (.I0(r1_out[2]), + .I1(r0_out[2]), + .I2(r3_out[2]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[2]), + .O(op0_OBUF[2])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[3]_inst_i_1 + (.I0(r1_out[3]), + .I1(r0_out[3]), + .I2(r3_out[3]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[3]), + .O(op0_OBUF[3])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[4]_inst_i_1 + (.I0(r1_out[4]), + .I1(r0_out[4]), + .I2(r3_out[4]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[4]), + .O(op0_OBUF[4])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[5]_inst_i_1 + (.I0(r1_out[5]), + .I1(r0_out[5]), + .I2(r3_out[5]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[5]), + .O(op0_OBUF[5])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[6]_inst_i_1 + (.I0(r1_out[6]), + .I1(r0_out[6]), + .I2(r3_out[6]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[6]), + .O(op0_OBUF[6])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[7]_inst_i_1 + (.I0(r1_out[7]), + .I1(r0_out[7]), + .I2(r3_out[7]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[7]), + .O(op0_OBUF[7])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op0_OBUF[8]_inst_i_1 + (.I0(r1_out[8]), + .I1(r0_out[8]), + .I2(r3_out[8]), + .I3(op0_idx_IBUF[1]), + .I4(op0_idx_IBUF[0]), + .I5(r2_out[8]), + .O(op0_OBUF[8])); +endmodule + +(* ORIG_REF_NAME = "mux_4_1" *) +module mux_4_1_0 + (op1_OBUF, + r1_out, + r0_out, + r3_out, + op1_idx_IBUF, + r2_out); + output [8:0]op1_OBUF; + input [8:0]r1_out; + input [8:0]r0_out; + input [8:0]r3_out; + input [1:0]op1_idx_IBUF; + input [8:0]r2_out; + + wire [8:0]op1_OBUF; + wire [1:0]op1_idx_IBUF; + wire [8:0]r0_out; + wire [8:0]r1_out; + wire [8:0]r2_out; + wire [8:0]r3_out; + + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[0]_inst_i_1 + (.I0(r1_out[0]), + .I1(r0_out[0]), + .I2(r3_out[0]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[0]), + .O(op1_OBUF[0])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[1]_inst_i_1 + (.I0(r1_out[1]), + .I1(r0_out[1]), + .I2(r3_out[1]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[1]), + .O(op1_OBUF[1])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[2]_inst_i_1 + (.I0(r1_out[2]), + .I1(r0_out[2]), + .I2(r3_out[2]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[2]), + .O(op1_OBUF[2])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[3]_inst_i_1 + (.I0(r1_out[3]), + .I1(r0_out[3]), + .I2(r3_out[3]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[3]), + .O(op1_OBUF[3])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[4]_inst_i_1 + (.I0(r1_out[4]), + .I1(r0_out[4]), + .I2(r3_out[4]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[4]), + .O(op1_OBUF[4])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[5]_inst_i_1 + (.I0(r1_out[5]), + .I1(r0_out[5]), + .I2(r3_out[5]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[5]), + .O(op1_OBUF[5])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[6]_inst_i_1 + (.I0(r1_out[6]), + .I1(r0_out[6]), + .I2(r3_out[6]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[6]), + .O(op1_OBUF[6])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[7]_inst_i_1 + (.I0(r1_out[7]), + .I1(r0_out[7]), + .I2(r3_out[7]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[7]), + .O(op1_OBUF[7])); + LUT6 #( + .INIT(64'hF0AAFFCCF0AA00CC)) + \op1_OBUF[8]_inst_i_1 + (.I0(r1_out[8]), + .I1(r0_out[8]), + .I2(r3_out[8]), + .I3(op1_idx_IBUF[1]), + .I4(op1_idx_IBUF[0]), + .I5(r2_out[8]), + .O(op1_OBUF[8])); +endmodule + +module register + (r0_out, + r1_out, + r2_out, + r3_out, + reset_IBUF, + write_data_IBUF, + clk_IBUF_BUFG, + \op0_OBUF[8]_inst_i_1 , + \op0_OBUF[8]_inst_i_1_0 , + \op0_OBUF[8]_inst_i_1_1 , + \op0_OBUF[8]_inst_i_1_2 ); + output [8:0]r0_out; + output [8:0]r1_out; + output [8:0]r2_out; + output [8:0]r3_out; + input reset_IBUF; + input [8:0]write_data_IBUF; + input clk_IBUF_BUFG; + input \op0_OBUF[8]_inst_i_1 ; + input \op0_OBUF[8]_inst_i_1_0 ; + input \op0_OBUF[8]_inst_i_1_1 ; + input \op0_OBUF[8]_inst_i_1_2 ; + + wire \Dout_tristate_oe_reg_n_0_[0] ; + wire \Dout_tristate_oe_reg_n_0_[1] ; + wire \Dout_tristate_oe_reg_n_0_[2] ; + wire \Dout_tristate_oe_reg_n_0_[3] ; + wire \Dout_tristate_oe_reg_n_0_[4] ; + wire \Dout_tristate_oe_reg_n_0_[5] ; + wire \Dout_tristate_oe_reg_n_0_[6] ; + wire \Dout_tristate_oe_reg_n_0_[7] ; + wire \Dout_tristate_oe_reg_n_0_[8] ; + wire clk_IBUF_BUFG; + wire \op0_OBUF[8]_inst_i_1 ; + wire \op0_OBUF[8]_inst_i_1_0 ; + wire \op0_OBUF[8]_inst_i_1_1 ; + wire \op0_OBUF[8]_inst_i_1_2 ; + wire [8:0]r0_out; + wire [8:0]r1_out; + wire [8:0]r2_out; + wire [8:0]r3_out; + wire reset_IBUF; + wire [8:0]write_data_IBUF; + + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[0] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[0]), + .Q(\Dout_tristate_oe_reg_n_0_[0] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[1] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[1]), + .Q(\Dout_tristate_oe_reg_n_0_[1] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[2] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[2]), + .Q(\Dout_tristate_oe_reg_n_0_[2] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[3] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[3]), + .Q(\Dout_tristate_oe_reg_n_0_[3] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[4] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[4]), + .Q(\Dout_tristate_oe_reg_n_0_[4] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[5] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[5]), + .Q(\Dout_tristate_oe_reg_n_0_[5] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[6] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[6]), + .Q(\Dout_tristate_oe_reg_n_0_[6] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[7] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[7]), + .Q(\Dout_tristate_oe_reg_n_0_[7] ), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_tristate_oe_reg[8] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(write_data_IBUF[8]), + .Q(\Dout_tristate_oe_reg_n_0_[8] ), + .R(reset_IBUF)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[0]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[0] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[0])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[0]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[0] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[0])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[0]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[0] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[0])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[0]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[0] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[0])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[1]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[1] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[1]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[1] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[1])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[1]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[1] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[1])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[1]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[1] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[1])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[2]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[2] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[2])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[2]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[2] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[2])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[2]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[2] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[2])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[2]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[2] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[2])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[3]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[3] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[3])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[3]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[3] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[3])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[3]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[3] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[3])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[3]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[3] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[3])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[4]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[4] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[4])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[4]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[4] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[4])); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[4]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[4] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[4])); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[4]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[4] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[4])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[5]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[5] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[5])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[5]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[5] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[5])); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[5]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[5] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[5])); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[5]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[5] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[5])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[6]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[6] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[6])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[6]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[6] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[6])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[6]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[6] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[6])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[6]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[6] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[6])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[7]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[7] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[7])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[7]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[7] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[7])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[7]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[7] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[7])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[7]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[7] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[7])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[8]_inst_i_2 + (.I0(\Dout_tristate_oe_reg_n_0_[8] ), + .I1(\op0_OBUF[8]_inst_i_1_0 ), + .O(r1_out[8])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[8]_inst_i_3 + (.I0(\Dout_tristate_oe_reg_n_0_[8] ), + .I1(\op0_OBUF[8]_inst_i_1 ), + .O(r0_out[8])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[8]_inst_i_4 + (.I0(\Dout_tristate_oe_reg_n_0_[8] ), + .I1(\op0_OBUF[8]_inst_i_1_2 ), + .O(r3_out[8])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT2 #( + .INIT(4'h8)) + \op0_OBUF[8]_inst_i_5 + (.I0(\Dout_tristate_oe_reg_n_0_[8] ), + .I1(\op0_OBUF[8]_inst_i_1_1 ), + .O(r2_out[8])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_vlog.prj b/lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_vlog.prj new file mode 100644 index 0000000..7eaa715 --- /dev/null +++ b/lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_vlog.prj @@ -0,0 +1,8 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"alu_tb_time_impl.v" \ +"../../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ +"../../../../../lab2CA.srcs/sources_1/new/ALU.v" \ + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb.tcl b/lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_time_impl.v b/lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_time_impl.v new file mode 100644 index 0000000..2bcaec9 --- /dev/null +++ b/lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_time_impl.v @@ -0,0 +1,463 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +// Date : Sat Feb 16 17:29:30 2019 +// Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file +// C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_time_impl.v +// Design : FetchUnit +// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or +// synthesized. Please ensure that this netlist is used with the corresponding SDF file. +// Device : xc7k160tifbg484-2L +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps +`define XIL_TIMING + +(* ECO_CHECKSUM = "fb52d5c" *) +(* NotValidForBitStream *) +module FetchUnit + (clk, + reset, + op_idx, + AddrIn, + AddrOut); + input clk; + input reset; + input op_idx; + input [8:0]AddrIn; + output [8:0]AddrOut; + + wire [8:0]AddrIn; + wire [8:0]AddrIn_IBUF; + wire [8:0]AddrOut; + wire [8:0]AddrOut_OBUF; + wire clk; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire op_idx; + wire op_idx_IBUF; + wire reset; + wire reset_IBUF; + +initial begin + $sdf_annotate("regFile_tb_time_impl.sdf",,,,"tool_control"); +end + IBUF \AddrIn_IBUF[0]_inst + (.I(AddrIn[0]), + .O(AddrIn_IBUF[0])); + IBUF \AddrIn_IBUF[1]_inst + (.I(AddrIn[1]), + .O(AddrIn_IBUF[1])); + IBUF \AddrIn_IBUF[2]_inst + (.I(AddrIn[2]), + .O(AddrIn_IBUF[2])); + IBUF \AddrIn_IBUF[3]_inst + (.I(AddrIn[3]), + .O(AddrIn_IBUF[3])); + IBUF \AddrIn_IBUF[4]_inst + (.I(AddrIn[4]), + .O(AddrIn_IBUF[4])); + IBUF \AddrIn_IBUF[5]_inst + (.I(AddrIn[5]), + .O(AddrIn_IBUF[5])); + IBUF \AddrIn_IBUF[6]_inst + (.I(AddrIn[6]), + .O(AddrIn_IBUF[6])); + IBUF \AddrIn_IBUF[7]_inst + (.I(AddrIn[7]), + .O(AddrIn_IBUF[7])); + IBUF \AddrIn_IBUF[8]_inst + (.I(AddrIn[8]), + .O(AddrIn_IBUF[8])); + OBUF \AddrOut_OBUF[0]_inst + (.I(AddrOut_OBUF[0]), + .O(AddrOut[0])); + OBUF \AddrOut_OBUF[1]_inst + (.I(AddrOut_OBUF[1]), + .O(AddrOut[1])); + OBUF \AddrOut_OBUF[2]_inst + (.I(AddrOut_OBUF[2]), + .O(AddrOut[2])); + OBUF \AddrOut_OBUF[3]_inst + (.I(AddrOut_OBUF[3]), + .O(AddrOut[3])); + OBUF \AddrOut_OBUF[4]_inst + (.I(AddrOut_OBUF[4]), + .O(AddrOut[4])); + OBUF \AddrOut_OBUF[5]_inst + (.I(AddrOut_OBUF[5]), + .O(AddrOut[5])); + OBUF \AddrOut_OBUF[6]_inst + (.I(AddrOut_OBUF[6]), + .O(AddrOut[6])); + OBUF \AddrOut_OBUF[7]_inst + (.I(AddrOut_OBUF[7]), + .O(AddrOut[7])); + OBUF \AddrOut_OBUF[8]_inst + (.I(AddrOut_OBUF[8]), + .O(AddrOut[8])); + register PC + (.AddrIn_IBUF(AddrIn_IBUF), + .AddrOut_OBUF(AddrOut_OBUF), + .clk_IBUF_BUFG(clk_IBUF_BUFG), + .op_idx_IBUF(op_idx_IBUF), + .reset_IBUF(reset_IBUF)); + BUFG clk_IBUF_BUFG_inst + (.I(clk_IBUF), + .O(clk_IBUF_BUFG)); + IBUF clk_IBUF_inst + (.I(clk), + .O(clk_IBUF)); + IBUF op_idx_IBUF_inst + (.I(op_idx), + .O(op_idx_IBUF)); + IBUF reset_IBUF_inst + (.I(reset), + .O(reset_IBUF)); +endmodule + +module register + (AddrOut_OBUF, + reset_IBUF, + clk_IBUF_BUFG, + op_idx_IBUF, + AddrIn_IBUF); + output [8:0]AddrOut_OBUF; + input reset_IBUF; + input clk_IBUF_BUFG; + input op_idx_IBUF; + input [8:0]AddrIn_IBUF; + + wire [8:0]AddrIn_IBUF; + wire [8:0]AddrOut_OBUF; + wire \AddrOut_OBUF[8]_inst_i_2_n_0 ; + wire \Dout[8]_i_2_n_0 ; + wire clk_IBUF_BUFG; + wire op_idx_IBUF; + wire [8:0]out; + wire [8:0]progC_out; + wire reset_IBUF; + + LUT1 #( + .INIT(2'h1)) + \AddrOut_OBUF[0]_inst_i_1 + (.I0(progC_out[0]), + .O(AddrOut_OBUF[0])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h6)) + \AddrOut_OBUF[1]_inst_i_1 + (.I0(progC_out[0]), + .I1(progC_out[1]), + .O(AddrOut_OBUF[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'h6A)) + \AddrOut_OBUF[2]_inst_i_1 + (.I0(progC_out[2]), + .I1(progC_out[0]), + .I2(progC_out[1]), + .O(AddrOut_OBUF[2])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'h7F80)) + \AddrOut_OBUF[3]_inst_i_1 + (.I0(progC_out[1]), + .I1(progC_out[0]), + .I2(progC_out[2]), + .I3(progC_out[3]), + .O(AddrOut_OBUF[3])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h6AAAAAAA)) + \AddrOut_OBUF[4]_inst_i_1 + (.I0(progC_out[4]), + .I1(progC_out[1]), + .I2(progC_out[0]), + .I3(progC_out[2]), + .I4(progC_out[3]), + .O(AddrOut_OBUF[4])); + LUT6 #( + .INIT(64'h6AAAAAAAAAAAAAAA)) + \AddrOut_OBUF[5]_inst_i_1 + (.I0(progC_out[5]), + .I1(progC_out[3]), + .I2(progC_out[2]), + .I3(progC_out[0]), + .I4(progC_out[1]), + .I5(progC_out[4]), + .O(AddrOut_OBUF[5])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'h6AAA)) + \AddrOut_OBUF[6]_inst_i_1 + (.I0(progC_out[6]), + .I1(progC_out[4]), + .I2(\AddrOut_OBUF[8]_inst_i_2_n_0 ), + .I3(progC_out[5]), + .O(AddrOut_OBUF[6])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h6AAAAAAA)) + \AddrOut_OBUF[7]_inst_i_1 + (.I0(progC_out[7]), + .I1(progC_out[5]), + .I2(\AddrOut_OBUF[8]_inst_i_2_n_0 ), + .I3(progC_out[4]), + .I4(progC_out[6]), + .O(AddrOut_OBUF[7])); + LUT6 #( + .INIT(64'h6AAAAAAAAAAAAAAA)) + \AddrOut_OBUF[8]_inst_i_1 + (.I0(progC_out[8]), + .I1(progC_out[6]), + .I2(progC_out[4]), + .I3(\AddrOut_OBUF[8]_inst_i_2_n_0 ), + .I4(progC_out[5]), + .I5(progC_out[7]), + .O(AddrOut_OBUF[8])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h8000)) + \AddrOut_OBUF[8]_inst_i_2 + (.I0(progC_out[3]), + .I1(progC_out[2]), + .I2(progC_out[0]), + .I3(progC_out[1]), + .O(\AddrOut_OBUF[8]_inst_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h74)) + \Dout[0]_i_1 + (.I0(progC_out[0]), + .I1(op_idx_IBUF), + .I2(AddrIn_IBUF[0]), + .O(out[0])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h6F60)) + \Dout[1]_i_1 + (.I0(progC_out[0]), + .I1(progC_out[1]), + .I2(op_idx_IBUF), + .I3(AddrIn_IBUF[1]), + .O(out[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h6AFF6A00)) + \Dout[2]_i_1 + (.I0(progC_out[2]), + .I1(progC_out[0]), + .I2(progC_out[1]), + .I3(op_idx_IBUF), + .I4(AddrIn_IBUF[2]), + .O(out[2])); + LUT6 #( + .INIT(64'h7F80FFFF7F800000)) + \Dout[3]_i_1 + (.I0(progC_out[1]), + .I1(progC_out[0]), + .I2(progC_out[2]), + .I3(progC_out[3]), + .I4(op_idx_IBUF), + .I5(AddrIn_IBUF[3]), + .O(out[3])); + LUT4 #( + .INIT(16'h6F60)) + \Dout[4]_i_1 + (.I0(progC_out[4]), + .I1(\AddrOut_OBUF[8]_inst_i_2_n_0 ), + .I2(op_idx_IBUF), + .I3(AddrIn_IBUF[4]), + .O(out[4])); + LUT5 #( + .INIT(32'h6AFF6A00)) + \Dout[5]_i_1 + (.I0(progC_out[5]), + .I1(\AddrOut_OBUF[8]_inst_i_2_n_0 ), + .I2(progC_out[4]), + .I3(op_idx_IBUF), + .I4(AddrIn_IBUF[5]), + .O(out[5])); + LUT6 #( + .INIT(64'h6AAAFFFF6AAA0000)) + \Dout[6]_i_1 + (.I0(progC_out[6]), + .I1(progC_out[4]), + .I2(\AddrOut_OBUF[8]_inst_i_2_n_0 ), + .I3(progC_out[5]), + .I4(op_idx_IBUF), + .I5(AddrIn_IBUF[6]), + .O(out[6])); + LUT5 #( + .INIT(32'h6AFF6A00)) + \Dout[7]_i_1 + (.I0(progC_out[7]), + .I1(\Dout[8]_i_2_n_0 ), + .I2(progC_out[6]), + .I3(op_idx_IBUF), + .I4(AddrIn_IBUF[7]), + .O(out[7])); + LUT6 #( + .INIT(64'h6AAAFFFF6AAA0000)) + \Dout[8]_i_1 + (.I0(progC_out[8]), + .I1(progC_out[6]), + .I2(\Dout[8]_i_2_n_0 ), + .I3(progC_out[7]), + .I4(op_idx_IBUF), + .I5(AddrIn_IBUF[8]), + .O(out[8])); + LUT6 #( + .INIT(64'h8000000000000000)) + \Dout[8]_i_2 + (.I0(progC_out[5]), + .I1(progC_out[3]), + .I2(progC_out[2]), + .I3(progC_out[0]), + .I4(progC_out[1]), + .I5(progC_out[4]), + .O(\Dout[8]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \Dout_reg[0] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(out[0]), + .Q(progC_out[0]), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_reg[1] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(out[1]), + .Q(progC_out[1]), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_reg[2] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(out[2]), + .Q(progC_out[2]), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_reg[3] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(out[3]), + .Q(progC_out[3]), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_reg[4] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(out[4]), + .Q(progC_out[4]), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_reg[5] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(out[5]), + .Q(progC_out[5]), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_reg[6] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(out[6]), + .Q(progC_out[6]), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_reg[7] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(out[7]), + .Q(progC_out[7]), + .R(reset_IBUF)); + FDRE #( + .INIT(1'b0)) + \Dout_reg[8] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .D(out[8]), + .Q(progC_out[8]), + .R(reset_IBUF)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_vlog.prj b/lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_vlog.prj new file mode 100644 index 0000000..f20f47b --- /dev/null +++ b/lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_vlog.prj @@ -0,0 +1,8 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"regFile_tb_time_impl.v" \ +"../../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ +"../../../../../lab2CA.srcs/sources_1/new/RegFile.v" \ + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.jou b/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.jou index e01861d..e86cd13 100644 --- a/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.jou +++ b/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Fri Feb 15 12:37:49 2019 -# Process ID: 17624 -# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log -# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou +# Start of session at: Sat Feb 16 17:29:42 2019 +# Process ID: 9128 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/regFile_tb_time_impl/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/JoseIgnacio/CA -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/regFile_tb_time_impl/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/webtalk_12684.backup.jou b/lab2CA.sim/sim_1/impl/timing/xsim/webtalk_12684.backup.jou new file mode 100644 index 0000000..717b45d --- /dev/null +++ b/lab2CA.sim/sim_1/impl/timing/xsim/webtalk_12684.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Feb 16 16:46:35 2019 +# Process ID: 12684 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/webtalk_17624.backup.jou b/lab2CA.sim/sim_1/impl/timing/xsim/webtalk_17624.backup.jou new file mode 100644 index 0000000..e01861d --- /dev/null +++ b/lab2CA.sim/sim_1/impl/timing/xsim/webtalk_17624.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Fri Feb 15 12:37:49 2019 +# Process ID: 17624 +# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log +# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/JoseIgnacio/CA -notrace diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/webtalk_6004.backup.jou b/lab2CA.sim/sim_1/impl/timing/xsim/webtalk_6004.backup.jou new file mode 100644 index 0000000..b0fb309 --- /dev/null +++ b/lab2CA.sim/sim_1/impl/timing/xsim/webtalk_6004.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Feb 16 16:44:18 2019 +# Process ID: 6004 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/xelab.pb b/lab2CA.sim/sim_1/impl/timing/xsim/xelab.pb index 938982491a11c89ee93dfd6a861d596838c34b7b..3f9f95058a9f7406776eac259197be37f82fe563 100644 GIT binary patch delta 180 zcmdnVzld+b3&u?oUn;TuW#W1IqnwD6aQ<9UJqzBZHSzMA@GYL0R1vP?EnA( delta 466 zcmZ3)x08Ru3&u4QUn;SDXX1J^nV<0_dr)e+TV_t`nl8!=J zevv{^etwBUZhlHBRFq4ARf^fz*i?(NI5W32C$S{I$Vih*6l!&RNoH9I&&9cc~dZm#QK=6|YM +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_79(char*, char *); +extern void execute_181(char*, char *); +extern void execute_182(char*, char *); +extern void execute_183(char*, char *); +extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_180(char*, char *); +extern void execute_84(char*, char *); +extern void execute_85(char*, char *); +extern void execute_129(char*, char *); +extern void execute_102(char*, char *); +extern void execute_150(char*, char *); +extern void execute_159(char*, char *); +extern void execute_168(char*, char *); +extern void execute_177(char*, char *); +extern void execute_178(char*, char *); +extern void execute_78(char*, char *); +extern void execute_81(char*, char *); +extern void execute_82(char*, char *); +extern void execute_83(char*, char *); +extern void execute_184(char*, char *); +extern void execute_185(char*, char *); +extern void execute_186(char*, char *); +extern void execute_187(char*, char *); +extern void execute_188(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[25] = {(funcp)execute_79, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_180, (funcp)execute_84, (funcp)execute_85, (funcp)execute_129, (funcp)execute_102, (funcp)execute_150, (funcp)execute_159, (funcp)execute_168, (funcp)execute_177, (funcp)execute_178, (funcp)execute_78, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_184, (funcp)execute_185, (funcp)execute_186, (funcp)execute_187, (funcp)execute_188, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 25; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/alu_tb_time_impl/xsim.reloc", (void **)funcTab, 25); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/alu_tb_time_impl/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/alu_tb_time_impl/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/alu_tb_time_impl/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/alu_tb_time_impl/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/alu_tb_time_impl/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..9a09bdf --- /dev/null +++ b/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+ diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..e5cac4d --- /dev/null +++ b/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/xsim_webtalk.tcl @@ -0,0 +1,42 @@ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Feb 16 16:46:45 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "3" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data 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+/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_2(char*, char *); +extern void execute_3(char*, char *); +extern void execute_17(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void execute_33(char*, char *); +extern void execute_34(char*, char *); +extern void execute_35(char*, char *); +extern void execute_36(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_6(char*, char *); +extern void execute_14(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_37(char*, char *); +extern void execute_38(char*, char *); +extern void execute_39(char*, char *); +extern void execute_40(char*, char *); +extern void execute_41(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +extern void transaction_10(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[30] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_17, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_6, (funcp)execute_14, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_10}; +const int NumRelocateId= 30; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/regFile_tb_time_impl/xsim.reloc", (void **)funcTab, 30); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/regFile_tb_time_impl/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/regFile_tb_time_impl/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/regFile_tb_time_impl/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/regFile_tb_time_impl/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/regFile_tb_time_impl/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/regFile_tb_time_impl/webtalk/usage_statistics_ext_xsim.xml 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