From 5cbe490aaecbc8d901fadba344a5eabaf32fd738 Mon Sep 17 00:00:00 2001
From: "jose.rodriguezlabra" <jkz5178@wmich.edu>
Date: Sat, 16 Mar 2019 14:01:32 -0400
Subject: [PATCH] Added link instruction

---
 CPU9bits_tb_behav.wcfg                        | 111 ++++++++++++++++++
 lab2CA.sim/sim_1/behav/xsim/webtalk.jou       |   4 +-
 ...08.backup.jou => webtalk_14664.backup.jou} |   6 +-
 ...968.backup.jou => webtalk_4744.backup.jou} |   6 +-
 .../xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c   |  60 +++++-----
 .../webtalk/xsim_webtalk.tcl                  |  28 +++--
 .../xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem  | Bin 15344 -> 15739 bytes
 lab2CA.srcs/sources_1/new/CPU9bits.v          |  36 ++++--
 lab2CA.srcs/sources_1/new/ControlUnit.v       |  30 ++++-
 lab2CA.xpr                                    |   5 +-
 10 files changed, 225 insertions(+), 61 deletions(-)
 create mode 100644 CPU9bits_tb_behav.wcfg
 rename lab2CA.sim/sim_1/behav/xsim/{webtalk_12808.backup.jou => webtalk_14664.backup.jou} (77%)
 rename lab2CA.sim/sim_1/behav/xsim/{webtalk_17968.backup.jou => webtalk_4744.backup.jou} (77%)

diff --git a/CPU9bits_tb_behav.wcfg b/CPU9bits_tb_behav.wcfg
new file mode 100644
index 0000000..033cbe2
--- /dev/null
+++ b/CPU9bits_tb_behav.wcfg
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="CPU9bits_tb_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="CPU9bits_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0fs"></ZoomStartTime>
+      <ZoomEndTime time="80000001fs"></ZoomEndTime>
+      <Cursor1Time time="80000000fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="127"></NameColumnWidth>
+      <ValueColumnWidth column_width="128"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="22" />
+   <wvobject fp_name="/CPU9bits_tb/instruction" type="array">
+      <obj_property name="ElementShortName">instruction[8:0]</obj_property>
+      <obj_property name="ObjectShortName">instruction[8:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/clk" type="logic">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/done" type="logic">
+      <obj_property name="ElementShortName">done</obj_property>
+      <obj_property name="ObjectShortName">done</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/reset" type="logic">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/enable" type="logic">
+      <obj_property name="ElementShortName">enable</obj_property>
+      <obj_property name="ObjectShortName">enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/write_index" type="array">
+      <obj_property name="ElementShortName">write_index[1:0]</obj_property>
+      <obj_property name="ObjectShortName">write_index[1:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/op0_idx" type="array">
+      <obj_property name="ElementShortName">op0_idx[1:0]</obj_property>
+      <obj_property name="ObjectShortName">op0_idx[1:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/op1_idx" type="array">
+      <obj_property name="ElementShortName">op1_idx[1:0]</obj_property>
+      <obj_property name="ObjectShortName">op1_idx[1:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/write_data" type="array">
+      <obj_property name="ElementShortName">write_data[8:0]</obj_property>
+      <obj_property name="ObjectShortName">write_data[8:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/op0" type="array">
+      <obj_property name="ElementShortName">op0[8:0]</obj_property>
+      <obj_property name="ObjectShortName">op0[8:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/op1" type="array">
+      <obj_property name="ElementShortName">op1[8:0]</obj_property>
+      <obj_property name="ObjectShortName">op1[8:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/decOut" type="array">
+      <obj_property name="ElementShortName">decOut[3:0]</obj_property>
+      <obj_property name="ObjectShortName">decOut[3:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r0_out" type="array">
+      <obj_property name="ElementShortName">r0_out[8:0]</obj_property>
+      <obj_property name="ObjectShortName">r0_out[8:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r1_out" type="array">
+      <obj_property name="ElementShortName">r1_out[8:0]</obj_property>
+      <obj_property name="ObjectShortName">r1_out[8:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r2_out" type="array">
+      <obj_property name="ElementShortName">r2_out[8:0]</obj_property>
+      <obj_property name="ObjectShortName">r2_out[8:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r3_out" type="array">
+      <obj_property name="ElementShortName">r3_out[8:0]</obj_property>
+      <obj_property name="ObjectShortName">r3_out[8:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/op_idx" type="logic">
+      <obj_property name="ElementShortName">op_idx</obj_property>
+      <obj_property name="ObjectShortName">op_idx</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/AddrIn" type="array">
+      <obj_property name="ElementShortName">AddrIn[8:0]</obj_property>
+      <obj_property name="ObjectShortName">AddrIn[8:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/AddrOut" type="array">
+      <obj_property name="ElementShortName">AddrOut[8:0]</obj_property>
+      <obj_property name="ObjectShortName">AddrOut[8:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/progC_out" type="array">
+      <obj_property name="ElementShortName">progC_out[8:0]</obj_property>
+      <obj_property name="ObjectShortName">progC_out[8:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/result_m" type="array">
+      <obj_property name="ElementShortName">result_m[8:0]</obj_property>
+      <obj_property name="ObjectShortName">result_m[8:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/cout" type="logic">
+      <obj_property name="ElementShortName">cout</obj_property>
+      <obj_property name="ObjectShortName">cout</obj_property>
+   </wvobject>
+</wave_config>
diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou
index eb52ade..d81d9af 100644
--- a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou
+++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou
@@ -2,8 +2,8 @@
 # Webtalk v2018.3 (64-bit)
 # SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 # IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
-# Start of session at: Thu Mar 14 14:24:20 2019
-# Process ID: 14664
+# Start of session at: Sat Mar 16 13:34:35 2019
+# Process ID: 4680
 # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim
 # Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
 # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_12808.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_14664.backup.jou
similarity index 77%
rename from lab2CA.sim/sim_1/behav/xsim/webtalk_12808.backup.jou
rename to lab2CA.sim/sim_1/behav/xsim/webtalk_14664.backup.jou
index cd841e1..eb52ade 100644
--- a/lab2CA.sim/sim_1/behav/xsim/webtalk_12808.backup.jou
+++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_14664.backup.jou
@@ -2,10 +2,10 @@
 # Webtalk v2018.3 (64-bit)
 # SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 # IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
-# Start of session at: Wed Mar 13 11:21:19 2019
-# Process ID: 12808
+# Start of session at: Thu Mar 14 14:24:20 2019
+# Process ID: 14664
 # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim
-# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace
+# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
 # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
 # Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
 #-----------------------------------------------------------
diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_17968.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_4744.backup.jou
similarity index 77%
rename from lab2CA.sim/sim_1/behav/xsim/webtalk_17968.backup.jou
rename to lab2CA.sim/sim_1/behav/xsim/webtalk_4744.backup.jou
index f19d8f7..03fe54d 100644
--- a/lab2CA.sim/sim_1/behav/xsim/webtalk_17968.backup.jou
+++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_4744.backup.jou
@@ -2,10 +2,10 @@
 # Webtalk v2018.3 (64-bit)
 # SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 # IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
-# Start of session at: Wed Mar 13 11:20:32 2019
-# Process ID: 17968
+# Start of session at: Sat Mar 16 12:09:51 2019
+# Process ID: 4744
 # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim
-# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace
+# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
 # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
 # Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
 #-----------------------------------------------------------
diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c
index e13ebca..ae6a047 100644
--- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c
+++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c
@@ -46,16 +46,14 @@ typedef void (*funcp)(char *, char *);
 extern int main(int, char**);
 extern void execute_2(char*, char *);
 extern void execute_3(char*, char *);
-extern void execute_135(char*, char *);
-extern void execute_332(char*, char *);
-extern void execute_333(char*, char *);
-extern void execute_334(char*, char *);
+extern void execute_137(char*, char *);
+extern void execute_336(char*, char *);
+extern void execute_337(char*, char *);
+extern void execute_338(char*, char *);
 extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
-extern void execute_316(char*, char *);
-extern void execute_317(char*, char *);
 extern void execute_318(char*, char *);
+extern void execute_319(char*, char *);
 extern void execute_320(char*, char *);
-extern void execute_321(char*, char *);
 extern void execute_322(char*, char *);
 extern void execute_323(char*, char *);
 extern void execute_324(char*, char *);
@@ -66,51 +64,55 @@ extern void execute_328(char*, char *);
 extern void execute_329(char*, char *);
 extern void execute_330(char*, char *);
 extern void execute_331(char*, char *);
-extern void execute_140(char*, char *);
-extern void execute_141(char*, char *);
+extern void execute_332(char*, char *);
+extern void execute_333(char*, char *);
+extern void execute_334(char*, char *);
+extern void execute_335(char*, char *);
 extern void execute_142(char*, char *);
 extern void execute_143(char*, char *);
 extern void execute_144(char*, char *);
 extern void execute_145(char*, char *);
 extern void execute_146(char*, char *);
+extern void execute_147(char*, char *);
+extern void execute_148(char*, char *);
 extern void execute_7(char*, char *);
 extern void execute_9(char*, char *);
 extern void execute_17(char*, char *);
-extern void execute_166(char*, char *);
 extern void execute_168(char*, char *);
-extern void execute_169(char*, char *);
-extern void execute_147(char*, char *);
-extern void execute_148(char*, char *);
+extern void execute_170(char*, char *);
+extern void execute_171(char*, char *);
+extern void execute_149(char*, char *);
+extern void execute_150(char*, char *);
 extern void execute_34(char*, char *);
-extern void execute_278(char*, char *);
-extern void execute_207(char*, char *);
-extern void execute_188(char*, char *);
-extern void execute_228(char*, char *);
-extern void execute_229(char*, char *);
+extern void execute_280(char*, char *);
+extern void execute_209(char*, char *);
+extern void execute_190(char*, char *);
 extern void execute_230(char*, char *);
 extern void execute_231(char*, char *);
 extern void execute_232(char*, char *);
 extern void execute_233(char*, char *);
-extern void execute_275(char*, char *);
-extern void execute_276(char*, char *);
+extern void execute_234(char*, char *);
+extern void execute_235(char*, char *);
+extern void execute_277(char*, char *);
+extern void execute_278(char*, char *);
 extern void execute_102(char*, char *);
 extern void execute_104(char*, char *);
 extern void execute_120(char*, char *);
-extern void execute_137(char*, char *);
-extern void execute_138(char*, char *);
 extern void execute_139(char*, char *);
-extern void execute_335(char*, char *);
-extern void execute_336(char*, char *);
-extern void execute_337(char*, char *);
-extern void execute_338(char*, char *);
+extern void execute_140(char*, char *);
+extern void execute_141(char*, char *);
 extern void execute_339(char*, char *);
+extern void execute_340(char*, char *);
+extern void execute_341(char*, char *);
+extern void execute_342(char*, char *);
+extern void execute_343(char*, char *);
 extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
-funcp funcTab[61] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_135, (funcp)execute_332, (funcp)execute_333, (funcp)execute_334, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_316, (funcp)execute_317, (funcp)execute_318, (funcp)execute_320, (funcp)execute_321, (funcp)execute_322, (funcp)execute_323, (funcp)execute_324, (funcp)execute_325, (funcp)execute_326, (funcp)execute_327, (funcp)execute_328, (funcp)execute_329, (funcp)execute_330, (funcp)execute_331, (funcp)execute_140, (funcp)execute_141, (funcp)execute_142, (funcp)execute_143, (funcp)execute_144, (funcp)execute_145, (funcp)execute_146, (funcp)execute_7, (funcp)execute_9, (funcp)execute_17, (funcp)execute_166, (funcp)execute_168, (funcp)execute_169, (funcp)execute_147, (funcp)execute_148, (funcp)execute_34, (funcp)execute_278, (funcp)execute_207, (funcp)execute_188, (funcp)execute_228, (funcp)execute_229, (funcp)execute_230, (funcp)execute_231, (funcp)execute_232, (funcp)execute_233, (funcp)execute_275, (funcp)execute_276, (funcp)execute_102, (funcp)execute_104, (funcp)execute_120, (funcp)execute_137, (funcp)execute_138, (funcp)execute_139, (funcp)execute_335, (funcp)execute_336, (funcp)execute_337, (funcp)execute_338, (funcp)execute_339, (funcp)vlog_transfunc_eventcallback};
-const int NumRelocateId= 61;
+funcp funcTab[63] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_137, (funcp)execute_336, (funcp)execute_337, (funcp)execute_338, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_318, (funcp)execute_319, (funcp)execute_320, (funcp)execute_322, (funcp)execute_323, (funcp)execute_324, (funcp)execute_325, (funcp)execute_326, (funcp)execute_327, (funcp)execute_328, (funcp)execute_329, (funcp)execute_330, (funcp)execute_331, (funcp)execute_332, (funcp)execute_333, (funcp)execute_334, (funcp)execute_335, (funcp)execute_142, (funcp)execute_143, (funcp)execute_144, (funcp)execute_145, (funcp)execute_146, (funcp)execute_147, (funcp)execute_148, (funcp)execute_7, (funcp)execute_9, (funcp)execute_17, (funcp)execute_168, (funcp)execute_170, (funcp)execute_171, (funcp)execute_149, (funcp)execute_150, (funcp)execute_34, (funcp)execute_280, (funcp)execute_209, (funcp)execute_190, (funcp)execute_230, (funcp)execute_231, (funcp)execute_232, (funcp)execute_233, (funcp)execute_234, (funcp)execute_235, (funcp)execute_277, (funcp)execute_278, (funcp)execute_102, (funcp)execute_104, (funcp)execute_120, (funcp)execute_139, (funcp)execute_140, (funcp)execute_141, (funcp)execute_339, (funcp)execute_340, (funcp)execute_341, (funcp)execute_342, (funcp)execute_343, (funcp)vlog_transfunc_eventcallback};
+const int NumRelocateId= 63;
 
 void relocate(char *dp)
 {
-	iki_relocate(dp, "xsim.dir/CPU9bits_tb_behav/xsim.reloc",  (void **)funcTab, 61);
+	iki_relocate(dp, "xsim.dir/CPU9bits_tb_behav/xsim.reloc",  (void **)funcTab, 63);
 
 	/*Populate the transaction function pointer field in the whole net structure */
 }
diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
index fb02517..20a4efa 100644
--- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
+++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
@@ -1,6 +1,6 @@
 webtalk_init -webtalk_dir C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
 webtalk_register_client -client project
-webtalk_add_data -client project -key date_generated -value "Thu Mar 14 14:36:57 2019" -context "software_version_and_target_device"
+webtalk_add_data -client project -key date_generated -value "Sat Mar 16 13:42:13 2019" -context "software_version_and_target_device"
 webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
 webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
 webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
@@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
 webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
 webtalk_add_data -client project -key random_id -value "17336daf-0d92-4f07-b4a4-ff1c52043edb" -context "software_version_and_target_device"
 webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
-webtalk_add_data -client project -key project_iteration -value "45" -context "software_version_and_target_device"
+webtalk_add_data -client project -key project_iteration -value "53" -context "software_version_and_target_device"
 webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
 webtalk_add_data -client project -key os_release -value "major release  (build 9200)" -context "user_environment"
 webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz" -context "user_environment"
@@ -22,11 +22,21 @@ webtalk_add_data -client project -key cpu_speed -value "2594 MHz" -context "user
 webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
 webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment"
 webtalk_register_client -client xsim
-webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
-webtalk_add_data -client xsim -key runtime -value "70 ns" -context "xsim\\usage"
-webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
-webtalk_add_data -client xsim -key Simulation_Time -value "0.00_sec" -context "xsim\\usage"
-webtalk_add_data -client xsim -key Simulation_Memory -value "5712_KB" -context "xsim\\usage"
-webtalk_transmit -clientid 920060351 -regid "" -xml C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
+webtalk_add_data -client xsim -key File_Counter -value "7" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key Simulation_Image_Code -value "92 KB" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Simulation_Image_Data -value "15 KB" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Total_Processes -value "230" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Total_Instances -value "118" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
+webtalk_add_data -client xsim -key Compiler_Time -value "0.92_sec" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Compiler_Memory -value "42696_KB" -context "xsim\\usage"
+webtalk_transmit -clientid 3357111948 -regid "" -xml C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
 webtalk_terminate
diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
index 3b54dd3205acfa7f2bf52ba698022b3c67c0e179..ad10912b9dc7945f1746c21703141d29c63e3a9b 100644
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diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v
index 2674138..b866e9f 100644
--- a/lab2CA.srcs/sources_1/new/CPU9bits.v
+++ b/lab2CA.srcs/sources_1/new/CPU9bits.v
@@ -6,10 +6,10 @@ module CPU9bits(
     output wire done
     );
     
-    wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
+    wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData;
     wire [2:0] FU;
     wire [3:0] aluOp;
-    wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1;
+    wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link;
         
     RegFile RF(
         .clk(clk),
@@ -46,7 +46,8 @@ module CPU9bits(
         .addi(addiS),
         .mem(loadS),
         .RegEn(RegEn),
-        .halt(done)
+        .halt(done),
+        .link(link)
      );
      
      
@@ -60,28 +61,28 @@ module CPU9bits(
         .Cout(cout0));
         
     mux_2_1 mux1(
-        .A(op1),
+        .A(op0),
         .B(FUJB),
         .out(FUAddr),
         .switch(FU[1]));
         
     mux_2_1 mux2(
-        .A({4'b0000,instr[4:0]}), //Jump
-        .B({6'b000000,instr[2:0]}),//Branch
+        .A({4'b0000,instr[4:0]}), //Jump -- Change with signer module!
+        .B({6'b000000,instr[2:0]}),//Branch -- Change with signer module!
         .out(JBRes),
         .switch(FU[2]));
         
     bit1_mux_2_1 BranMux( // BEQ MUX
         .A(FU[0]),
-        .B(op1[0]),
+        .B(op0[0]),
         .out(fetchBranch),
         .switch(FU[2])); // FU[2] only goes high when BEQ
         
     ///--------------------------Addi Stuff
         
     add_9bit Addier(
-        .A({6'b000000,instr[2:0]}),
-        .B(op1),
+        .A({6'b000000,instr[2:0]}), // Change with signer module!
+        .B(op0),
         .Cin(1'b0),
         .Sum(AddiOut),
         .Cout(cout1));
@@ -92,11 +93,22 @@ module CPU9bits(
         .out(loadMux),
         .switch(addiS));
         
+        
+    ///--------------------------Mem stuff
+        
     mux_2_1 mux4(
-        .A(loadMux),
-        .B(9'b000000001),
+        .A(linkData),
+        .B(9'b000000001), // This is DATA MEM
         .out(RFIn),
         .switch(loadS));
+        
+    ///--------------------------Link Stuff
+    
+    mux_2_1 mux5(
+        .A(loadMux),
+        .B(PCout),
+        .out(linkData),
+        .switch(link));
      
          
 endmodule
@@ -133,6 +145,8 @@ module CPU9bits_tb();
         #10
         instruction = 9'b111100000;
         #10
+        instruction = 9'b001101000;
+        #10
         instruction = 9'b000000000;
         #10    
         $finish;
diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v
index 6f716ed..3722fe7 100644
--- a/lab2CA.srcs/sources_1/new/ControlUnit.v
+++ b/lab2CA.srcs/sources_1/new/ControlUnit.v
@@ -8,7 +8,8 @@ module ControlUnit(
     output reg addi,
     output reg mem,
     output reg RegEn,
-    output reg halt);
+    output reg halt,
+    output reg link);
     
         always @(instIn, functBit)begin
             case(instIn)
@@ -20,6 +21,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
+                    link <= 1'b0;
                 end
                 else begin
                     aluOut <= 4'b0000; //Add
@@ -28,6 +30,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
+                    link <= 1'b0;
                 end
             4'b1101: begin 
                      aluOut <= 4'b0011; //nor
@@ -36,6 +39,7 @@ module ControlUnit(
                      halt <= 1'b0;
                      addi <= 1'b0;
                      mem <= 1'b0;
+                     link <= 1'b0;
                      end
             4'b1110: 
                 if(functBit == 1) begin
@@ -45,6 +49,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
+                    link <= 1'b0;
                 end
                 else begin
                     aluOut <= 4'b0010; //or
@@ -53,6 +58,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
+                    link <= 1'b0;
                 end           
             4'b1111:
                 if(functBit == 1) begin
@@ -62,6 +68,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
+                    link <= 1'b0;
                 end
                 else begin
                     aluOut <= 4'b0101; //shift left
@@ -70,6 +77,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
+                    link <= 1'b0;
                 end
             4'b0111: begin 
                      aluOut <= 4'b1001; //Less than
@@ -78,6 +86,7 @@ module ControlUnit(
                      halt <= 1'b0;
                      addi <= 1'b0;
                      mem <= 1'b0;
+                     link <= 1'b0;
                 end
             4'b0110: begin
                      aluOut <= 4'b0000;
@@ -86,14 +95,25 @@ module ControlUnit(
                      FU <= 3'b001; // Disable Branching
                      halt <= 1'b0;
                      mem <= 1'b0;
+                     link <= 1'b0;
                 end
-            4'b1001: begin //We got it wrong, first bit must always be zero whenever branching happens. Fixed
+            4'b1001: begin 
                      aluOut <= 4'b0000;
                      FU <= 3'b010; // jump
                      RegEn <= 1'b1;
                      halt <= 1'b0;
                      addi <= 1'b0;
                      mem <= 1'b0;
+                     link <= 1'b0;
+                end
+            4'b0011: begin // link
+                     halt <= 1'b0;
+                     RegEn <= 1'b0; 
+                     FU <= 3'b001; 
+                     addi <= 1'b0;
+                     aluOut <= 4'b0000;
+                     mem <= 1'b0;
+                     link <= 1'b1;
                 end
             4'b1010: begin
                      aluOut <= 4'b0000;
@@ -102,6 +122,7 @@ module ControlUnit(
                      halt <= 1'b0;
                      addi <= 1'b0;
                      mem <= 1'b0;
+                     link <= 1'b0;
                 end
             4'b1000: begin 
                      aluOut <= 4'b0000;
@@ -110,6 +131,7 @@ module ControlUnit(
                      halt <= 1'b0;
                      addi <= 1'b0;
                      mem <= 1'b0;
+                     link <= 1'b0;
                 end
             4'b0001: begin
                      aluOut <= 4'b0000;
@@ -118,6 +140,7 @@ module ControlUnit(
                      FU <= 3'b001; // Disable Branching
                      addi <= 1'b0;
                      halt <= 1'b0;
+                     link <= 1'b0;
                 end
             4'b0010: begin
                      aluOut <= 4'b0000;
@@ -126,6 +149,7 @@ module ControlUnit(
                      FU <= 3'b001; // Disable Branching
                      halt <= 1'b0;
                      addi <= 1'b0;
+                     link <= 1'b0;
                 end
             4'b0000: begin // regs should initialize at 0, so we shouldn't need to declare it everywhere
                      halt <= 1'b1; // halt
@@ -134,6 +158,7 @@ module ControlUnit(
                      addi <= 1'b0;
                      aluOut <= 4'b0000;
                      mem <= 1'b0;
+                     link <= 1'b0;
                 end
             default: begin
                      halt <= 1'b1;
@@ -142,6 +167,7 @@ module ControlUnit(
                      addi <= 1'b0;
                      aluOut <= 4'b0000;
                      mem <= 1'b0;
+                     link <= 1'b0;
                      end
         endcase
     end
diff --git a/lab2CA.xpr b/lab2CA.xpr
index 3dadb41..7550d07 100644
--- a/lab2CA.xpr
+++ b/lab2CA.xpr
@@ -31,7 +31,7 @@
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSAVendor" Val="xilinx"/>
     <Option Name="DSANumComputeUnits" Val="60"/>
-    <Option Name="WTXSimLaunchSim" Val="125"/>
+    <Option Name="WTXSimLaunchSim" Val="133"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -122,7 +122,7 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
       <Filter Type="Srcs"/>
-      <File Path="$PPRDIR/regFile_tb_behav.wcfg">
+      <File Path="$PPRDIR/CPU9bits_tb_behav.wcfg">
         <FileInfo>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
@@ -135,6 +135,7 @@
         <Option Name="TransportIntDelay" Val="0"/>
         <Option Name="SrcSet" Val="sources_1"/>
         <Option Name="XSimWcfgFile" Val="$PPRDIR/regFile_tb_behav.wcfg"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/CPU9bits_tb_behav.wcfg"/>
       </Config>
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">