diff --git a/CPU9bits_tb_behav.wcfg b/CPU9bits_tb_behav.wcfg index 40abd4d..3a75952 100644 --- a/CPU9bits_tb_behav.wcfg +++ b/CPU9bits_tb_behav.wcfg @@ -11,241 +11,514 @@ - - - + + + - + - - - clk - clk + + + CPU + label + + + reset + reset + + + clk + clk + + + result[8:0] + result[8:0] + + + done + done + + + instr[8:0] + instr[8:0] + + + op1[8:0] + op1[8:0] + + + op0[8:0] + op0[8:0] + + + FUAddr[8:0] + FUAddr[8:0] + + + FUJB[8:0] + FUJB[8:0] + + + PCout[8:0] + PCout[8:0] + + + JBRes[8:0] + JBRes[8:0] + + + FUJ[8:0] + FUJ[8:0] + + + FUB[8:0] + FUB[8:0] + + + AddiOut[8:0] + AddiOut[8:0] + + + AluOut[8:0] + AluOut[8:0] + + + RFIn[8:0] + RFIn[8:0] + + + loadMux[8:0] + loadMux[8:0] + + + dataMemOut[8:0] + dataMemOut[8:0] + + + linkData[8:0] + linkData[8:0] + + + SE1N[8:0] + SE1N[8:0] + + + SE2N[8:0] + SE2N[8:0] + + + SE3N[8:0] + SE3N[8:0] + + + bankData[8:0] + bankData[8:0] + + + bankOP[8:0] + bankOP[8:0] + + + jumpNeg[8:0] + jumpNeg[8:0] + + + aluOp[3:0] + aluOp[3:0] + + + FU[2:0] + FU[2:0] + + + bankS[1:0] + bankS[1:0] + + + addiS + addiS + + + RegEn + RegEn + + + loadS + loadS + + + fetchBranch + fetchBranch + + + halt + halt + + + cout0 + cout0 + + + cout1 + cout1 + + + link + link + + + js + js + + + dataMemEn + dataMemEn + - - reset - reset + + Control Unit + label + + instIn[3:0] + instIn[3:0] + + + functBit + functBit + + + aluOut[3:0] + aluOut[3:0] + + + FU[2:0] + FU[2:0] + + + bank[1:0] + bank[1:0] + + + addi + addi + + + mem + mem + + + dataMemEn + dataMemEn + + + RegEn + RegEn + + + halt + halt + + + link + link + + + js + js + - - done - done + + Fetch Unit + label + + clk + clk + + + reset + reset + + + op_idx + op_idx + + + AddrIn[8:0] + AddrIn[8:0] + + + AddrOut[8:0] + AddrOut[8:0] + + + progC_out[8:0] + progC_out[8:0] + + + result_m[8:0] + result_m[8:0] + + + cout + cout + - - instr[8:0] - instr[8:0] - BINARYRADIX + + ALU + label + + opcode[3:0] + opcode[3:0] + + + operand0[8:0] + operand0[8:0] + + + operand1[8:0] + operand1[8:0] + + + result[8:0] + result[8:0] + + + result_A[8:0] + result_A[8:0] + + + result_B[8:0] + result_B[8:0] + + + result_C[8:0] + result_C[8:0] + + + result_D[8:0] + result_D[8:0] + + + result_E[8:0] + result_E[8:0] + + + result_F[8:0] + result_F[8:0] + + + result_G[8:0] + result_G[8:0] + + + result_H[8:0] + result_H[8:0] + + + result_I[8:0] + result_I[8:0] + + + result_J[8:0] + result_J[8:0] + + + result_K[8:0] + result_K[8:0] + + + result_L[8:0] + result_L[8:0] + + + result_M[8:0] + result_M[8:0] + + + result_N[8:0] + result_N[8:0] + + + result_O[8:0] + result_O[8:0] + + + result_P[8:0] + result_P[8:0] + + + cout + cout + - - AddrOut[8:0] - AddrOut[8:0] - UNSIGNEDDECRADIX - - + Registers label - + + clk + clk + + + reset + reset + + + enable + enable + + + write_index[1:0] + write_index[1:0] + + + op0_idx[1:0] + op0_idx[1:0] + + + op1_idx[1:0] + op1_idx[1:0] + + + write_data[8:0] + write_data[8:0] + + + op0[8:0] + op0[8:0] + + + op1[8:0] + op1[8:0] + + + decOut[3:0] + decOut[3:0] + - label r0_out[8:0] r0_out[8:0] - RegisterA - UNSIGNEDDECRADIX - label r1_out[8:0] r1_out[8:0] - RegisterB - UNSIGNEDDECRADIX - label r2_out[8:0] r2_out[8:0] - RegisterC - UNSIGNEDDECRADIX - label r3_out[8:0] r3_out[8:0] - RegisterD - UNSIGNEDDECRADIX - + Banks label - + + clk + clk + + + reset + reset + + + enable + enable + + + write_index[1:0] + write_index[1:0] + + + op0_idx[1:0] + op0_idx[1:0] + + + op1_idx[1:0] + op1_idx[1:0] + + + write_data[8:0] + write_data[8:0] + + + op0[8:0] + op0[8:0] + + + op1[8:0] + op1[8:0] + + + decOut[3:0] + decOut[3:0] + - label r0_out[8:0] r0_out[8:0] - Bank0 - UNSIGNEDDECRADIX - label r1_out[8:0] r1_out[8:0] - Bank1 - UNSIGNEDDECRADIX - label r2_out[8:0] r2_out[8:0] - Bank2 - UNSIGNEDDECRADIX - label r3_out[8:0] r3_out[8:0] - Bank3 - UNSIGNEDDECRADIX Divider label - + + Instruction Memory label - memory[23:0][8:0] - memory[23:0][8:0] + + address[8:0] + address[8:0] + + + memory[100:0][8:0] + memory[100:0][8:0] + + + readData[8:0] + readData[8:0] + + + Data Memory - UNSIGNEDDECRADIX - - - [23][8:0] - [23][8:0] - UNSIGNEDDECRADIX + label + + clk + clk - - [22][8:0] - [22][8:0] - UNSIGNEDDECRADIX + + writeEnable + writeEnable - - [21][8:0] - [21][8:0] - UNSIGNEDDECRADIX + + address[8:0] + address[8:0] - - [20][8:0] - [20][8:0] - UNSIGNEDDECRADIX + + writeData[8:0] + writeData[8:0] - - [19][8:0] - [19][8:0] - UNSIGNEDDECRADIX + + readData[8:0] + readData[8:0] - - [18][8:0] - [18][8:0] - UNSIGNEDDECRADIX + + memory[100:0][8:0] + memory[100:0][8:0] - - [17][8:0] - [17][8:0] - UNSIGNEDDECRADIX - - - [16][8:0] - [16][8:0] - UNSIGNEDDECRADIX - - - [15][8:0] - [15][8:0] - UNSIGNEDDECRADIX - - - [14][8:0] - [14][8:0] - UNSIGNEDDECRADIX - - - [13][8:0] - [13][8:0] - UNSIGNEDDECRADIX - - - [12][8:0] - [12][8:0] - UNSIGNEDDECRADIX - - - [11][8:0] - [11][8:0] - UNSIGNEDDECRADIX - - - [10][8:0] - [10][8:0] - UNSIGNEDDECRADIX - - - [9][8:0] - [9][8:0] - UNSIGNEDDECRADIX - - - [8][8:0] - [8][8:0] - UNSIGNEDDECRADIX - - - [7][8:0] - [7][8:0] - UNSIGNEDDECRADIX - - - [6][8:0] - [6][8:0] - UNSIGNEDDECRADIX - - - [5][8:0] - [5][8:0] - UNSIGNEDDECRADIX - - - [4][8:0] - [4][8:0] - UNSIGNEDDECRADIX - - - [3][8:0] - [3][8:0] - UNSIGNEDDECRADIX - - - [2][8:0] - [2][8:0] - UNSIGNEDDECRADIX - - - [1][8:0] - [1][8:0] - UNSIGNEDDECRADIX - - - [0][8:0] - [0][8:0] - UNSIGNEDDECRADIX - - - - readData[8:0] - readData[8:0] - - - AddrIn[8:0] - AddrIn[8:0] diff --git a/lab2CA.runs/.jobs/vrs_config_59.xml b/lab2CA.runs/.jobs/vrs_config_59.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_59.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_60.xml b/lab2CA.runs/.jobs/vrs_config_60.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_60.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_61.xml b/lab2CA.runs/.jobs/vrs_config_61.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_61.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_62.xml b/lab2CA.runs/.jobs/vrs_config_62.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_62.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_63.xml b/lab2CA.runs/.jobs/vrs_config_63.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_63.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_64.xml b/lab2CA.runs/.jobs/vrs_config_64.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_64.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_65.xml b/lab2CA.runs/.jobs/vrs_config_65.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_65.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_66.xml b/lab2CA.runs/.jobs/vrs_config_66.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_66.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_67.xml b/lab2CA.runs/.jobs/vrs_config_67.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_67.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_68.xml b/lab2CA.runs/.jobs/vrs_config_68.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_68.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_69.xml b/lab2CA.runs/.jobs/vrs_config_69.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_69.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_70.xml b/lab2CA.runs/.jobs/vrs_config_70.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_70.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb b/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb deleted file mode 100644 index 3390588..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_opted.pb b/lab2CA.runs/impl_1/CPU9bits_drc_opted.pb deleted file mode 100644 index 0158a2a..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_drc_opted.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_routed.pb b/lab2CA.runs/impl_1/CPU9bits_drc_routed.pb deleted file mode 100644 index 0158a2a..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_drc_routed.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.pb b/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.pb deleted file mode 100644 index 4526e93..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.pb +++ /dev/null @@ -1,2 +0,0 @@ - -2012.4’)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/lab2CA.runs/impl_1/htr.txt b/lab2CA.runs/impl_1/htr.txt deleted file mode 100644 index a32836e..0000000 --- a/lab2CA.runs/impl_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log CPU9bits.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace diff --git a/lab2CA.runs/synth_1/CPU9bits_tb.dcp b/lab2CA.runs/synth_1/CPU9bits_tb.dcp new file mode 100644 index 0000000..94e89b7 Binary files /dev/null and b/lab2CA.runs/synth_1/CPU9bits_tb.dcp differ diff --git a/lab2CA.runs/synth_1/CPU9bits.tcl b/lab2CA.runs/synth_1/CPU9bits_tb.tcl similarity index 100% rename from lab2CA.runs/synth_1/CPU9bits.tcl rename to lab2CA.runs/synth_1/CPU9bits_tb.tcl diff --git a/lab2CA.runs/synth_1/CPU9bits.vds b/lab2CA.runs/synth_1/CPU9bits_tb.vds similarity index 100% rename from lab2CA.runs/synth_1/CPU9bits.vds rename to lab2CA.runs/synth_1/CPU9bits_tb.vds diff --git a/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb b/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb new file mode 100644 index 0000000..68f663d Binary files /dev/null and b/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb differ diff --git a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt b/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt similarity index 100% rename from lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt rename to lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt diff --git a/lab2CA.runs/synth_1/htr.txt b/lab2CA.runs/synth_1/htr.txt index 641d4cb..b59ff1f 100644 --- a/lab2CA.runs/synth_1/htr.txt +++ b/lab2CA.runs/synth_1/htr.txt @@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status. REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. REM -vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl +vivado -log CPU9bits_tb.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_26660.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_10700.backup.jou similarity index 84% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_26660.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_10700.backup.jou index 21e9e99..d1b0d25 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_26660.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_10700.backup.jou @@ -2,10 +2,10 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Fri Mar 29 15:21:59 2019 -# Process ID: 26660 +# Start of session at: Sat Apr 6 13:17:03 2019 +# Process ID: 10700 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11564.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_11564.backup.jou new file mode 100644 index 0000000..71a23ce --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_11564.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Apr 6 13:16:30 2019 +# Process ID: 11564 +# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/REPOSITORIES/Educational/Western -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_14652.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_16352.backup.jou similarity index 92% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_14652.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_16352.backup.jou index 5f01ab3..ebcc5c7 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_14652.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_16352.backup.jou @@ -2,8 +2,8 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Fri Mar 29 15:13:54 2019 -# Process ID: 14652 +# Start of session at: Sat Apr 6 14:28:59 2019 +# Process ID: 16352 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim # Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v index 9a0c11e..a41e2ae 100644 --- a/lab2CA.srcs/sources_1/new/ControlUnit.v +++ b/lab2CA.srcs/sources_1/new/ControlUnit.v @@ -13,71 +13,72 @@ module ControlUnit( case(instIn) 4'b0000: // Halt/NOP begin - halt <= 1'b1; - RegEn <= 1'b1; - FU <= 3'b001; // Disable Branching - addi <= 1'b0; - dataMemEn <= 1'b0; // Disabled - aluOut <= 4'b0000; - mem <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + halt <= 1'b1; + RegEn <= 1'b1; + FU <= 3'b001; // Disable Branching + addi <= 1'b0; + dataMemEn <= 1'b0; // Disabled + aluOut <= 4'b0000; + mem <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b0001: // Load Byte begin - aluOut <= 4'b0000; - mem <= 1'b1; - dataMemEn <= 1'b0; // Disabled - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - addi <= 1'b0; - halt <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b1; + dataMemEn <= 1'b0; // Disabled + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + addi <= 1'b0; + halt <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b0010: // Store Byte begin - aluOut <= 4'b0000; - mem <= 1'b0; - dataMemEn <= 1'b1; // Enabled - RegEn <= 1'b1; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b0; + dataMemEn <= 1'b1; // Enabled + RegEn <= 1'b1; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b0011: // Link begin - halt <= 1'b0; - RegEn <= 1'b0; - FU <= 3'b001; - addi <= 1'b0; - aluOut <= 4'b0000; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b1; - bank <= 2'b10; - js <= 1'b0; + halt <= 1'b0; + RegEn <= 1'b0; + FU <= 3'b001; + addi <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b1; + bank <= 2'b10; + js <= 1'b0; end 4'b0100: // Zero begin - aluOut <= 4'b1011; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b1011; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b0101: // Add/Subtract - if(functBit == 1) begin // Subtract + if(functBit == 1) // Subtract + begin aluOut <= 4'b0001; RegEn <= 1'b0; FU <= 3'b001; @@ -88,8 +89,9 @@ module ControlUnit( link <= 1'b0; bank <= 2'b10; js <= 1'b0; - end - else begin // Add + end + else // Add + begin aluOut <= 4'b0000; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching @@ -100,114 +102,114 @@ module ControlUnit( link <= 1'b0; bank <= 2'b10; js <= 1'b0; - end + end 4'b0110: // Add Immediate begin - aluOut <= 4'b1010; - addi <= 1'b1; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b1010; + addi <= 1'b1; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b0111: // Set if Less Than begin - aluOut <= 4'b1001; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b1001; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b1000: // Jump to Register begin - aluOut <= 4'b0000; - FU <= 3'b000; - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b0000; + FU <= 3'b000; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b1001: // Jump Forward begin - aluOut <= 4'b0000; - FU <= 3'b010; - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b0000; + FU <= 3'b010; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b1010: // Bank Load/Bank Store begin - halt <= 1'b0; - RegEn <= !functBit; - FU <= 3'b001; // Disable Branching - addi <= 1'b0; - aluOut <= 4'b0000; - dataMemEn <= 1'b0; // Disabled - mem <= 1'b0; - link <= 1'b0; - bank <= {functBit,functBit}; - js <= 1'b0; + halt <= 1'b0; + RegEn <= !functBit; + FU <= 3'b001; // Disable Branching + addi <= 1'b0; + aluOut <= 4'b0000; + dataMemEn <= 1'b0; // Disabled + mem <= 1'b0; + link <= 1'b0; + bank <= {functBit,functBit}; + js <= 1'b0; end 4'b1011: // Jump Backward begin - aluOut <= 4'b0000; - FU <= 3'b010; - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b1; + aluOut <= 4'b0000; + FU <= 3'b010; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b1; end 4'b1100: // Branch if Zero begin - aluOut <= 4'b1010; - FU <= 3'b110; - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b1010; + FU <= 3'b110; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b1101: // NOR begin - aluOut <= 4'b0011; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b0011; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b1110: // OR/AND if(functBit == 1) // AND - begin + begin aluOut <= 4'b0100; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching @@ -218,9 +220,9 @@ module ControlUnit( link <= 1'b0; bank <= 2'b10; js <= 1'b0; - end + end else // OR - begin + begin aluOut <= 4'b0010; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching @@ -231,10 +233,10 @@ module ControlUnit( link <= 1'b0; bank <= 2'b10; js <= 1'b0; - end + end 4'b1111: // Shift Right Logical/Shift Left Logical if(functBit == 1) // Shift Right Logical - begin + begin aluOut <= 4'b0110; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching @@ -245,9 +247,9 @@ module ControlUnit( link <= 1'b0; bank <= 2'b10; js <= 1'b0; - end + end else // Shift Left Logical - begin + begin aluOut <= 4'b0101; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching @@ -258,19 +260,19 @@ module ControlUnit( link <= 1'b0; bank <= 2'b10; js <= 1'b0; - end + end default: begin - halt <= 1'b1; - RegEn <= 1'b1; - FU <= 3'b001; - dataMemEn <= 1'b0; // Disabled - addi <= 1'b0; - aluOut <= 4'b0000; - mem <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + halt <= 1'b1; + RegEn <= 1'b1; + FU <= 3'b001; + dataMemEn <= 1'b0; // Disabled + addi <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end endcase end diff --git a/lab2CA.srcs/sources_1/new/FetchUnit.v b/lab2CA.srcs/sources_1/new/FetchUnit.v index 3e77260..17440c3 100644 --- a/lab2CA.srcs/sources_1/new/FetchUnit.v +++ b/lab2CA.srcs/sources_1/new/FetchUnit.v @@ -1,9 +1,11 @@ `timescale 1ns / 1ps -module FetchUnit(input wire clk, reset, - input wire op_idx, - input wire [8:0] AddrIn, - output wire [8:0] AddrOut); +module FetchUnit( + input wire clk, reset, + input wire op_idx, + input wire [8:0] AddrIn, + output wire [8:0] AddrOut + ); //Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a) wire [8:0] progC_out, result_m; @@ -29,7 +31,6 @@ module FetchUnit(input wire clk, reset, .out(result_m), .switch(op_idx)); - endmodule //testbench diff --git a/lab2CA.srcs/sources_1/new/dataMemory.v b/lab2CA.srcs/sources_1/new/dataMemory.v index d2ff236..7ce5443 100644 --- a/lab2CA.srcs/sources_1/new/dataMemory.v +++ b/lab2CA.srcs/sources_1/new/dataMemory.v @@ -6,7 +6,7 @@ module dataMemory( output reg [8:0] readData ); - reg [8:0] memory [512:0]; // Maximum of 512 memory locations + reg [8:0] memory [100:0]; // Maximum of 512 memory locations // Vivado will give warnings of unconnected ports on the "address" bus if they are unused initial begin @@ -97,107 +97,107 @@ module dataMemory( // Program 1 Test Data -// memory[0] <= 9'd100; -// memory[1] <= 9'd58; -// memory[2] <= 9'd6; -// memory[3] <= 9'd12; -// memory[4] <= 9'b110110000; // -80 -// memory[5] <= 9'd17; -// memory[6] <= 9'b111011011; // -37 -// memory[7] <= 9'd25; -// memory[8] <= -9'd83; // -83 -// memory[9] <= -9'd98; // -98 -// memory[10] <= -9'd98; // -98 -// memory[11] <= -9'd74; // -74 -// memory[12] <= 9'd70; -// memory[13] <= -9'd38; // -38 -// memory[14] <= 9'd52; -// memory[15] <= -9'd96; // -96 -// memory[16] <= -9'd32; // -32 -// memory[17] <= -9'd93; // -93 -// memory[18] <= -9'd40; // -40 -// memory[19] <= 9'd59; -// memory[20] <= 9'd10; -// memory[21] <= 9'd81; -// memory[22] <= -9'd23; // -28 -// memory[23] <=- 9'd99; // -99 -// memory[24] <= -9'd41; // -41 -// memory[25] <= 9'd33; -// memory[26] <= 9'd98; -// memory[27] <= 9'd73; -// memory[28] <= -9'd1; // -1 -// memory[29] <= 9'd28; -// memory[30] <= 9'd5; -// memory[31] <= -9'd74; // -74 -// memory[32] <= -9'd41; // -41 -// memory[33] <= 9'd41; -// memory[34] <= 9'd39; -// memory[35] <= 9'd62; -// memory[36] <= 9'd19; -// memory[37] <= -9'd40; // -40 -// memory[38] <= -9'd8; // -8 -// memory[39] <= 9'd92; -// memory[40] <= 9'd37; -// memory[41] <= 9'd50; -// memory[42] <= -9'd72; // -72 -// memory[43] <= -9'd5; // -5 -// memory[44] <= 9'd19; -// memory[45] <= 9'd58; -// memory[46] <= -9'd13; // -13 -// memory[47] <= 9'd0; -// memory[48] <= -9'd97; // -97 -// memory[49] <= 9'd54; -// memory[50] <= -9'd17; // -17 -// memory[51] <= -9'd83; // -83 -// memory[52] <= 9'd53; -// memory[53] <= 9'd82; -// memory[54] <= -9'd94; // -94 -// memory[55] <= -9'd77; // -77 -// memory[56] <= -9'd74; // -74 -// memory[57] <= -9'd52; // -52 -// memory[58] <= 9'd85; -// memory[59] <= -9'd65; // -65 -// memory[60] <= -9'd10; // -10 -// memory[61] <= -9'd45; // -45 -// memory[62] <= -9'd92; // -92 -// memory[63] <= -9'd30; // -30 -// memory[64] <= 9'd18; -// memory[65] <= -9'd95; // -95 -// memory[66] <= -9'd27; // -27 -// memory[67] <= -9'd74; // -74 -// memory[68] <= 9'd62; -// memory[69] <= 9'd64; -// memory[70] <= -9'd9; // -9 -// memory[71] <= 9'd66; -// memory[72] <= -9'd71; // -71 -// memory[73] <= -9'd31; // -31 -// memory[74] <= 9'd34; -// memory[75] <= 9'd12; -// memory[76] <= 9'd3; -// memory[77] <= 9'd82; -// memory[78] <= 9'd13; -// memory[79] <= -9'd78; // -78 -// memory[80] <= -9'd8; // -8 -// memory[81] <= 9'd88; -// memory[82] <= 9'd42; -// memory[83] <= 9'd42; -// memory[84] <= 9'd21; -// memory[85] <= -9'd44; // -44 -// memory[86] <= 9'd30; -// memory[87] <= -9'd93; // -93 -// memory[88] <= 9'd2; -// memory[89] <= -9'd34; // -34 -// memory[90] <= 9'd92; -// memory[91] <= -9'd45; // -45 -// memory[92] <= 9'd26; -// memory[93] <= -9'd79; // -79 -// memory[94] <= 9'd43; -// memory[95] <= -9'd25; // -25 -// memory[96] <= -9'd24; // -24 -// memory[97] <= -9'd25; // -25 -// memory[98] <= -9'd19; // -19 -// memory[99] <= -9'd49; // -49 -// memory[100] <= -9'd8; // -8 + memory[0] <= 9'd100; + memory[1] <= 9'd58; + memory[2] <= 9'd6; + memory[3] <= 9'd12; + memory[4] <= 9'b110110000; // -80 + memory[5] <= 9'd17; + memory[6] <= 9'b111011011; // -37 + memory[7] <= 9'd25; + memory[8] <= -9'd83; // -83 + memory[9] <= -9'd98; // -98 + memory[10] <= -9'd98; // -98 + memory[11] <= -9'd74; // -74 + memory[12] <= 9'd70; + memory[13] <= -9'd38; // -38 + memory[14] <= 9'd52; + memory[15] <= -9'd96; // -96 + memory[16] <= -9'd32; // -32 + memory[17] <= -9'd93; // -93 + memory[18] <= -9'd40; // -40 + memory[19] <= 9'd59; + memory[20] <= 9'd10; + memory[21] <= 9'd81; + memory[22] <= -9'd23; // -28 + memory[23] <=- 9'd99; // -99 + memory[24] <= -9'd41; // -41 + memory[25] <= 9'd33; + memory[26] <= 9'd98; + memory[27] <= 9'd73; + memory[28] <= -9'd1; // -1 + memory[29] <= 9'd28; + memory[30] <= 9'd5; + memory[31] <= -9'd74; // -74 + memory[32] <= -9'd41; // -41 + memory[33] <= 9'd41; + memory[34] <= 9'd39; + memory[35] <= 9'd62; + memory[36] <= 9'd19; + memory[37] <= -9'd40; // -40 + memory[38] <= -9'd8; // -8 + memory[39] <= 9'd92; + memory[40] <= 9'd37; + memory[41] <= 9'd50; + memory[42] <= -9'd72; // -72 + memory[43] <= -9'd5; // -5 + memory[44] <= 9'd19; + memory[45] <= 9'd58; + memory[46] <= -9'd13; // -13 + memory[47] <= 9'd0; + memory[48] <= -9'd97; // -97 + memory[49] <= 9'd54; + memory[50] <= -9'd17; // -17 + memory[51] <= -9'd83; // -83 + memory[52] <= 9'd53; + memory[53] <= 9'd82; + memory[54] <= -9'd94; // -94 + memory[55] <= -9'd77; // -77 + memory[56] <= -9'd74; // -74 + memory[57] <= -9'd52; // -52 + memory[58] <= 9'd85; + memory[59] <= -9'd65; // -65 + memory[60] <= -9'd10; // -10 + memory[61] <= -9'd45; // -45 + memory[62] <= -9'd92; // -92 + memory[63] <= -9'd30; // -30 + memory[64] <= 9'd18; + memory[65] <= -9'd95; // -95 + memory[66] <= -9'd27; // -27 + memory[67] <= -9'd74; // -74 + memory[68] <= 9'd62; + memory[69] <= 9'd64; + memory[70] <= -9'd9; // -9 + memory[71] <= 9'd66; + memory[72] <= -9'd71; // -71 + memory[73] <= -9'd31; // -31 + memory[74] <= 9'd34; + memory[75] <= 9'd12; + memory[76] <= 9'd3; + memory[77] <= 9'd82; + memory[78] <= 9'd13; + memory[79] <= -9'd78; // -78 + memory[80] <= -9'd8; // -8 + memory[81] <= 9'd88; + memory[82] <= 9'd42; + memory[83] <= 9'd42; + memory[84] <= 9'd21; + memory[85] <= -9'd44; // -44 + memory[86] <= 9'd30; + memory[87] <= -9'd93; // -93 + memory[88] <= 9'd2; + memory[89] <= -9'd34; // -34 + memory[90] <= 9'd92; + memory[91] <= -9'd45; // -45 + memory[92] <= 9'd26; + memory[93] <= -9'd79; // -79 + memory[94] <= 9'd43; + memory[95] <= -9'd25; // -25 + memory[96] <= -9'd24; // -24 + memory[97] <= -9'd25; // -25 + memory[98] <= -9'd19; // -19 + memory[99] <= -9'd49; // -49 + memory[100] <= -9'd8; // -8 diff --git a/lab2CA.srcs/sources_1/new/instructionMemory.v b/lab2CA.srcs/sources_1/new/instructionMemory.v index d4af570..2675e30 100644 --- a/lab2CA.srcs/sources_1/new/instructionMemory.v +++ b/lab2CA.srcs/sources_1/new/instructionMemory.v @@ -5,16 +5,17 @@ module instructionMemory( output reg [8:0] readData ); - reg [8:0] memory [512:0]; + reg [8:0] memory [100:0]; // Maximum of 512 memory locations + // Vivado will give warnings of unconnected ports on the "address" bus if they are unused initial begin - //Equation Solver - memory[0] <= 9'b000000000; - memory[1] <= 9'b000100000; //load - memory[2] <= 9'b000101000; //load - memory[3] <= 9'b010100010; //add - memory[4] <= 9'b111100000; //shift left - memory[5] <= 9'b111100000; //shift left +// //Equation Solver +// memory[0] <= 9'b000000000; +// memory[1] <= 9'b000100000; //load +// memory[2] <= 9'b000101000; //load +// memory[3] <= 9'b010100010; //add +// memory[4] <= 9'b111100000; //shift left +// memory[5] <= 9'b111100000; //shift left // //Testing all instructions // memory[6] <= 9'b010100011; //sub @@ -75,69 +76,69 @@ module instructionMemory( // memory[39] <= 9'b000000000; -// Bubble Sort -// memory[0] <= 9'b000000001; // nop -// // Setup -// memory[1] <= 9'b010000000; // zero $a -// memory[2] <= 9'b000100000; // lb $a, $a -// memory[3] <= 9'b010001000; // zero $b -// memory[4] <= 9'b010010000; // zero $c -// memory[5] <= 9'b010011000; // zero $d -// memory[6] <= 9'b101001000; // banks $b, $0 -// memory[7] <= 9'b101001010; // banks $b, $1 -// memory[8] <= 9'b100100011; // jf EndChk -// // Increment current index to compare next pair of values -// // Inc: -// memory[9] <= 9'b101001001; // bankl $b, $0 -// memory[10] <= 9'b011001001; // addi $b, 1 -// memory[11] <= 9'b101001000; // banks $b, $0 -// // Check if at the end of the array -// // EndChk: -// memory[12] <= 9'b101001001; // bankl $b, $0 -// memory[13] <= 9'b011101000; // slt $b, $a -// memory[14] <= 9'b110001001; // beq $b, JSC -// memory[15] <= 9'b100100001; // jf LoadNext -// // JSC: -// memory[16] <= 9'b100110100; // jf SwapChk -// // Load next values for comparison -// // LoadNext: -// memory[17] <= 9'b101001001; // bankl $b, $0 -// memory[18] <= 9'b011001001; // addi $b, 1 -// memory[19] <= 9'b000110010; // lb $c, $b -// memory[20] <= 9'b011001001; // addi $b, 1 -// memory[21] <= 9'b000111010; // lb $d, $b -// // Compare loaded values to see if they need to be swapped -// memory[22] <= 9'b101011110; // banks $d, $3 -// memory[23] <= 9'b011111100; // slt $d, $c -// memory[24] <= 9'b110011001; // beq $d, JI -// memory[25] <= 9'b100100001; // jf Swap -// // JI: -// memory[26] <= 9'b101110010; // jb Inc -// // Swap values in array -// // Swap: -// memory[27] <= 9'b101001001; // bankl $b, $0 -// memory[28] <= 9'b011001001; // addi $b, 1 -// memory[29] <= 9'b101011111; // bankl $d, $3 -// memory[30] <= 9'b001011010; // sb $d, $b -// memory[31] <= 9'b011001001; // addi $b, 1 -// memory[32] <= 9'b001010010; // sb $c, $b -// memory[33] <= 9'b010001000; // zero $b -// memory[34] <= 9'b011001001; // addi $b, 1 -// memory[35] <= 9'b101001010; // banks $b, $1 -// memory[36] <= 9'b101111100; // jb Inc -// // Check to see if any swaps have been made in the last iteration -// // SwapChk: -// memory[37] <= 9'b101001011; // bankl $b, $1 -// memory[38] <= 9'b110001001; // beq $b, JE -// memory[39] <= 9'b100100001; // jf Reset -// // JE: -// memory[40] <= 9'b100100011; // jf End -// // Reset: -// memory[41] <= 9'b010001000; // zero $b -// memory[42] <= 9'b101001000; // banks $b, $0 -// memory[43] <= 9'b101111011; // jb LoadNext -// // End: -// memory[44] <= 9'b000000000; // halt + //Bubble Sort + memory[0] <= 9'b000000001; // nop + // Setup + memory[1] <= 9'b010000000; // zero $a + memory[2] <= 9'b000100000; // lb $a, $a + memory[3] <= 9'b010001000; // zero $b + memory[4] <= 9'b010010000; // zero $c + memory[5] <= 9'b010011000; // zero $d + memory[6] <= 9'b101001000; // banks $b, $0 + memory[7] <= 9'b101001010; // banks $b, $1 + memory[8] <= 9'b100100011; // jf EndChk + // Increment current index to compare next pair of values + // Inc: + memory[9] <= 9'b101001001; // bankl $b, $0 + memory[10] <= 9'b011001001; // addi $b, 1 + memory[11] <= 9'b101001000; // banks $b, $0 + // Check if at the end of the array + // EndChk: + memory[12] <= 9'b101001001; // bankl $b, $0 + memory[13] <= 9'b011101000; // slt $b, $a + memory[14] <= 9'b110001001; // beq $b, JSC + memory[15] <= 9'b100100001; // jf LoadNext + // JSC: + memory[16] <= 9'b100110100; // jf SwapChk + // Load next values for comparison + // LoadNext: + memory[17] <= 9'b101001001; // bankl $b, $0 + memory[18] <= 9'b011001001; // addi $b, 1 + memory[19] <= 9'b000110010; // lb $c, $b + memory[20] <= 9'b011001001; // addi $b, 1 + memory[21] <= 9'b000111010; // lb $d, $b + // Compare loaded values to see if they need to be swapped + memory[22] <= 9'b101011110; // banks $d, $3 + memory[23] <= 9'b011111100; // slt $d, $c + memory[24] <= 9'b110011001; // beq $d, JI + memory[25] <= 9'b100100001; // jf Swap + // JI: + memory[26] <= 9'b101110010; // jb Inc + // Swap values in array + // Swap: + memory[27] <= 9'b101001001; // bankl $b, $0 + memory[28] <= 9'b011001001; // addi $b, 1 + memory[29] <= 9'b101011111; // bankl $d, $3 + memory[30] <= 9'b001011010; // sb $d, $b + memory[31] <= 9'b011001001; // addi $b, 1 + memory[32] <= 9'b001010010; // sb $c, $b + memory[33] <= 9'b010001000; // zero $b + memory[34] <= 9'b011001001; // addi $b, 1 + memory[35] <= 9'b101001010; // banks $b, $1 + memory[36] <= 9'b101111100; // jb Inc + // Check to see if any swaps have been made in the last iteration + // SwapChk: + memory[37] <= 9'b101001011; // bankl $b, $1 + memory[38] <= 9'b110001001; // beq $b, JE + memory[39] <= 9'b100100001; // jf Reset + // JE: + memory[40] <= 9'b100100011; // jf End + // Reset: + memory[41] <= 9'b010001000; // zero $b + memory[42] <= 9'b101001000; // banks $b, $0 + memory[43] <= 9'b101111011; // jb LoadNext + // End: + memory[44] <= 9'b000000000; // halt // Binary Search