From b4f855c65bc22df6ba1e4e6b36dc8e4c60734eb0 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Sat, 6 Apr 2019 14:15:51 -0400 Subject: [PATCH 01/17] Reverting removing the enable signals to test if that is the issue --- lab2CA.srcs/sources_1/new/BasicModules.v | 31 ++++++++++++++++-------- lab2CA.srcs/sources_1/new/RegFile.v | 7 ++++-- 2 files changed, 26 insertions(+), 12 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index 122e393..f1f476a 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -259,32 +259,43 @@ module comparator_tb(); endmodule module decoder ( + input wire en, input wire [1:0] index, output reg [3:0] regOut); - always @ (index) - case(index) - 2'b00: regOut <= 4'b1110; - 2'b01: regOut <= 4'b1101; - 2'b10: regOut <= 4'b1011; - 2'b11: regOut <= 4'b0111; - default: regOut <= 4'b1111; - endcase + always @(en, index)begin + if(en == 0)begin + case(index) + 2'b00: regOut <= 4'b1110; + 2'b01: regOut <= 4'b1101; + 2'b10: regOut <= 4'b1011; + 2'b11: regOut <= 4'b0111; + default: regOut <= 4'b1111; + endcase + end + else begin + regOut <= 4'b1111; + end + end endmodule //testbench module decoder_tb(); + reg enable; reg [1:0] indexIn; wire [3:0] regOut; decoder dec0( + .en(enable), .index(indexIn), - .regOut(regOut) - ); + .regOut(regOut)); initial begin + enable = 0; indexIn = 2'b00; #5 + enable = 1; + #5 indexIn = 2'b01; #5 indexIn = 2'b10; diff --git a/lab2CA.srcs/sources_1/new/RegFile.v b/lab2CA.srcs/sources_1/new/RegFile.v index ccd17e3..de3ea8e 100644 --- a/lab2CA.srcs/sources_1/new/RegFile.v +++ b/lab2CA.srcs/sources_1/new/RegFile.v @@ -1,6 +1,6 @@ `timescale 1ns / 1ps -module RegFile(input wire clk, reset, +module RegFile(input wire clk, reset, enable, input wire [1:0] write_index, op0_idx, op1_idx, input wire [8:0] write_data, output wire [8:0] op0, op1); @@ -11,6 +11,7 @@ module RegFile(input wire clk, reset, // To select a register En input must be 2'b00 decoder d0( + .en(enable), .index(write_index), .regOut(decOut) ); @@ -66,7 +67,7 @@ endmodule module regFile_tb(); reg [8:0] write_d; reg [1:0] w_idx, op0_idx, op1_idx; - reg reset,clk; + reg reset,clk, enable; wire [8:0] op0,op1; initial begin @@ -78,6 +79,7 @@ module regFile_tb(); RegFile regFile0( .clk(clk), + .enable(enable), .reset(reset), .write_index(w_idx), .op0_idx(op0_idx), @@ -92,6 +94,7 @@ module regFile_tb(); reset = 1; #5 reset = 0; + enable = 1; w_idx = 2'b00; op0_idx = 2'b00; op1_idx = 2'b00; From de8740a231b95d36b1ceb64ebddc6d99a5ad07a0 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Sat, 6 Apr 2019 14:16:26 -0400 Subject: [PATCH 02/17] Vivado runs/sim --- lab2CA.cache/wt/webtalk_pa.xml | 57 +- lab2CA.runs/.jobs/vrs_config_58.xml | 8 + lab2CA.runs/.jobs/vrs_config_59.xml | 8 + lab2CA.runs/.jobs/vrs_config_60.xml | 8 + lab2CA.runs/.jobs/vrs_config_61.xml | 8 + lab2CA.runs/.jobs/vrs_config_62.xml | 8 + lab2CA.runs/impl_1/CPU9bits.tcl | 152 ----- lab2CA.runs/impl_1/CPU9bits.vdi | 473 ---------------- .../impl_1/CPU9bits_bus_skew_routed.pb | Bin 30 -> 0 bytes .../impl_1/CPU9bits_bus_skew_routed.rpt | 15 - .../CPU9bits_clock_utilization_routed.rpt | 154 ----- .../impl_1/CPU9bits_control_sets_placed.rpt | 68 --- lab2CA.runs/impl_1/CPU9bits_drc_opted.pb | Bin 37 -> 0 bytes lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt | 61 -- lab2CA.runs/impl_1/CPU9bits_drc_routed.pb | Bin 37 -> 0 bytes lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt | 61 -- lab2CA.runs/impl_1/CPU9bits_io_placed.rpt | 526 ------------------ .../impl_1/CPU9bits_methodology_drc_routed.pb | Bin 52 -> 0 bytes .../CPU9bits_methodology_drc_routed.rpt | 145 ----- lab2CA.runs/impl_1/CPU9bits_opt.dcp | Bin 37264 -> 0 bytes lab2CA.runs/impl_1/CPU9bits_placed.dcp | Bin 163734 -> 0 bytes lab2CA.runs/impl_1/CPU9bits_power_routed.rpt | 151 ----- .../impl_1/CPU9bits_power_summary_routed.pb | Bin 722 -> 0 bytes lab2CA.runs/impl_1/CPU9bits_route_status.pb | Bin 43 -> 0 bytes lab2CA.runs/impl_1/CPU9bits_route_status.rpt | 11 - lab2CA.runs/impl_1/CPU9bits_routed.dcp | Bin 178325 -> 0 bytes lab2CA.runs/impl_1/CPU9bits_tb.vdi | 173 ------ lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb | Bin 37 -> 0 bytes lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt | 49 -- lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp | Bin 3472 -> 0 bytes .../impl_1/CPU9bits_timing_summary_routed.pb | 2 - .../impl_1/CPU9bits_timing_summary_routed.rpt | 173 ------ .../impl_1/CPU9bits_utilization_placed.pb | Bin 289 -> 0 bytes .../impl_1/CPU9bits_utilization_placed.rpt | 211 ------- lab2CA.runs/impl_1/gen_run.xml | 167 ------ lab2CA.runs/impl_1/htr.txt | 9 - lab2CA.runs/impl_1/init_design.pb | Bin 1837 -> 0 bytes lab2CA.runs/impl_1/opt_design.pb | Bin 12471 -> 0 bytes lab2CA.runs/impl_1/place_design.pb | Bin 12212 -> 0 bytes lab2CA.runs/impl_1/route_design.pb | Bin 12222 -> 0 bytes lab2CA.runs/impl_1/vivado.jou | 12 - lab2CA.runs/impl_1/vivado.pb | Bin 149 -> 0 bytes lab2CA.runs/impl_1/vivado_13064.backup.jou | 12 - lab2CA.runs/synth_1/CPU9bits.dcp | Bin 36344 -> 79019 bytes lab2CA.runs/synth_1/CPU9bits.tcl | 2 - lab2CA.runs/synth_1/CPU9bits.vds | 199 ++++--- .../synth_1/CPU9bits_utilization_synth.pb | Bin 289 -> 289 bytes .../synth_1/CPU9bits_utilization_synth.rpt | 27 +- lab2CA.runs/synth_1/gen_run.xml | 2 +- lab2CA.runs/synth_1/vivado.jou | 4 +- lab2CA.runs/synth_1/vivado.pb | Bin 50521 -> 51804 bytes lab2CA.sim/sim_1/behav/xsim/CPU9bits.tcl | 11 + lab2CA.sim/sim_1/behav/xsim/CPU9bits_vlog.prj | 16 + lab2CA.sim/sim_1/behav/xsim/webtalk.jou | 6 +- .../sim_1/behav/xsim/webtalk_11344.backup.jou | 12 - .../sim_1/behav/xsim/webtalk_11564.backup.jou | 12 + .../sim_1/behav/xsim/webtalk_12056.backup.jou | 12 - .../sim_1/behav/xsim/webtalk_28052.backup.jou | 12 + lab2CA.sim/sim_1/behav/xsim/xelab.pb | Bin 969 -> 4262 bytes .../CPU9bits_behav/Compile_Options.txt | 1 + .../CPU9bits_behav/TempBreakPointFile.txt | 1 + .../xsim/xsim.dir/CPU9bits_behav/obj/xsim_1.c | 169 ++++++ .../CPU9bits_behav/webtalk/xsim_webtalk.tcl | 32 ++ .../xsim/xsim.dir/CPU9bits_behav/xsim.mem | Bin 0 -> 20417 bytes lab2CA.sim/sim_1/behav/xsim/xvlog.pb | Bin 16 -> 8973 bytes 65 files changed, 453 insertions(+), 2787 deletions(-) create mode 100644 lab2CA.runs/.jobs/vrs_config_58.xml create mode 100644 lab2CA.runs/.jobs/vrs_config_59.xml create mode 100644 lab2CA.runs/.jobs/vrs_config_60.xml create mode 100644 lab2CA.runs/.jobs/vrs_config_61.xml create mode 100644 lab2CA.runs/.jobs/vrs_config_62.xml delete mode 100644 lab2CA.runs/impl_1/CPU9bits.tcl delete mode 100644 lab2CA.runs/impl_1/CPU9bits.vdi delete mode 100644 lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb delete mode 100644 lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt delete mode 100644 lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt delete mode 100644 lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt delete mode 100644 lab2CA.runs/impl_1/CPU9bits_drc_opted.pb delete mode 100644 lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt delete mode 100644 lab2CA.runs/impl_1/CPU9bits_drc_routed.pb delete mode 100644 lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt delete mode 100644 lab2CA.runs/impl_1/CPU9bits_io_placed.rpt delete mode 100644 lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb delete mode 100644 lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt delete mode 100644 lab2CA.runs/impl_1/CPU9bits_opt.dcp delete mode 100644 lab2CA.runs/impl_1/CPU9bits_placed.dcp delete mode 100644 lab2CA.runs/impl_1/CPU9bits_power_routed.rpt delete mode 100644 lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb delete mode 100644 lab2CA.runs/impl_1/CPU9bits_route_status.pb delete mode 100644 lab2CA.runs/impl_1/CPU9bits_route_status.rpt delete mode 100644 lab2CA.runs/impl_1/CPU9bits_routed.dcp delete mode 100644 lab2CA.runs/impl_1/CPU9bits_tb.vdi delete mode 100644 lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb delete mode 100644 lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt delete mode 100644 lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp delete mode 100644 lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.pb delete mode 100644 lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt delete mode 100644 lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb delete mode 100644 lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt delete mode 100644 lab2CA.runs/impl_1/gen_run.xml delete mode 100644 lab2CA.runs/impl_1/htr.txt delete mode 100644 lab2CA.runs/impl_1/init_design.pb delete mode 100644 lab2CA.runs/impl_1/opt_design.pb delete mode 100644 lab2CA.runs/impl_1/place_design.pb delete mode 100644 lab2CA.runs/impl_1/route_design.pb delete mode 100644 lab2CA.runs/impl_1/vivado.jou delete mode 100644 lab2CA.runs/impl_1/vivado.pb delete mode 100644 lab2CA.runs/impl_1/vivado_13064.backup.jou create mode 100644 lab2CA.sim/sim_1/behav/xsim/CPU9bits.tcl create mode 100644 lab2CA.sim/sim_1/behav/xsim/CPU9bits_vlog.prj delete mode 100644 lab2CA.sim/sim_1/behav/xsim/webtalk_11344.backup.jou create mode 100644 lab2CA.sim/sim_1/behav/xsim/webtalk_11564.backup.jou delete mode 100644 lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou create mode 100644 lab2CA.sim/sim_1/behav/xsim/webtalk_28052.backup.jou create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/Compile_Options.txt create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/TempBreakPointFile.txt create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/obj/xsim_1.c create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/xsim.mem diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 652ae82..391e24d 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,7 +17,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -27,17 +27,18 @@ This means code written to parse this file will need to be revisited each subseq - + - + - - + + + @@ -48,7 +49,8 @@ This means code written to parse this file will need to be revisited each subseq - + + @@ -58,18 +60,18 @@ This means code written to parse this file will need to be revisited each subseq - - + + - + - + @@ -88,12 +90,12 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -118,7 +120,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -129,9 +131,10 @@ This means code written to parse this file will need to be revisited each subseq - + + - + @@ -141,10 +144,10 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -162,7 +165,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -172,29 +175,33 @@ This means code written to parse this file will need to be revisited each subseq - - + + + + + - + - + + - + - +
diff --git a/lab2CA.runs/.jobs/vrs_config_58.xml b/lab2CA.runs/.jobs/vrs_config_58.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_58.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_59.xml b/lab2CA.runs/.jobs/vrs_config_59.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_59.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_60.xml b/lab2CA.runs/.jobs/vrs_config_60.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_60.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_61.xml b/lab2CA.runs/.jobs/vrs_config_61.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_61.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_62.xml b/lab2CA.runs/.jobs/vrs_config_62.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_62.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/impl_1/CPU9bits.tcl b/lab2CA.runs/impl_1/CPU9bits.tcl deleted file mode 100644 index 8e1b126..0000000 --- a/lab2CA.runs/impl_1/CPU9bits.tcl +++ /dev/null @@ -1,152 +0,0 @@ -# -# Report generation script generated by Vivado -# - -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -proc start_step { step } { - set stopFile ".stop.rst" - if {[file isfile .stop.rst]} { - puts "" - puts "*** Halting run - EA reset detected ***" - puts "" - puts "" - return -code error - } - set beginFile ".$step.begin.rst" - set platform "$::tcl_platform(platform)" - set user "$::tcl_platform(user)" - set pid [pid] - set host "" - if { [string equal $platform unix] } { - if { [info exist ::env(HOSTNAME)] } { - set host $::env(HOSTNAME) - } - } else { - if { [info exist ::env(COMPUTERNAME)] } { - set host $::env(COMPUTERNAME) - } - } - set ch [open $beginFile w] - puts $ch "" - puts $ch "" - puts $ch " " - puts $ch " " - puts $ch "" - close $ch -} - -proc end_step { step } { - set endFile ".$step.end.rst" - set ch [open $endFile w] - close $ch -} - -proc step_failed { step } { - set endFile ".$step.error.rst" - set ch [open $endFile w] - close $ch -} - -set_msg_config -id {Synth 8-256} -limit 10000 -set_msg_config -id {Synth 8-638} -limit 10000 - -start_step init_design -set ACTIVE_STEP init_design -set rc [catch { - create_msg_db init_design.pb - create_project -in_memory -part xc7k160tifbg484-2L - set_property design_mode GateLvl [current_fileset] - set_param project.singleFileAddWarning.threshold 0 - set_property webtalk.parent_dir {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/wt} [current_project] - set_property parent.project_path {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr} [current_project] - set_property ip_output_repo {{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/ip}} [current_project] - set_property ip_cache_permissions {read write} [current_project] - add_files -quiet {{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp}} - link_design -top CPU9bits -part xc7k160tifbg484-2L - close_msg_db -file init_design.pb -} RESULT] -if {$rc} { - step_failed init_design - return -code error $RESULT -} else { - end_step init_design - unset ACTIVE_STEP -} - -start_step opt_design -set ACTIVE_STEP opt_design -set rc [catch { - create_msg_db opt_design.pb - opt_design - write_checkpoint -force CPU9bits_opt.dcp - create_report "impl_1_opt_report_drc_0" "report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx" - close_msg_db -file opt_design.pb -} RESULT] -if {$rc} { - step_failed opt_design - return -code error $RESULT -} else { - end_step opt_design - unset ACTIVE_STEP -} - -start_step place_design -set ACTIVE_STEP place_design -set rc [catch { - create_msg_db place_design.pb - if { [llength [get_debug_cores -quiet] ] > 0 } { - implement_debug_core - } - place_design - write_checkpoint -force CPU9bits_placed.dcp - create_report "impl_1_place_report_io_0" "report_io -file CPU9bits_io_placed.rpt" - create_report "impl_1_place_report_utilization_0" "report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb" - create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt" - close_msg_db -file place_design.pb -} RESULT] -if {$rc} { - step_failed place_design - return -code error $RESULT -} else { - end_step place_design - unset ACTIVE_STEP -} - -start_step route_design -set ACTIVE_STEP route_design -set rc [catch { - create_msg_db route_design.pb - route_design - write_checkpoint -force CPU9bits_routed.dcp - create_report "impl_1_route_report_drc_0" "report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx" - create_report "impl_1_route_report_methodology_0" "report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx" - create_report "impl_1_route_report_power_0" "report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx" - create_report "impl_1_route_report_route_status_0" "report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb" - create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation " - create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt" - create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt" - create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx" - close_msg_db -file route_design.pb -} RESULT] -if {$rc} { - write_checkpoint -force CPU9bits_routed_error.dcp - step_failed route_design - return -code error $RESULT -} else { - end_step route_design - unset ACTIVE_STEP -} - diff --git a/lab2CA.runs/impl_1/CPU9bits.vdi b/lab2CA.runs/impl_1/CPU9bits.vdi deleted file mode 100644 index 492611e..0000000 --- a/lab2CA.runs/impl_1/CPU9bits.vdi +++ /dev/null @@ -1,473 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Mar 30 15:53:31 2019 -# Process ID: 13696 -# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1 -# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace -# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi -# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source CPU9bits.tcl -notrace -Command: link_design -top CPU9bits -part xc7k160tifbg484-2L -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7k160tifbg484-2L -INFO: [Project 1-570] Preparing netlist for logic optimization -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 581.816 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 587.391 ; gain = 332.746 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 603.059 ; gain = 15.668 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 257e1e38 - -Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1127.293 ; gain = 524.234 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.196 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.199 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 0 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1225.961 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.206 . Memory (MB): peak = 1225.961 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -INFO: [Pwropt 34-9] Applying IDT optimizations ... -INFO: [Pwropt 34-10] Applying ODC optimizations ... -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.000 | TNS=0.000 | -WARNING: [Power 33-232] No user defined clocks were found in the design! -Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation - - -Starting PowerOpt Patch Enables Task -INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. -INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports -Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2 -Ending PowerOpt Patch Enables Task | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Ending Power Optimization Task | Checksum: 257e1e38 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1335.719 ; gain = 109.758 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1335.719 ; gain = 748.328 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx -Command: report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1704] No user IP repositories specified -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt. -report_drc completed successfully -report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e0025bd - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: be8e8081 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 154227d99 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 154227d99 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 154227d99 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 154227d99 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000 -WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer -Phase 2 Global Placement | Checksum: 168f30526 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 168f30526 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 10b26ca05 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 171e1f517 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 171e1f517 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -Phase 4.1 Post Commit Optimization | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: eb242549 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Ending Placer Task | Checksum: 99ceed10 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -45 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -place_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.323 . Memory (MB): peak = 1335.719 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.130 . Memory (MB): peak = 1335.719 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: 7bcec753 ConstDB: 0 ShapeSum: 1e0025bd RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 16c615449 - -Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1486.191 ; gain = 150.473 -Post Restoration Checksum: NetGraph: 8cbcc684 NumContArr: dfa48dc5 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization -INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. - -Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 16c615449 - -Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1490.352 ; gain = 154.633 - -Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 16c615449 - -Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1490.352 ; gain = 154.633 - Number of Nodes with overlaps = 0 -Phase 2 Router Initialization | Checksum: 10053be5d - -Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 94ab7af4 - -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 15 - Number of Nodes with overlaps = 0 -Phase 4.1 Global Iteration 0 | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 -Phase 4 Rip-up And Reroute | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 5 Delay and Skew Optimization -Phase 5 Delay and Skew Optimization | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter -Phase 6.1 Hold Fix Iter | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 -Phase 6 Post Hold Fix | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.00626714 % - Global Horizontal Routing Utilization = 0.0102302 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Congestion Report -North Dir 1x1 Area, Max Cong = 18.9189%, No Congested Regions. -South Dir 1x1 Area, Max Cong = 10.8108%, No Congested Regions. -East Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions. -West Dir 1x1 Area, Max Cong = 27.9412%, No Congested Regions. - ------------------------------- -Reporting congestion hotspots ------------------------------- -Direction: North ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: South ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: East ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: West ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 - -Phase 7 Route finalize | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 148b7f565 - -Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:42 . Memory (MB): peak = 1517.723 ; gain = 182.004 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1517.723 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1517.723 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx -Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx -Command: report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx -Command: report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx -WARNING: [Power 33-232] No user defined clocks were found in the design! -Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -68 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. -INFO: [runtcl-4] Executing : report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Sat Mar 30 15:55:20 2019... diff --git a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb b/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb deleted file mode 100644 index 3390588d5da71a6f6866045d7ae5646edfab7b0e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 30 lcmd;LGcqu=&@-IGEZ|gHtWcbtTCPx(T3nh_Qapp10RVJW2(bVF diff --git a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt deleted file mode 100644 index dad6504..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt +++ /dev/null @@ -1,15 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:20 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx -| Design : CPU9bits -| Device : 7k160ti-fbg484 -| Speed File : -2L PRODUCTION 1.12 2017-02-17 ---------------------------------------------------------------------------------------------------------------------------------------------------------- - -Bus Skew Report - -No bus skew constraints - diff --git a/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt deleted file mode 100644 index be7e934..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt +++ /dev/null @@ -1,154 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:20 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt -| Design : CPU9bits -| Device : 7k160ti-fbg484 -| Speed File : -2L PRODUCTION 1.12 2017-02-17 -| Temperature Grade : I -------------------------------------------------------------------------------------------- - -Clock Utilization Report - -Table of Contents ------------------ -1. Clock Primitive Utilization -2. Global Clock Resources -3. Global Clock Source Details -4. Clock Regions: Key Resource Utilization -5. Clock Regions : Global Clock Summary -6. Device Cell Placement Summary for Global Clock g0 -7. Clock Region Cell Placement per Global Clock: Region X0Y1 - -1. Clock Primitive Utilization ------------------------------- - -+----------+------+-----------+-----+--------------+--------+ -| Type | Used | Available | LOC | Clock Region | Pblock | -+----------+------+-----------+-----+--------------+--------+ -| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | -| BUFH | 0 | 120 | 0 | 0 | 0 | -| BUFIO | 0 | 32 | 0 | 0 | 0 | -| BUFMR | 0 | 16 | 0 | 0 | 0 | -| BUFR | 0 | 32 | 0 | 0 | 0 | -| MMCM | 0 | 8 | 0 | 0 | 0 | -| PLL | 0 | 8 | 0 | 0 | 0 | -+----------+------+-----------+-----+--------------+--------+ - - -2. Global Clock Resources -------------------------- - -+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | -+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 22 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | -+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) - - -3. Global Clock Source Details ------------------------------- - -+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ -| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | -+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ -| src0 | g0 | IBUF/O | None | IOB_X0Y78 | X0Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | -+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) - - -4. Clock Regions: Key Resource Utilization ------------------------------------------- - -+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ -| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | -+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | -+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | -| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | -| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 21 | 2800 | 14 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | -| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | -| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | -| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | -| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | -| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 | -| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | -| X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | -+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -* Global Clock column represents track count; while other columns represents cell counts - - -5. Clock Regions : Global Clock Summary ---------------------------------------- - -All Modules -+----+----+----+ -| | X0 | X1 | -+----+----+----+ -| Y4 | 0 | 0 | -| Y3 | 0 | 0 | -| Y2 | 0 | 0 | -| Y1 | 1 | 0 | -| Y0 | 0 | 0 | -+----+----+----+ - - -6. Device Cell Placement Summary for Global Clock g0 ----------------------------------------------------- - -+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | -+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -| g0 | BUFG/O | n/a | | | | 22 | 0 | 0 | 0 | clk_IBUF_BUFG | -+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources -** IO Loads column represents load cell count of IO types -*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) -**** GT Loads column represents load cell count of GT types - - -+----+-----+----+ -| | X0 | X1 | -+----+-----+----+ -| Y4 | 0 | 0 | -| Y3 | 0 | 0 | -| Y2 | 0 | 0 | -| Y1 | 22 | 0 | -| Y0 | 0 | 0 | -+----+-----+----+ - - -7. Clock Region Cell Placement per Global Clock: Region X0Y1 ------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ -| g0 | n/a | BUFG/O | None | 22 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts - - - -# Location of BUFG Primitives -set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] - -# Location of IO Primitives which is load of clock spine - -# Location of clock ports -set_property LOC IOB_X0Y78 [get_ports clk] - -# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" -#startgroup -create_pblock {CLKAG_clk_IBUF_BUFG} -add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] -resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1} -#endgroup diff --git a/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt b/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt deleted file mode 100644 index b20d0aa..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt +++ /dev/null @@ -1,68 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:54:32 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt -| Design : CPU9bits -| Device : xc7k160ti -------------------------------------------------------------------------------------- - -Control Set Information - -Table of Contents ------------------ -1. Summary -2. Histogram -3. Flip-Flop Distribution -4. Detailed Control Set Information - -1. Summary ----------- - -+----------------------------------------------------------+-------+ -| Status | Count | -+----------------------------------------------------------+-------+ -| Number of unique control sets | 3 | -| Unused register locations in slices containing registers | 19 | -+----------------------------------------------------------+-------+ - - -2. Histogram ------------- - -+--------+--------------+ -| Fanout | Control Sets | -+--------+--------------+ -| 3 | 1 | -| 9 | 2 | -+--------+--------------+ - - -3. Flip-Flop Distribution -------------------------- - -+--------------+-----------------------+------------------------+-----------------+--------------+ -| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | -+--------------+-----------------------+------------------------+-----------------+--------------+ -| No | No | No | 3 | 1 | -| No | No | Yes | 0 | 0 | -| No | Yes | No | 0 | 0 | -| Yes | No | No | 0 | 0 | -| Yes | No | Yes | 0 | 0 | -| Yes | Yes | No | 18 | 8 | -+--------------+-----------------------+------------------------+-----------------+--------------+ - - -4. Detailed Control Set Information ------------------------------------ - -+----------------+----------------------------+------------------+------------------+----------------+ -| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | -+----------------+----------------------------+------------------+------------------+----------------+ -| clk_IBUF_BUFG | | | 1 | 3 | -| clk_IBUF_BUFG | FetchU/PC/E[0] | reset_IBUF | 4 | 9 | -| clk_IBUF_BUFG | FetchU/PC/Dout_reg[0]_1[0] | reset_IBUF | 4 | 9 | -+----------------+----------------------------+------------------+------------------+----------------+ - - diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_opted.pb b/lab2CA.runs/impl_1/CPU9bits_drc_opted.pb deleted file mode 100644 index 0158a2ad826bcd75c8436a6a29252340aee67559..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 37 scmd;LGcqtV(KDRH% - Ruledeck: default - Max violations: - Violations found: 3 -+----------+------------------+-----------------------------------------------------+------------+ -| Rule | Severity | Description | Violations | -+----------+------------------+-----------------------------------------------------+------------+ -| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | -| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | -| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | -+----------+------------------+-----------------------------------------------------+------------+ - -2. REPORT DETAILS ------------------ -NSTD-1#1 Critical Warning -Unspecified I/O Standard -12 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset. -Related violations: - -UCIO-1#1 Critical Warning -Unconstrained Logical Port -12 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset. -Related violations: - -CFGBVS-1#1 Warning -Missing CFGBVS and CONFIG_VOLTAGE Design Properties -Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: - - set_property CFGBVS value1 [current_design] - #where value1 is either VCCO or GND - - set_property CONFIG_VOLTAGE value2 [current_design] - #where value2 is the voltage provided to configuration bank 0 - -Refer to the device configuration user guide for more information. -Related violations: - - diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_routed.pb b/lab2CA.runs/impl_1/CPU9bits_drc_routed.pb deleted file mode 100644 index 0158a2ad826bcd75c8436a6a29252340aee67559..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 37 scmd;LGcqtV(KDRH% - Ruledeck: default - Max violations: - Violations found: 3 -+----------+------------------+-----------------------------------------------------+------------+ -| Rule | Severity | Description | Violations | -+----------+------------------+-----------------------------------------------------+------------+ -| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | -| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | -| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | -+----------+------------------+-----------------------------------------------------+------------+ - -2. REPORT DETAILS ------------------ -NSTD-1#1 Critical Warning -Unspecified I/O Standard -12 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset. -Related violations: - -UCIO-1#1 Critical Warning -Unconstrained Logical Port -12 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset. -Related violations: - -CFGBVS-1#1 Warning -Missing CFGBVS and CONFIG_VOLTAGE Design Properties -Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: - - set_property CFGBVS value1 [current_design] - #where value1 is either VCCO or GND - - set_property CONFIG_VOLTAGE value2 [current_design] - #where value2 is the voltage provided to configuration bank 0 - -Refer to the device configuration user guide for more information. -Related violations: - - diff --git a/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt b/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt deleted file mode 100644 index a4df712..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt +++ /dev/null @@ -1,526 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:54:32 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_io -file CPU9bits_io_placed.rpt -| Design : CPU9bits -| Device : xc7k160ti -| Speed File : -2L -| Package : fbg484 -| Package Version : FINAL 2012-06-26 -| Package Pin Delay Version : VERS. 2.0 2012-06-26 -------------------------------------------------------------------------------------------------- - -IO Information - -Table of Contents ------------------ -1. Summary -2. IO Assignments by Package Pin - -1. Summary ----------- - -+---------------+ -| Total User IO | -+---------------+ -| 12 | -+---------------+ - - -2. IO Assignments by Package Pin --------------------------------- - -+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | -+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | -| A3 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | | -| A4 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | | -| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A8 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | -| A9 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | -| A10 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| A11 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A13 | | High Range | IO_L4P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | -| A14 | | High Range | IO_L4N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | -| A15 | | High Range | IO_L9N_T1_DQS_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | -| A16 | | High Range | IO_L8N_T1_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | -| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | -| A18 | | High Range | IO_L10N_T1_AD4N_15 | User IO | | 15 | | | | | | | | | | | | | | -| A19 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | -| A20 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | -| A21 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | -| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| AA1 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| AA3 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| AA4 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| AA5 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA6 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | -| AA8 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA9 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA10 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA11 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| AA13 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA14 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA15 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| AA18 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA19 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA20 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA21 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| AB1 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| AB2 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| AB3 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| AB4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | -| AB5 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB6 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB7 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB8 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| AB10 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB11 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB12 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB13 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| AB15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| AB16 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| AB17 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| AB18 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| AB20 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | -| AB21 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | -| AB22 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| B1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | | -| B2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | | -| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B5 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | | -| B6 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | | -| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B8 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B10 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| B11 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| B12 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | -| B13 | | High Range | IO_L5N_T0_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | -| B14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | -| B15 | | High Range | IO_L9P_T1_DQS_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | -| B16 | | High Range | IO_L8P_T1_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | -| B17 | | High Range | IO_L10P_T1_AD4P_15 | User IO | | 15 | | | | | | | | | | | | | | -| B18 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | -| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B20 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | -| B21 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | -| B22 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | -| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | -| C3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | | -| C4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | | -| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C8 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| C9 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | -| C10 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | -| C11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | -| C12 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | -| C13 | | High Range | IO_L5P_T0_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | -| C14 | | High Range | IO_L7P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | -| C15 | | High Range | IO_L7N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | -| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C17 | | High Range | IO_L12P_T1_MRCC_AD5P_15 | User IO | | 15 | | | | | | | | | | | | | | -| C18 | | High Range | IO_L12N_T1_MRCC_AD5N_15 | User IO | | 15 | | | | | | | | | | | | | | -| C19 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | -| C20 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | -| C21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | -| C22 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | -| D1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | | -| D2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | | -| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | | -| D6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | | -| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | -| D9 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| D10 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | -| D11 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| D12 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | -| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D14 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | -| D15 | | High Range | IO_L11P_T1_SRCC_AD12P_15 | User IO | | 15 | | | | | | | | | | | | | | -| D16 | | High Range | IO_L11N_T1_SRCC_AD12N_15 | User IO | | 15 | | | | | | | | | | | | | | -| D17 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| D18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | -| D19 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | -| D20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | -| D21 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | -| D22 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | -| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | -| E3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | | -| E4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | | -| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E8 | | High Range | IO_24_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| E9 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | -| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E11 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| E12 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | -| E13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | -| E14 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | -| E15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | -| E16 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| E17 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| E18 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| E19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | -| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | -| E22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | -| F1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | | -| F2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | | -| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | | -| F6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | | -| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F8 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | -| F9 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | -| F10 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| F11 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| F12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | -| F13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | -| F14 | | High Range | IO_6_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | -| F15 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | -| F16 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | -| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | -| F19 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | -| F20 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | -| F21 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | -| F22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | -| G3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | | -| G4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | | -| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| G7 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | -| G8 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | -| G9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | -| G10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| G11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| G12 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| G13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | -| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | -| G16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | -| G17 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | -| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | -| G19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| G20 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | -| G21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | -| G22 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | -| H1 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | | -| H2 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | | -| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H6 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | -| H7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | -| H8 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | -| H9 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | -| H10 | | High Range | IO_18_T2_16 | User IO | | 16 | | | | | | | | | | | | | | -| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H12 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| H13 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | -| H14 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | -| H15 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | -| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | -| H17 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | -| H18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | -| H19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | -| H20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H22 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | -| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J4 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | | -| J5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | -| J6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | -| J7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | -| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| J14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| J16 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | -| J17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | -| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J19 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | -| J20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| J21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | -| J22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | -| K1 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| K2 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| K3 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| K4 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | | -| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | -| K7 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | -| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| K11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | -| K12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | -| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K16 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | -| K17 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | -| K18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| K19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | -| K20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| K21 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| K22 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | -| L1 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L3 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| L4 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | -| L5 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| L6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | -| L7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | -| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | -| L12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | -| L13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | -| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| L16 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| L18 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | -| L19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| L20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| L21 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | -| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M1 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| M2 | | High Performance | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| M3 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| M4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | -| M5 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| M6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | -| M7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | -| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| M11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | -| M12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | -| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M16 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | -| M17 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| M18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M20 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | -| M21 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | -| M22 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| N1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | -| N2 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| N3 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| N4 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| N5 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | -| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | -| N12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | -| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | -| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N17 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | -| N18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| N19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| N20 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | -| N21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| N22 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| P1 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| P2 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P4 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| P5 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| P6 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | -| P7 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | -| P8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P16 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | -| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | -| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| P19 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | -| P20 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | -| P21 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | -| P22 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | -| R1 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| R2 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| R3 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| R4 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| R5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | -| R6 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | -| R7 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | -| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | -| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| R16 | reset | High Range | IO_L20P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | -| R17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | -| R18 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | -| R19 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | -| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R21 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | -| R22 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | -| T1 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| T2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | -| T3 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| T4 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| T5 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| T6 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | | -| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| T8 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | -| T9 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | -| T10 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | -| T11 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | -| T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | -| T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | | -| T15 | result[2] | High Range | IO_L24P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| T16 | done | High Range | IO_L20N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| T19 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | -| T20 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| T21 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| T22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| U1 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| U2 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| U3 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| U5 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| U6 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | -| U7 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | -| U8 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| U9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | -| U10 | | High Performance | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| U11 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | -| U12 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | -| U13 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| U15 | result[1] | High Range | IO_L24N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| U16 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | -| U17 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| U18 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| U19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| U20 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | -| U21 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| U22 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| V2 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| V3 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| V4 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| V5 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | | -| V6 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | -| V7 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| V8 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| V9 | | High Performance | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| V10 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| V12 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| V13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| V14 | result[0] | High Range | IO_25_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| V15 | result[4] | High Range | IO_L23P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| V17 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | -| V18 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| V19 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| V20 | clk | High Range | IO_L11P_T1_SRCC_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | -| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| V22 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| W1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| W2 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| W3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | -| W4 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| W5 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| W6 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | -| W7 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| W9 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| W10 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| W11 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| W12 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | -| W14 | result[6] | High Range | IO_L22P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| W15 | result[3] | High Range | IO_L23N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| W16 | result[8] | High Range | IO_L21P_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| W17 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| W19 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| W20 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| W21 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| W22 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y1 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y2 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y3 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y4 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| Y6 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y7 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y8 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y9 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | -| Y11 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y12 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y13 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y14 | result[5] | High Range | IO_L22N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| Y16 | result[7] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| Y17 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y18 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y19 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| Y21 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y22 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | -+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -* Default value -** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. - - diff --git a/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb b/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb deleted file mode 100644 index 1cf59643e28ed0872ba5627775b2fda1a220b706..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 52 zcmd;LGcqtV(=(jJEajV8l98X1pOc?nso - Max violations: - Violations found: 22 -+-----------+----------+-----------------------------+------------+ -| Rule | Severity | Description | Violations | -+-----------+----------+-----------------------------+------------+ -| TIMING-17 | Warning | Non-clocked sequential cell | 22 | -+-----------+----------+-----------------------------+------------+ - -2. REPORT DETAILS ------------------ -TIMING-17#1 Warning -Non-clocked sequential cell -The clock pin FetchU/PC/Dout_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#2 Warning -Non-clocked sequential cell -The clock pin FetchU/PC/Dout_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#3 Warning -Non-clocked sequential cell -The clock pin FetchU/PC/Dout_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#4 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#5 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#6 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#7 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#8 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#9 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#10 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[6]/C is not reached by a timing clock -Related violations: - -TIMING-17#11 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[7]/C is not reached by a timing clock -Related violations: - -TIMING-17#12 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[8]/C is not reached by a timing clock -Related violations: - -TIMING-17#13 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#14 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#15 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#16 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#17 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#18 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#19 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[6]/C is not reached by a timing clock -Related violations: - -TIMING-17#20 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[7]/C is not reached by a timing clock -Related violations: - -TIMING-17#21 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[8]/C is not reached by a timing clock -Related violations: - -TIMING-17#22 Warning -Non-clocked sequential cell -The clock pin dM/memory_reg/CLKARDCLK is not reached by a timing clock -Related violations: - - diff --git a/lab2CA.runs/impl_1/CPU9bits_opt.dcp b/lab2CA.runs/impl_1/CPU9bits_opt.dcp deleted file mode 100644 index acc9d4fc697168b92b328d7e422542db6d3a91b4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 37264 zcmaI7W0Yh;*QQ;z-DTUhZQHiHx@?#T?qu@z-N!O(z!fS`azeSPJ%>n}(Hfq{TJL4klE0jjBqBfYzwZA_A!L!cm<*y@u; zSDiJcnBZ;U9m#+pnGg}wMh(=2BDq*-pW)Mv292GH6n4u^ju$x#14|a}3pB2yK2k<3 zX98y1cpKZ2ahKODrPPlqKjwrWa49SPeK7m24xEY{BVxZZI@Rp}v$|0d`9yFtMx^#< zvRsdnGe04g%?P?kK&01k1nVFGmvNUBvX$)WVJ3{q5SiC*f%Q?EQ<0 zN`uOil-vfLAR#nHDN~WG8O+`v{6*5oWAY#v^WNXT_(`B4UXrsZV(l{*HLi~>bJy<5 z>zGGQIAsDC-vX>o6Jd#|r7h-EIwEyls*hE4de!d4a829N1tmtRRz{7Msy-X4e#Tif zo@@VtTl9R^s44v;{Sla=^EIc)Dsk-hn^QI;BD(l^i`zZ%`riB}q@2waFI+|nM_Eru zoL>v0?YHlwQ{@x1;(ra(``^^kP97j2?_v-jIKVK8D5`N8Te-T>o0*zl`B*uSNF+Z0 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zu#hdwNRP9|@uN)rNwRc^Z_Ta4JO}d;`30xzbf{1jju5`W&%s;=n@w^xMFd0u;P03T zD1%b@QEGwbuf9YHgjT1)v+f;Ao z-?jaH?)n>?_4yn8eJ1<8m*3}{KYIDoW((hc^z!En^gI0fVEh{n_xl$NADU{4Pm%v< zg8@Gh;EwL{M+9&Jq - - -1.1 On-Chip Components ----------------------- - -+----------------+-----------+----------+-----------+-----------------+ -| On-Chip | Power (W) | Used | Available | Utilization (%) | -+----------------+-----------+----------+-----------+-----------------+ -| Slice Logic | 1.248 | 107 | --- | --- | -| LUT as Logic | 1.231 | 73 | 101400 | 0.07 | -| Register | 0.012 | 21 | 202800 | 0.01 | -| BUFG | 0.005 | 1 | 32 | 3.13 | -| Others | 0.000 | 4 | --- | --- | -| Signals | 1.328 | 114 | --- | --- | -| Block RAM | 0.060 | 0.5 | 325 | 0.15 | -| I/O | 8.393 | 12 | 285 | 4.21 | -| Static Power | 0.142 | | | | -| Total | 11.172 | | | | -+----------------+-----------+----------+-----------+-----------------+ - - -1.2 Power Supply Summary ------------------------- - -+-----------+-------------+-----------+-------------+------------+ -| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | -+-----------+-------------+-----------+-------------+------------+ -| Vccint | 0.950 | 2.849 | 2.775 | 0.074 | -| Vccaux | 1.800 | 0.707 | 0.687 | 0.020 | -| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | -| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | -| Vcco18 | 1.800 | 3.975 | 3.974 | 0.001 | -| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | -| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | -| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | -| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccbram | 0.950 | 0.007 | 0.005 | 0.002 | -| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | -| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | -| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccadc | 1.800 | 0.018 | 0.000 | 0.018 | -+-----------+-------------+-----------+-------------+------------+ - - -1.3 Confidence Level --------------------- - -+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ -| User Input Data | Confidence | Details | Action | -+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ -| Design implementation state | High | Design is routed | | -| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | -| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | -| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | -| Device models | High | Device models are Production | | -| | | | | -| Overall confidence level | Low | | | -+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ - - -2. Settings ------------ - -2.1 Environment ---------------- - -+-----------------------+--------------------------+ -| Ambient Temp (C) | 25.0 | -| ThetaJA (C/W) | 2.5 | -| Airflow (LFM) | 250 | -| Heat Sink | medium (Medium Profile) | -| ThetaSA (C/W) | 4.2 | -| Board Selection | medium (10"x10") | -| # of Board Layers | 12to15 (12 to 15 Layers) | -| Board Temperature (C) | 25.0 | -+-----------------------+--------------------------+ - - -2.2 Clock Constraints ---------------------- - -+-------+--------+-----------------+ -| Clock | Domain | Constraint (ns) | -+-------+--------+-----------------+ - - -3. Detailed Reports -------------------- - -3.1 By Hierarchy ----------------- - -+----------+-----------+ -| Name | Power (W) | -+----------+-----------+ -| CPU9bits | 11.030 | -| FetchU | 1.191 | -| PC | 1.191 | -| RF | 1.317 | -| r0 | 0.812 | -| r1 | 0.506 | -| dM | 0.113 | -+----------+-----------+ - - diff --git a/lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb b/lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb deleted file mode 100644 index f938afde86790d09b9285560c09d140de6296573..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 722 zcmZ|N&ui2`6bJAbS{4)w{e)re@g>N)5~1`mn9YE31M9a0Y$|uZ|NWC6_+*WS%u<6?-5JbW P@Pr+xJ1KbQCq{n&<&ff_ diff --git a/lab2CA.runs/impl_1/CPU9bits_route_status.pb b/lab2CA.runs/impl_1/CPU9bits_route_status.pb deleted file mode 100644 index a8cf1799c0a7c67d63ef9070a85ee399521294e5..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 43 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default - Max violations: - Violations found: 1 -+----------+----------+-----------------------------------------------------+------------+ -| Rule | Severity | Description | Violations | -+----------+----------+-----------------------------------------------------+------------+ -| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | -+----------+----------+-----------------------------------------------------+------------+ - -2. REPORT DETAILS ------------------ -CFGBVS-1#1 Warning -Missing CFGBVS and CONFIG_VOLTAGE Design Properties -Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: - - set_property CFGBVS value1 [current_design] - #where value1 is either VCCO or GND - - set_property CONFIG_VOLTAGE value2 [current_design] - #where value2 is the voltage provided to configuration bank 0 - -Refer to the device configuration user guide for more information. -Related violations: - - diff --git a/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp b/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp deleted file mode 100644 index a888ad70601491891872dbbbf48bddb830ca3a16..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3472 zcmZ{n2{hDQAIHZwmaz;W;(25%lWmM`2uaB@_9c6k89QSML&$Ej45E$5k|iNRXhaeQ z8A_JOSR#@wYLN9E@AI7VyyiUbJ?EbLKmYUpoO^%w_x&w@69gSSHvj-&0?gkDHImvF z<8h?{0Itvh0F0EkD5SqksILz$%g`@Y6P!5k)ye?=g7LQOy66+mtCGyI7uzP8n1*oO zr|c{Dw}$mUD`ehVdNrU{*PLZZScn9c6~kRJIc#EP$JTF|l6`B({$T2dY)@skwbL#X z^VO=IclpzTC~v@RJ*o9j)hS^Y)twBRTHIo2h$Ol{@&x9a+ zie>uq9@z;B;++SW$izDOiLJLKFzv3?mVBakz>P3#uIB9=ro1#UNrysF67ya;^1NH0ud` z3J>|`h%#8m1 z$}T>BSOdfesO`?n7%7(0WaJq#%@6(&KSqvdo3|f?b3EOGH(yH!1`=sQDj84bL!4Pb zF-~FxY0w5skfmL;SF{F=FMAiQ!s8X253rJp?1LZ`h5$&+#Lo;kN<*pG)b8Znurvm` z#dTd6aPQ`~mGqhpCMOpBx>KLfFaFAgN1x2W zMHqS_OhOdP3Y_9?z~}CH@^8tL`)A}XEX`L37(TWwe!Dx7Z! zu_=^(AYW3uv?@q?;CbWZi_Fo?SYg9hrb1&JFmj03-|t*;Ea1F7bS~_GVdWP^=u=?mMVg{FG#C(+bpDXgS?+fp^L5h$D^Jr*@ds{tfI*tzUUJe zyG7ZZq}QoCuWSy<_cs~aqIkcDr=KfW2DV(Ti&L`X*J}@gEh;r;S zr${B4GQm`m@kAp7K|OuMK14c3Pf9Np^G-H-s}CWgPc$S->h%S@>yed3NW+HYm0@NQ zM$)|oeLa=>QaybGb+!6Z`u*Kf2urAfCDa5;<8rzkh%*i48`RAJQEB$uK-QfoO7>8s z=$2ZufhcEJQ=->rO>i1cm~7#@=%On*o_XmR#7Gz`NaAzg8tXFZHm$5T_jE4dIbRpD z!xt8<=Kjo~Cm#Q+;jQxSKGD9mk87!x9C44Y`Eyb8o<@S)=gpyMUc)_w*v8R{-3oho z*IWW8U?1HyUV}<@OazmWr5QnEw=n*%HrbX=b^dTUH`%6(&+IS-bm^a$vi6fpk%st7GQ=!PU zQ6(MxK{O_$)rQ>7<{}CFXw*3PZ4fnPNLvI}y_=roQ@Lu$OVQkG_NQx#QEf1XZNP9=2L{mab#(mk>lYmCc89M&Mdhsd2t5+l zh%|%Ao z&5mQQ(epYy$wtO0<*jhyOXG$+uaOZs&(oUc#Z<&y(^i+>Hzc?f>I=Ji;Yh9GVYafM z9^Tmc@taC@nP>Cef2Xf%u_i&?cn=xUlb-uxXe7|1OgnsR> zHd3ciOaUTT4+YcuPIQvF$P6)kdi&~{crm7}FaA(csUYBbdD=!qtad}^2;Fw)`dX^B zF7V}cuzA{#A)yl-Q5KaR=r1a*>8v*95Kr`XB%#F$AbtXz3m%t9j zN~wB@O)fI20qy%`Q3WfEs`jey_0s9#<~ed~%g@YyLZjG3TWg=*Y&PwBxRQ=E1<@BV zst*HF+Ykf@QgNn;K+<=Y?hcq?R$x!MfEtnj?08&K+}Ep01HsQi~*ebXLE!wX2 zifXH7@Amc@@DXU)+q9Rn=SGvJfeCFfUzh?q6Wg)4(nyB${UIyb=So)nT@#bZR_(j8 z^6$-fC0!=hls><=XdK*|=3G~4;|oj50JYLKSghaDNj8%BaiRN4Ds84%sALOq%zD#)>-)vB)5e8%m6M~NHtlj-pd2i?q zDW-a?b@Z@$b{sR(^xdABPP^^r`C3S|De2S8N++g=quH7R^Z3U2L~H>Kqw2>&a&i4T zP$Zfh;nt%+ly{@QLQkRbiqbnI*=)2`M%{dYbk2PyZVfL`U$=E**Kg2gVY9c;frQC9 z5Et>0A>0iRte1(PwaR{tcdDn|D_qg^$2%u;iyo@aT5a5dl(G^=%!{Pt zoH9gga_;ir3}M4=y`-A-&4$1 zrqo=cu{WP^4d=Fe)RZIVZ4|s!zg!Lp}23MvhbLlds0SfJt>GDf&c&+fVRAk vq*s7;kjEus_uv3`Tem={oVha6M&9c(TnBSe(e3O`Equ3=ET;_6jrb9CL3KnOQK|wpWq?2<}QU?BH-;Dg|P% zm1kgZaQrLJ(9q|6RAJGcHixsSKw5)okN0r&f0;L%(Vv+j!!`(!&?^+xz`m)IJUZh*uCB$ y@-C2Ua9HXCVt?|Hau11cHHvrk_x1Jn(}8k49R2)Uebxqol>7yf4faQaKx_ckEl%M8 diff --git a/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt b/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt deleted file mode 100644 index e85b036..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt +++ /dev/null @@ -1,211 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:54:32 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb -| Design : CPU9bits -| Device : 7k160tifbg484-2L -| Design State : Fully Placed -------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Slice Logic Distribution -3. Memory -4. DSP -5. IO and GT Specific -6. Clocking -7. Specific Feature -8. Primitives -9. Black Boxes -10. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs | 73 | 0 | 101400 | 0.07 | -| LUT as Logic | 73 | 0 | 101400 | 0.07 | -| LUT as Memory | 0 | 0 | 35000 | 0.00 | -| Slice Registers | 21 | 0 | 202800 | 0.01 | -| Register as Flip Flop | 21 | 0 | 202800 | 0.01 | -| Register as Latch | 0 | 0 | 202800 | 0.00 | -| F7 Muxes | 0 | 0 | 50700 | 0.00 | -| F8 Muxes | 0 | 0 | 25350 | 0.00 | -+-------------------------+------+-------+-----------+-------+ - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 21 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Slice Logic Distribution ---------------------------- - -+--------------------------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+--------------------------------------------+------+-------+-----------+-------+ -| Slice | 21 | 0 | 25350 | 0.08 | -| SLICEL | 11 | 0 | | | -| SLICEM | 10 | 0 | | | -| LUT as Logic | 73 | 0 | 101400 | 0.07 | -| using O5 output only | 0 | | | | -| using O6 output only | 65 | | | | -| using O5 and O6 | 8 | | | | -| LUT as Memory | 0 | 0 | 35000 | 0.00 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 0 | 0 | | | -| Slice Registers | 21 | 0 | 202800 | 0.01 | -| Register driven from within the Slice | 4 | | | | -| Register driven from outside the Slice | 17 | | | | -| LUT in front of the register is unused | 0 | | | | -| LUT in front of the register is used | 17 | | | | -| Unique Control Sets | 3 | | 25350 | 0.01 | -+--------------------------------------------+------+-------+-----------+-------+ -* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. - - -3. Memory ---------- - -+-------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 0.5 | 0 | 325 | 0.15 | -| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | -| RAMB18 | 1 | 0 | 650 | 0.15 | -| RAMB18E1 only | 1 | | | | -+-------------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -4. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 600 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -5. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 12 | 0 | 285 | 4.21 | -| IOB Master Pads | 6 | | | | -| IOB Slave Pads | 5 | | | | -| Bonded IPADs | 0 | 0 | 14 | 0.00 | -| Bonded OPADs | 0 | 0 | 8 | 0.00 | -| PHY_CONTROL | 0 | 0 | 8 | 0.00 | -| PHASER_REF | 0 | 0 | 8 | 0.00 | -| OUT_FIFO | 0 | 0 | 32 | 0.00 | -| IN_FIFO | 0 | 0 | 32 | 0.00 | -| IDELAYCTRL | 0 | 0 | 8 | 0.00 | -| IBUFDS | 0 | 0 | 275 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 1 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | -| ILOGIC | 0 | 0 | 285 | 0.00 | -| OLOGIC | 0 | 0 | 285 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -6. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 1 | 0 | 32 | 3.13 | -| BUFIO | 0 | 0 | 32 | 0.00 | -| MMCME2_ADV | 0 | 0 | 8 | 0.00 | -| PLLE2_ADV | 0 | 0 | 8 | 0.00 | -| BUFMRCE | 0 | 0 | 16 | 0.00 | -| BUFHCE | 0 | 0 | 120 | 0.00 | -| BUFR | 0 | 0 | 32 | 0.00 | -+------------+------+-------+-----------+-------+ - - -7. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -8. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| LUT6 | 37 | LUT | -| LUT4 | 27 | LUT | -| FDRE | 21 | Flop & Latch | -| OBUF | 10 | IO | -| LUT5 | 10 | LUT | -| LUT2 | 4 | LUT | -| LUT3 | 3 | LUT | -| IBUF | 2 | IO | -| RAMB18E1 | 1 | Block Memory | -| BUFG | 1 | Clock | -+----------+------+---------------------+ - - -9. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -10. Instantiated Netlists -------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml deleted file mode 100644 index fdb8b46..0000000 --- a/lab2CA.runs/impl_1/gen_run.xml +++ /dev/null @@ -1,167 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/lab2CA.runs/impl_1/htr.txt b/lab2CA.runs/impl_1/htr.txt deleted file mode 100644 index a32836e..0000000 --- a/lab2CA.runs/impl_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. 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b/lab2CA.runs/synth_1/CPU9bits.tcl @@ -17,8 +17,6 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } -set_msg_config -id {Synth 8-256} -limit 10000 -set_msg_config -id {Synth 8-638} -limit 10000 create_project -in_memory -part xc7k160tifbg484-2L set_param project.singleFileAddWarning.threshold 0 diff --git a/lab2CA.runs/synth_1/CPU9bits.vds b/lab2CA.runs/synth_1/CPU9bits.vds index a64412c..19e8641 100644 --- a/lab2CA.runs/synth_1/CPU9bits.vds +++ b/lab2CA.runs/synth_1/CPU9bits.vds @@ -2,8 +2,8 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Mar 30 15:52:45 2019 -# Process ID: 9028 +# Start of session at: Sat Apr 6 14:00:40 2019 +# Process ID: 8416 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1 # Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds @@ -15,9 +15,9 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 18388 +INFO: Helper process launched with PID 19172 --------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 364.258 ; gain = 100.730 +Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 362.617 ; gain = 101.777 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] @@ -26,76 +26,77 @@ INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Education INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] -INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:266] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268] INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] -INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766] -INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766] -INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396] -INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:401] -INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396] +INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777] +INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777] +INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412] +INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407] INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] -INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325] -INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:331] -INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325] +INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342] +INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336] INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] -INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1300] -INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1365] -INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676] -INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676] -INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1365] -INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1300] -INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713] -INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713] -INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632] -INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632] +INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311] +INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376] +INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687] +INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687] +INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376] +INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311] +INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724] +INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724] +INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643] +INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643] INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] -INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:842] -INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:842] -INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:916] -INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:916] -INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:879] -INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:879] -INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309] -INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309] -INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1414] -INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1414] -INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524] -INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:530] -INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524] +INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] +INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] +INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] +INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] +INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] +INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] +INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541] +INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:13] INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] -INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:985] -INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:985] -INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339] -INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:345] -INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339] +INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996] +INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996] +INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356] +INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] +WARNING: [Synth 8-3331] design dataMemory has unconnected port address[8] +WARNING: [Synth 8-3331] design dataMemory has unconnected port address[7] --------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355 +Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.656 ; gain = 157.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355 +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.656 ; gain = 157.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k160tifbg484-2L --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.656 ; gain = 157.816 +--------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7k160tifbg484-2L --------------------------------------------------------------------------------- -INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5) ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 420.883 ; gain = 157.355 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 418.656 ; gain = 157.816 --------------------------------------------------------------------------------- INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_3bit) to 'SE3' @@ -114,11 +115,11 @@ Detailed RTL Component Info : +---Registers : 9 Bit Registers := 10 +---RAMs : - 4K Bit RAMs := 1 + 909 Bit RAMs := 1 +---Muxes : - 7 Input 9 Bit Muxes := 1 4 Input 9 Bit Muxes := 5 2 Input 9 Bit Muxes := 8 + 2 Input 4 Bit Muxes := 2 4 Input 4 Bit Muxes := 2 16 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 @@ -139,19 +140,16 @@ Detailed RTL Component Info : +---Muxes : 4 Input 9 Bit Muxes := 1 8 Input 2 Bit Muxes := 1 -Module instructionMemory -Detailed RTL Component Info : -+---Muxes : - 7 Input 9 Bit Muxes := 1 Module dataMemory Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 +---RAMs : - 4K Bit RAMs := 1 + 909 Bit RAMs := 1 Module decoder Detailed RTL Component Info : +---Muxes : + 2 Input 4 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 Module register Detailed RTL Component Info : @@ -199,24 +197,33 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- +ROM: ++------------------+------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------------+------------+---------------+----------------+ +|instructionMemory | p_0_out | 64x9 | LUT | +|CPU9bits | p_0_out | 64x9 | LUT | ++------------------+------------+---------------+----------------+ + + Block RAM: Preliminary Mapping Report (see note below) +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ -|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 | +|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 | +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- -INFO: [Synth 8-6837] The timing for the instance i_1/dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance i_0/dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. Report RTL Partitions: +-+--------------+------------+----------+ @@ -228,7 +235,7 @@ No constraint files found. Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting @@ -238,7 +245,7 @@ Block RAM: Final Mapping Report +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ -|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 | +|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 | +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ --------------------------------------------------------------------------------- @@ -255,7 +262,7 @@ Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-6837] The timing for the instance dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -279,7 +286,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- Report Check Netlist: @@ -292,7 +299,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -304,25 +311,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -339,51 +346,59 @@ Report Cell Usage: | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| -|2 |LUT2 | 4| -|3 |LUT3 | 3| -|4 |LUT4 | 27| -|5 |LUT5 | 10| -|6 |LUT6 | 37| -|7 |RAMB18E1 | 1| -|8 |FDRE | 21| -|9 |IBUF | 2| -|10 |OBUF | 10| +|2 |LUT2 | 13| +|3 |LUT3 | 21| +|4 |LUT4 | 23| +|5 |LUT5 | 33| +|6 |LUT6 | 135| +|7 |MUXF7 | 11| +|8 |RAMB18E1 | 1| +|9 |FDRE | 81| +|10 |IBUF | 2| +|11 |OBUF | 10| +------+---------+------+ Report Instance Areas: +------+---------+-----------+------+ | |Instance |Module |Cells | +------+---------+-----------+------+ -|1 |top | | 116| -|2 | FetchU |FetchUnit | 31| -|3 | PC |register_1 | 31| -|4 | RF |RegFile | 71| -|5 | r0 |register | 42| -|6 | r1 |register_0 | 29| -|7 | dM |dataMemory | 1| +|1 |top | | 331| +|2 | Bank |RegFile | 45| +|3 | r0 |register_5 | 15| +|4 | r1 |register_6 | 9| +|5 | r2 |register_7 | 11| +|6 | r3 |register_8 | 10| +|7 | FetchU |FetchUnit | 135| +|8 | PC |register_4 | 135| +|9 | RF |RegFile_0 | 137| +|10 | r0 |register | 87| +|11 | r1 |register_1 | 17| +|12 | r2 |register_2 | 14| +|13 | r3 |register_3 | 19| +|14 | dM |dataMemory | 1| +------+---------+-----------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 -Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 +Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 684.082 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 683.707 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +72 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 684.082 ; gain = 433.695 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 684.082 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 683.707 ; gain = 435.820 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 683.707 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sat Mar 30 15:53:22 2019... +INFO: [Common 17-206] Exiting Vivado at Sat Apr 6 14:01:18 2019... diff --git a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb index 0e56dc691e9a43f25e74e35505252f7307b33505..14cb01249cafaf1e704987a1ac4492f008326991 100644 GIT binary patch delta 42 ycmZ3;w2*0nxxyl+xx5TKZXQp0|IJXgeJjMk;OM+pn1Sb*d#i}kb0@or;imvBW)7YJ delta 42 zcmV+_0M-AY0-*wsHz24%oecmCMo8riB&aDo?GgY0l0v-`01U=Qg%p`^lRc4F${;xo AUH||9 diff --git a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt index 2b9cc8b..336ac7e 100644 --- a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt +++ b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:53:22 2019 +| Date : Sat Apr 6 14:01:18 2019 | Host : WM-G75VW running 64-bit major release (build 9200) | Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb | Design : CPU9bits @@ -30,13 +30,13 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 73 | 0 | 101400 | 0.07 | -| LUT as Logic | 73 | 0 | 101400 | 0.07 | +| Slice LUTs* | 193 | 0 | 101400 | 0.19 | +| LUT as Logic | 193 | 0 | 101400 | 0.19 | | LUT as Memory | 0 | 0 | 35000 | 0.00 | -| Slice Registers | 21 | 0 | 202800 | 0.01 | -| Register as Flip Flop | 21 | 0 | 202800 | 0.01 | +| Slice Registers | 81 | 0 | 202800 | 0.04 | +| Register as Flip Flop | 81 | 0 | 202800 | 0.04 | | Register as Latch | 0 | 0 | 202800 | 0.00 | -| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| F7 Muxes | 11 | 0 | 50700 | 0.02 | | F8 Muxes | 0 | 0 | 25350 | 0.00 | +-------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -57,7 +57,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 0 | Yes | Set | - | -| 21 | Yes | Reset | - | +| 81 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -152,13 +152,14 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| LUT6 | 37 | LUT | -| LUT4 | 27 | LUT | -| FDRE | 21 | Flop & Latch | +| LUT6 | 135 | LUT | +| FDRE | 81 | Flop & Latch | +| LUT5 | 33 | LUT | +| LUT4 | 23 | LUT | +| LUT3 | 21 | LUT | +| LUT2 | 13 | LUT | +| MUXF7 | 11 | MuxFx | | OBUF | 10 | IO | -| LUT5 | 10 | LUT | -| LUT2 | 4 | LUT | -| LUT3 | 3 | LUT | | IBUF | 2 | IO | | RAMB18E1 | 1 | Block Memory | | BUFG | 1 | Clock | diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml index 6b9dffe..6b83595 100644 --- a/lab2CA.runs/synth_1/gen_run.xml +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/lab2CA.runs/synth_1/vivado.jou b/lab2CA.runs/synth_1/vivado.jou index 1cb2f8d..fe3cd53 100644 --- a/lab2CA.runs/synth_1/vivado.jou +++ b/lab2CA.runs/synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Mar 30 15:52:45 2019 -# Process ID: 9028 +# Start of session at: Sat Apr 6 14:00:40 2019 +# Process ID: 8416 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1 # Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds diff --git a/lab2CA.runs/synth_1/vivado.pb b/lab2CA.runs/synth_1/vivado.pb index 81e985f66ffa9891b2212f9cf165835b7700589d..6d9392fc435c9a4484d553c31fb285463a73c913 100644 GIT binary patch delta 2597 zcmbtWYitx%6lP}o+NJN7K7mecN#D!dnc3L~pgd|r?StL5ghGRT?b=HZkBLwdO%oE7!~nh0Rw$%tlmv{_h9AZUq>VAg@B{IO;17-W-dRGcSgLL|Gv}W3 zedm7X&bf2v>m$1F-qxL0c}|9z>U5~#b222Oip;_)p`+E~71jtyL`JjO4EImw;Q@X+ zjvd;$3Q{6qdtTJ%V?VMsG(Fe+d& z|1NJ~`5{!g7K#ggBtx81*upV@Mty%pF-NJ7RMixV@cPojIMZ%izE0t)HM9f*z$lb(n>#YUMraGyXPi>cYnT6=$nG{+9UG`LbVl|OP zLR8idYkH%>o@~Se8&-0}$fwH%4=V5RCN@=n?g&xsNX}u*hgD@nxyYD~jrCl`AGVo*XwQ%x?MuI&mScI(!-wtQ$4#F3s%RzQXkXo|@LXPbD^5YukThThJ zXocHbjzMip0o-jo1#7n@z~vnouyUsjYFZLu+C}Y+_}*4sEZpcz#g?`(7h&1pz0Pbf zxUNT74w5ASPrI^`vs8&}Oi_AVysVOqsYnY$eB?C_$T6}4AV4pYG zDdiYq49-n;HoAjTeRE@53>)CUo-{Zg(nIoVN$~SPG_$AQje}K3Ghy7JZ|I&&X*5)Z z>wK=BU2dViwaYDNzp&tJs1-J~?I4{agoR3Xcd%2~D{S$&$UQ7ncXjV_ce%Z^tJVdC zFif?xIdgEoX? zy~}BpPs+N%zS-L52?k~p|6SJ9zia)+<(>%TIY;P%l}{D*S|k8kunh#{}b`3U&_$-~i4!LT;el0M7h zfx$ug4xTS5CD09d{PgHTp{LG_Efo5}+2I93;rQt+eEp-($@wC~)J4{o{X=PR{lXHk zV-uteWsrktR$%+k5?-F;IWv^5L*#}07?fdVO%tx$+*rlTFdZXsV1=BYzYJApXzduT zs&qcDLFv^(0WgVU;Z0o0Av}eDCvSRkJmM@^JF>JudIVkH>fK4~u+!a91uLaJW1=ZEkDpHUm~D=*BT9;s z|aQifbLQ)CxQLa zk*D?aD=+3j$>p|%z`nU$#k~yqW6wop75}Sk9jF)hv7rFQ}I5DB8-x|a;R)l8BoW#URJHP>Tl)8a#x|zl6 zxV>hJ8nc)!22B>7hikVf!qm7QGGnq!T%!Ci{&1P`$2Pa@cFtE}?vJ!T+V^|k=Xu`S z`A&a4BK&YrIHzNz!o&3$P=j-`RHv-D$#T-9H!_RPZ z*qWb+Wi5so#fkx8;x9pdZaMh!MtP6}UHMf47FijNayU&MVcp=sbisW%S>S~3(&wOf z$vt?z$Vpc&Rar?f+DApjh|^|kswoy>Pu_mPB`I{q;X_zbjM#LU1Y@O=5z`f!r=i`Y z4uqM_(@&Q*2w08zH&&D&Zgb7E;;&dTTBJ86naRc4SCrqe%VVf)QZ>YE+OOGIB{AQ3 zIa^H^O}CEdVm!p(ZJ#{#C?2SR{E&AjP>K;7+Sxs7Qrtl1E$tDWXqz{?N**xx#n^z z8WY}OhX;f2!nZXq!s+@~8u6|6GIygt5)Kl7AkYyEhe^1lJ4lL)!X+f! z=5K8cc970ye>?kP(dJNVz=)-qb4`lJqnDaP{%}`V&b2IP3$}$iy5xjF@Kt{V5|f{W zn`!BZn-;j2X_~5n*w+Kg2kr1?y@XuGt8tj16gol+d5jZZ5yH|8jhNwe6Q8!4Fw{tLDJG5?(B#(cD97ty+&r@si(^1YYQyrN)_B*5~0DfHrd*95Lh4;|=F zfZ9&mywvlDT^Mw~mFh?CE@0Qm$-(S-IrOLF_e^nOxjw!1aTLXYH_j|kGd}$!PGJ)=D#<^0L%>9Zg7Iu)QK>`4m?%#?rbF9M7CRdM0n%Y~C=>RN zr~|{90#W`KV!#iEUqEiSGn@hLAq{R1CxAFog+v+|`3ngWyR!<$6(qyUQ9DoMAGSeX zG!OnBdj>|MixMTWi?GjJpit$H-07>1S-xOXbqhPgF)tymIgK;p$zT~@Xqk<$Ym?;~ zh$chy^OPhprYw876T1jK|Ha$!%nEj2xQ;}qy?AiGO+0+X4vvYf@xZ>Hs767sUs?rF zoJAv-vawlpif)TOj+T=i^iQp(e_qYT8D4(}QA8qXm6}p1%S09>&ttp^R(+lSFGWm$p#T5? diff --git a/lab2CA.sim/sim_1/behav/xsim/CPU9bits.tcl b/lab2CA.sim/sim_1/behav/xsim/CPU9bits.tcl new file mode 100644 index 0000000..8243a08 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/CPU9bits.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 100000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/CPU9bits_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/CPU9bits_vlog.prj new file mode 100644 index 0000000..34fbace --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/CPU9bits_vlog.prj @@ -0,0 +1,16 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/ALU.v" \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ +"../../../../lab2CA.srcs/sources_1/new/ControlUnit.v" \ +"../../../../lab2CA.srcs/sources_1/new/FetchUnit.v" \ +"../../../../lab2CA.srcs/sources_1/new/RegFile.v" \ +"../../../../lab2CA.srcs/sources_1/new/dataMemory.v" \ +"../../../../lab2CA.srcs/sources_1/new/instructionMemory.v" \ +"../../../../lab2CA.srcs/sources_1/new/CPU9bits.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou index b4e6d63..d1b0d25 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou @@ -2,10 +2,10 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Fri Mar 29 15:28:37 2019 -# Process ID: 28052 +# Start of session at: Sat Apr 6 13:17:03 2019 +# Process ID: 10700 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11344.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_11344.backup.jou deleted file mode 100644 index 1dd23b5..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_11344.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 17:25:06 2019 -# Process ID: 11344 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11564.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_11564.backup.jou new file mode 100644 index 0000000..71a23ce --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_11564.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Apr 6 13:16:30 2019 +# Process ID: 11564 +# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/REPOSITORIES/Educational/Western -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou deleted file mode 100644 index 1b4851e..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 17:34:31 2019 -# Process ID: 12056 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_28052.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_28052.backup.jou new file mode 100644 index 0000000..b4e6d63 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_28052.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Fri Mar 29 15:28:37 2019 +# Process ID: 28052 +# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/REPOSITORIES/Educational/Western -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index a4feb667b8049fdf96af39c9c779cfe113421ed1..029ca563f54065ea55bee30c779f3173eaad5fc0 100644 GIT binary patch literal 4262 zcmcgw+m75c815d_3JX;$6|}Ill7TL*U?-E)%p`k7chpKqErRWCg}8~F#FH2tJJ`<5 z>|5{(yaX@BOAybAY?c9!BK2y<&gA?4??2i900!=#N_Z;4(c#H~@7P~|AW2bCq_}XO zf}?k2ic${WZuTCec!Dab&evbu6L87AO5~~?`R+V z1`ZZAD{P^O#P+u{!&^$CahnvnLuTU)BcRG zp>Og298(lqc#dIjrZ}|GAh10=Ns;gS_8^YkAdV-#7bDljfgQkJkFZ44A1RKj462)w zB#72)Q3K8E&q6^L_Fls|q0!3Gl*D?cVx$g?jHbALf3Yl3BKUeOaZ(9P%EilNQA0_F zN||#7$3I+$F;Oy#agL@fXlwnny`RyzHjMHNYK>eVg)P0h>*i&UeLrma`wARi%i7ts zuc4%9ilNE{M(HxoywRxX`H#V#yA?O|nz$F>@mqz2($G>NMUstugtJ8wd%oKMUs*Q@ znkZxNWXy|_VujOfFmBMSg(Zv^4x2DPG@xyRtZDdpC< z4DBXQ2_9+7b&+PU;Aus19r{I2u?J1m0r>oOa$AH+C8|W*_68SR+<dd>D&3V$sXF*iN6IyiRBoDnJ@9EO{a#^}*OxC-;toxPVksk)BWB7Kn~Hn} z9<@YXy!_FWr9%zqhU^T@J8}m>FJ51p3i`#=ZGG@r%WY%Ml;Cui&d*KRe9)duB*|EW z=L*;L?d@=c{%T5TgU2m_HH#DNc#d{Rko8Pv8oI<(*>mtwOPLf6_d>rpPCNwQB}?n6CE+4H+WQ-ECII;W delta 193 zcmZ3cc#?g>3&yV#Un;R2VB%UmnV<2BVM=02qHk($eou5Cs5AP(w-p diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/Compile_Options.txt new file mode 100644 index 0000000..e653d16 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "CPU9bits_behav" "xil_defaultlib.CPU9bits" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/obj/xsim_1.c new file mode 100644 index 0000000..90eeca3 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/obj/xsim_1.c @@ -0,0 +1,169 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_173(char*, char *); +extern void execute_388(char*, char *); +extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_390(char*, char *); +extern void execute_391(char*, char *); +extern void execute_393(char*, char *); +extern void execute_394(char*, char *); +extern void execute_395(char*, char *); +extern void execute_396(char*, char *); +extern void execute_397(char*, char *); +extern void execute_398(char*, char *); +extern void execute_399(char*, char *); +extern void execute_400(char*, char *); +extern void execute_401(char*, char *); +extern void execute_402(char*, char *); +extern void execute_403(char*, char *); +extern void execute_404(char*, char *); +extern void execute_405(char*, char *); +extern void execute_406(char*, char *); +extern void execute_407(char*, char *); +extern void execute_408(char*, char *); +extern void execute_409(char*, char *); +extern void execute_410(char*, char *); +extern void execute_411(char*, char *); +extern void execute_412(char*, char *); +extern void execute_3(char*, char *); +extern void execute_4(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_178(char*, char *); +extern void execute_179(char*, char *); +extern void execute_180(char*, char *); +extern void execute_181(char*, char *); +extern void execute_182(char*, char *); +extern void execute_183(char*, char *); +extern void execute_184(char*, char *); +extern void execute_10(char*, char *); +extern void execute_12(char*, char *); +extern void execute_20(char*, char *); +extern void execute_211(char*, char *); +extern void execute_213(char*, char *); +extern void execute_214(char*, char *); +extern void execute_192(char*, char *); +extern void execute_193(char*, char *); +extern void execute_52(char*, char *); +extern void execute_323(char*, char *); +extern void execute_324(char*, char *); +extern void execute_325(char*, char *); +extern void execute_326(char*, char *); +extern void execute_327(char*, char *); +extern void execute_328(char*, char *); +extern void execute_252(char*, char *); +extern void execute_233(char*, char *); +extern void execute_273(char*, char *); +extern void execute_274(char*, char *); +extern void execute_275(char*, char *); +extern void execute_276(char*, char *); +extern void execute_277(char*, char *); +extern void execute_278(char*, char *); +extern void execute_320(char*, char *); +extern void execute_321(char*, char *); +extern void execute_120(char*, char *); +extern void execute_122(char*, char *); +extern void execute_368(char*, char *); +extern void execute_153(char*, char *); +extern void execute_175(char*, char *); +extern void execute_176(char*, char *); +extern void execute_177(char*, char *); +extern void execute_413(char*, char *); +extern void execute_414(char*, char *); +extern void execute_415(char*, char *); +extern void execute_416(char*, char *); +extern void execute_417(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +extern void transaction_59(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[75] = {(funcp)execute_173, (funcp)execute_388, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_390, (funcp)execute_391, (funcp)execute_393, (funcp)execute_394, (funcp)execute_395, (funcp)execute_396, (funcp)execute_397, (funcp)execute_398, (funcp)execute_399, (funcp)execute_400, (funcp)execute_401, (funcp)execute_402, (funcp)execute_403, (funcp)execute_404, (funcp)execute_405, (funcp)execute_406, (funcp)execute_407, (funcp)execute_408, (funcp)execute_409, (funcp)execute_410, (funcp)execute_411, (funcp)execute_412, (funcp)execute_3, (funcp)execute_4, (funcp)execute_6, (funcp)execute_7, (funcp)execute_178, (funcp)execute_179, (funcp)execute_180, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)execute_184, (funcp)execute_10, (funcp)execute_12, (funcp)execute_20, (funcp)execute_211, (funcp)execute_213, (funcp)execute_214, (funcp)execute_192, (funcp)execute_193, (funcp)execute_52, (funcp)execute_323, (funcp)execute_324, (funcp)execute_325, (funcp)execute_326, (funcp)execute_327, (funcp)execute_328, (funcp)execute_252, (funcp)execute_233, (funcp)execute_273, (funcp)execute_274, (funcp)execute_275, (funcp)execute_276, (funcp)execute_277, (funcp)execute_278, (funcp)execute_320, (funcp)execute_321, (funcp)execute_120, (funcp)execute_122, (funcp)execute_368, (funcp)execute_153, (funcp)execute_175, (funcp)execute_176, (funcp)execute_177, (funcp)execute_413, (funcp)execute_414, (funcp)execute_415, (funcp)execute_416, (funcp)execute_417, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_59}; +const int NumRelocateId= 75; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/CPU9bits_behav/xsim.reloc", (void **)funcTab, 75); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/CPU9bits_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/CPU9bits_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/CPU9bits_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/CPU9bits_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/CPU9bits_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..7c2a370 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Apr 6 14:02:33 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "f67bb5263bf851bf9c1beaa84fe1017c" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "21" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2395 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "100 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.11_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "5928_KB" -context "xsim\\usage" +webtalk_transmit -clientid 4022637463 -regid "" -xml C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


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zMm2a{2MMbKD^gsAv4jq$Ux%Lq$H~q=0VIzbI-rv4Mw4mNT6WsV#eQ<8OQXZ#kw(ex z?vcQ{|a}b0+)2ADwX) znAf-wS-m3=?DQ9#PQP);}#T7Js*C@q33n z>(6G6sHT&wnacT|+KlsJi3H4P-1uS%9c=b5n`VD<$jkni&4to33-ecY3!YQ>g*rmE zuHXW*9#?3t2m)RKUu~{{w+?yImlM5mWjcT7?B~;YhXTxQWDVGs2X=W2AypB%Q|5(J HMnleTfK8{2 literal 16 Xcmd<$ Date: Sat, 6 Apr 2019 14:17:10 -0400 Subject: [PATCH 03/17] Added back enable signals --- lab2CA.srcs/sources_1/new/CPU9bits.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v index e933368..5588f78 100644 --- a/lab2CA.srcs/sources_1/new/CPU9bits.v +++ b/lab2CA.srcs/sources_1/new/CPU9bits.v @@ -28,6 +28,7 @@ module CPU9bits( RegFile RF( .clk(clk), .reset(reset), + .enable(RegEn), .write_index(instr[4:3]), .op0_idx(instr[4:3]), .op1_idx(instr[2:1]), @@ -39,6 +40,7 @@ module CPU9bits( RegFile Bank( .clk(clk), .reset(reset), + .enable(bankS[1]), .write_index(instr[2:1]), .op0_idx(instr[2:1]), .op1_idx(2'b00),//Doesn't matter From 7c3f8c6da9df9c0b5dd23684a950b274bbf651e3 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Sat, 6 Apr 2019 14:17:47 -0400 Subject: [PATCH 04/17] Condensed a little bit. Maybe we can get the first instruction to work --- lab2CA.srcs/sources_1/new/CPU9bits.v | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v index 5588f78..abaab48 100644 --- a/lab2CA.srcs/sources_1/new/CPU9bits.v +++ b/lab2CA.srcs/sources_1/new/CPU9bits.v @@ -215,13 +215,10 @@ module CPU9bits_tb(); initial begin clk = 1'b0; - #5 reset = 1'b1; - #10 + #5 reset = 1'b0; #50000 - - // instruction = 9'b000100000; // reset = 1'b1; From 3129880d509a3bd6ace41c370608618200adc6b2 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Sat, 6 Apr 2019 14:18:18 -0400 Subject: [PATCH 05/17] Enabled test data for Program 1 --- lab2CA.srcs/sources_1/new/dataMemory.v | 204 ++++++++++++------------- 1 file changed, 102 insertions(+), 102 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/dataMemory.v b/lab2CA.srcs/sources_1/new/dataMemory.v index d2ff236..7ce5443 100644 --- a/lab2CA.srcs/sources_1/new/dataMemory.v +++ b/lab2CA.srcs/sources_1/new/dataMemory.v @@ -6,7 +6,7 @@ module dataMemory( output reg [8:0] readData ); - reg [8:0] memory [512:0]; // Maximum of 512 memory locations + reg [8:0] memory [100:0]; // Maximum of 512 memory locations // Vivado will give warnings of unconnected ports on the "address" bus if they are unused initial begin @@ -97,107 +97,107 @@ module dataMemory( // Program 1 Test Data -// memory[0] <= 9'd100; -// memory[1] <= 9'd58; -// memory[2] <= 9'd6; -// memory[3] <= 9'd12; -// memory[4] <= 9'b110110000; // -80 -// memory[5] <= 9'd17; -// memory[6] <= 9'b111011011; // -37 -// memory[7] <= 9'd25; -// memory[8] <= -9'd83; // -83 -// memory[9] <= -9'd98; // -98 -// memory[10] <= -9'd98; // -98 -// memory[11] <= -9'd74; // -74 -// memory[12] <= 9'd70; -// memory[13] <= -9'd38; // -38 -// memory[14] <= 9'd52; -// memory[15] <= -9'd96; // -96 -// memory[16] <= -9'd32; // -32 -// memory[17] <= -9'd93; // -93 -// memory[18] <= -9'd40; // -40 -// memory[19] <= 9'd59; -// memory[20] <= 9'd10; -// memory[21] <= 9'd81; -// memory[22] <= -9'd23; // -28 -// memory[23] <=- 9'd99; // -99 -// memory[24] <= -9'd41; // -41 -// memory[25] <= 9'd33; -// memory[26] <= 9'd98; -// memory[27] <= 9'd73; -// memory[28] <= -9'd1; // -1 -// memory[29] <= 9'd28; -// memory[30] <= 9'd5; -// memory[31] <= -9'd74; // -74 -// memory[32] <= -9'd41; // -41 -// memory[33] <= 9'd41; -// memory[34] <= 9'd39; -// memory[35] <= 9'd62; -// memory[36] <= 9'd19; -// memory[37] <= -9'd40; // -40 -// memory[38] <= -9'd8; // -8 -// memory[39] <= 9'd92; -// memory[40] <= 9'd37; -// memory[41] <= 9'd50; -// memory[42] <= -9'd72; // -72 -// memory[43] <= -9'd5; // -5 -// memory[44] <= 9'd19; -// memory[45] <= 9'd58; -// memory[46] <= -9'd13; // -13 -// memory[47] <= 9'd0; -// memory[48] <= -9'd97; // -97 -// memory[49] <= 9'd54; -// memory[50] <= -9'd17; // -17 -// memory[51] <= -9'd83; // -83 -// memory[52] <= 9'd53; -// memory[53] <= 9'd82; -// memory[54] <= -9'd94; // -94 -// memory[55] <= -9'd77; // -77 -// memory[56] <= -9'd74; // -74 -// memory[57] <= -9'd52; // -52 -// memory[58] <= 9'd85; -// memory[59] <= -9'd65; // -65 -// memory[60] <= -9'd10; // -10 -// memory[61] <= -9'd45; // -45 -// memory[62] <= -9'd92; // -92 -// memory[63] <= -9'd30; // -30 -// memory[64] <= 9'd18; -// memory[65] <= -9'd95; // -95 -// memory[66] <= -9'd27; // -27 -// memory[67] <= -9'd74; // -74 -// memory[68] <= 9'd62; -// memory[69] <= 9'd64; -// memory[70] <= -9'd9; // -9 -// memory[71] <= 9'd66; -// memory[72] <= -9'd71; // -71 -// memory[73] <= -9'd31; // -31 -// memory[74] <= 9'd34; -// memory[75] <= 9'd12; -// memory[76] <= 9'd3; -// memory[77] <= 9'd82; -// memory[78] <= 9'd13; -// memory[79] <= -9'd78; // -78 -// memory[80] <= -9'd8; // -8 -// memory[81] <= 9'd88; -// memory[82] <= 9'd42; -// memory[83] <= 9'd42; -// memory[84] <= 9'd21; -// memory[85] <= -9'd44; // -44 -// memory[86] <= 9'd30; -// memory[87] <= -9'd93; // -93 -// memory[88] <= 9'd2; -// memory[89] <= -9'd34; // -34 -// memory[90] <= 9'd92; -// memory[91] <= -9'd45; // -45 -// memory[92] <= 9'd26; -// memory[93] <= -9'd79; // -79 -// memory[94] <= 9'd43; -// memory[95] <= -9'd25; // -25 -// memory[96] <= -9'd24; // -24 -// memory[97] <= -9'd25; // -25 -// memory[98] <= -9'd19; // -19 -// memory[99] <= -9'd49; // -49 -// memory[100] <= -9'd8; // -8 + memory[0] <= 9'd100; + memory[1] <= 9'd58; + memory[2] <= 9'd6; + memory[3] <= 9'd12; + memory[4] <= 9'b110110000; // -80 + memory[5] <= 9'd17; + memory[6] <= 9'b111011011; // -37 + memory[7] <= 9'd25; + memory[8] <= -9'd83; // -83 + memory[9] <= -9'd98; // -98 + memory[10] <= -9'd98; // -98 + memory[11] <= -9'd74; // -74 + memory[12] <= 9'd70; + memory[13] <= -9'd38; // -38 + memory[14] <= 9'd52; + memory[15] <= -9'd96; // -96 + memory[16] <= -9'd32; // -32 + memory[17] <= -9'd93; // -93 + memory[18] <= -9'd40; // -40 + memory[19] <= 9'd59; + memory[20] <= 9'd10; + memory[21] <= 9'd81; + memory[22] <= -9'd23; // -28 + memory[23] <=- 9'd99; // -99 + memory[24] <= -9'd41; // -41 + memory[25] <= 9'd33; + memory[26] <= 9'd98; + memory[27] <= 9'd73; + memory[28] <= -9'd1; // -1 + memory[29] <= 9'd28; + memory[30] <= 9'd5; + memory[31] <= -9'd74; // -74 + memory[32] <= -9'd41; // -41 + memory[33] <= 9'd41; + memory[34] <= 9'd39; + memory[35] <= 9'd62; + memory[36] <= 9'd19; + memory[37] <= -9'd40; // -40 + memory[38] <= -9'd8; // -8 + memory[39] <= 9'd92; + memory[40] <= 9'd37; + memory[41] <= 9'd50; + memory[42] <= -9'd72; // -72 + memory[43] <= -9'd5; // -5 + memory[44] <= 9'd19; + memory[45] <= 9'd58; + memory[46] <= -9'd13; // -13 + memory[47] <= 9'd0; + memory[48] <= -9'd97; // -97 + memory[49] <= 9'd54; + memory[50] <= -9'd17; // -17 + memory[51] <= -9'd83; // -83 + memory[52] <= 9'd53; + memory[53] <= 9'd82; + memory[54] <= -9'd94; // -94 + memory[55] <= -9'd77; // -77 + memory[56] <= -9'd74; // -74 + memory[57] <= -9'd52; // -52 + memory[58] <= 9'd85; + memory[59] <= -9'd65; // -65 + memory[60] <= -9'd10; // -10 + memory[61] <= -9'd45; // -45 + memory[62] <= -9'd92; // -92 + memory[63] <= -9'd30; // -30 + memory[64] <= 9'd18; + memory[65] <= -9'd95; // -95 + memory[66] <= -9'd27; // -27 + memory[67] <= -9'd74; // -74 + memory[68] <= 9'd62; + memory[69] <= 9'd64; + memory[70] <= -9'd9; // -9 + memory[71] <= 9'd66; + memory[72] <= -9'd71; // -71 + memory[73] <= -9'd31; // -31 + memory[74] <= 9'd34; + memory[75] <= 9'd12; + memory[76] <= 9'd3; + memory[77] <= 9'd82; + memory[78] <= 9'd13; + memory[79] <= -9'd78; // -78 + memory[80] <= -9'd8; // -8 + memory[81] <= 9'd88; + memory[82] <= 9'd42; + memory[83] <= 9'd42; + memory[84] <= 9'd21; + memory[85] <= -9'd44; // -44 + memory[86] <= 9'd30; + memory[87] <= -9'd93; // -93 + memory[88] <= 9'd2; + memory[89] <= -9'd34; // -34 + memory[90] <= 9'd92; + memory[91] <= -9'd45; // -45 + memory[92] <= 9'd26; + memory[93] <= -9'd79; // -79 + memory[94] <= 9'd43; + memory[95] <= -9'd25; // -25 + memory[96] <= -9'd24; // -24 + memory[97] <= -9'd25; // -25 + memory[98] <= -9'd19; // -19 + memory[99] <= -9'd49; // -49 + memory[100] <= -9'd8; // -8 From 31f0d8a9fc1aaea541ca131ec71ed14d5071c1d4 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Sat, 6 Apr 2019 14:18:43 -0400 Subject: [PATCH 06/17] Enabled Bubble Sort for testing --- lab2CA.srcs/sources_1/new/instructionMemory.v | 143 +++++++++--------- 1 file changed, 72 insertions(+), 71 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/instructionMemory.v b/lab2CA.srcs/sources_1/new/instructionMemory.v index d4af570..2675e30 100644 --- a/lab2CA.srcs/sources_1/new/instructionMemory.v +++ b/lab2CA.srcs/sources_1/new/instructionMemory.v @@ -5,16 +5,17 @@ module instructionMemory( output reg [8:0] readData ); - reg [8:0] memory [512:0]; + reg [8:0] memory [100:0]; // Maximum of 512 memory locations + // Vivado will give warnings of unconnected ports on the "address" bus if they are unused initial begin - //Equation Solver - memory[0] <= 9'b000000000; - memory[1] <= 9'b000100000; //load - memory[2] <= 9'b000101000; //load - memory[3] <= 9'b010100010; //add - memory[4] <= 9'b111100000; //shift left - memory[5] <= 9'b111100000; //shift left +// //Equation Solver +// memory[0] <= 9'b000000000; +// memory[1] <= 9'b000100000; //load +// memory[2] <= 9'b000101000; //load +// memory[3] <= 9'b010100010; //add +// memory[4] <= 9'b111100000; //shift left +// memory[5] <= 9'b111100000; //shift left // //Testing all instructions // memory[6] <= 9'b010100011; //sub @@ -75,69 +76,69 @@ module instructionMemory( // memory[39] <= 9'b000000000; -// Bubble Sort -// memory[0] <= 9'b000000001; // nop -// // Setup -// memory[1] <= 9'b010000000; // zero $a -// memory[2] <= 9'b000100000; // lb $a, $a -// memory[3] <= 9'b010001000; // zero $b -// memory[4] <= 9'b010010000; // zero $c -// memory[5] <= 9'b010011000; // zero $d -// memory[6] <= 9'b101001000; // banks $b, $0 -// memory[7] <= 9'b101001010; // banks $b, $1 -// memory[8] <= 9'b100100011; // jf EndChk -// // Increment current index to compare next pair of values -// // Inc: -// memory[9] <= 9'b101001001; // bankl $b, $0 -// memory[10] <= 9'b011001001; // addi $b, 1 -// memory[11] <= 9'b101001000; // banks $b, $0 -// // Check if at the end of the array -// // EndChk: -// memory[12] <= 9'b101001001; // bankl $b, $0 -// memory[13] <= 9'b011101000; // slt $b, $a -// memory[14] <= 9'b110001001; // beq $b, JSC -// memory[15] <= 9'b100100001; // jf LoadNext -// // JSC: -// memory[16] <= 9'b100110100; // jf SwapChk -// // Load next values for comparison -// // LoadNext: -// memory[17] <= 9'b101001001; // bankl $b, $0 -// memory[18] <= 9'b011001001; // addi $b, 1 -// memory[19] <= 9'b000110010; // lb $c, $b -// memory[20] <= 9'b011001001; // addi $b, 1 -// memory[21] <= 9'b000111010; // lb $d, $b -// // Compare loaded values to see if they need to be swapped -// memory[22] <= 9'b101011110; // banks $d, $3 -// memory[23] <= 9'b011111100; // slt $d, $c -// memory[24] <= 9'b110011001; // beq $d, JI -// memory[25] <= 9'b100100001; // jf Swap -// // JI: -// memory[26] <= 9'b101110010; // jb Inc -// // Swap values in array -// // Swap: -// memory[27] <= 9'b101001001; // bankl $b, $0 -// memory[28] <= 9'b011001001; // addi $b, 1 -// memory[29] <= 9'b101011111; // bankl $d, $3 -// memory[30] <= 9'b001011010; // sb $d, $b -// memory[31] <= 9'b011001001; // addi $b, 1 -// memory[32] <= 9'b001010010; // sb $c, $b -// memory[33] <= 9'b010001000; // zero $b -// memory[34] <= 9'b011001001; // addi $b, 1 -// memory[35] <= 9'b101001010; // banks $b, $1 -// memory[36] <= 9'b101111100; // jb Inc -// // Check to see if any swaps have been made in the last iteration -// // SwapChk: -// memory[37] <= 9'b101001011; // bankl $b, $1 -// memory[38] <= 9'b110001001; // beq $b, JE -// memory[39] <= 9'b100100001; // jf Reset -// // JE: -// memory[40] <= 9'b100100011; // jf End -// // Reset: -// memory[41] <= 9'b010001000; // zero $b -// memory[42] <= 9'b101001000; // banks $b, $0 -// memory[43] <= 9'b101111011; // jb LoadNext -// // End: -// memory[44] <= 9'b000000000; // halt + //Bubble Sort + memory[0] <= 9'b000000001; // nop + // Setup + memory[1] <= 9'b010000000; // zero $a + memory[2] <= 9'b000100000; // lb $a, $a + memory[3] <= 9'b010001000; // zero $b + memory[4] <= 9'b010010000; // zero $c + memory[5] <= 9'b010011000; // zero $d + memory[6] <= 9'b101001000; // banks $b, $0 + memory[7] <= 9'b101001010; // banks $b, $1 + memory[8] <= 9'b100100011; // jf EndChk + // Increment current index to compare next pair of values + // Inc: + memory[9] <= 9'b101001001; // bankl $b, $0 + memory[10] <= 9'b011001001; // addi $b, 1 + memory[11] <= 9'b101001000; // banks $b, $0 + // Check if at the end of the array + // EndChk: + memory[12] <= 9'b101001001; // bankl $b, $0 + memory[13] <= 9'b011101000; // slt $b, $a + memory[14] <= 9'b110001001; // beq $b, JSC + memory[15] <= 9'b100100001; // jf LoadNext + // JSC: + memory[16] <= 9'b100110100; // jf SwapChk + // Load next values for comparison + // LoadNext: + memory[17] <= 9'b101001001; // bankl $b, $0 + memory[18] <= 9'b011001001; // addi $b, 1 + memory[19] <= 9'b000110010; // lb $c, $b + memory[20] <= 9'b011001001; // addi $b, 1 + memory[21] <= 9'b000111010; // lb $d, $b + // Compare loaded values to see if they need to be swapped + memory[22] <= 9'b101011110; // banks $d, $3 + memory[23] <= 9'b011111100; // slt $d, $c + memory[24] <= 9'b110011001; // beq $d, JI + memory[25] <= 9'b100100001; // jf Swap + // JI: + memory[26] <= 9'b101110010; // jb Inc + // Swap values in array + // Swap: + memory[27] <= 9'b101001001; // bankl $b, $0 + memory[28] <= 9'b011001001; // addi $b, 1 + memory[29] <= 9'b101011111; // bankl $d, $3 + memory[30] <= 9'b001011010; // sb $d, $b + memory[31] <= 9'b011001001; // addi $b, 1 + memory[32] <= 9'b001010010; // sb $c, $b + memory[33] <= 9'b010001000; // zero $b + memory[34] <= 9'b011001001; // addi $b, 1 + memory[35] <= 9'b101001010; // banks $b, $1 + memory[36] <= 9'b101111100; // jb Inc + // Check to see if any swaps have been made in the last iteration + // SwapChk: + memory[37] <= 9'b101001011; // bankl $b, $1 + memory[38] <= 9'b110001001; // beq $b, JE + memory[39] <= 9'b100100001; // jf Reset + // JE: + memory[40] <= 9'b100100011; // jf End + // Reset: + memory[41] <= 9'b010001000; // zero $b + memory[42] <= 9'b101001000; // banks $b, $0 + memory[43] <= 9'b101111011; // jb LoadNext + // End: + memory[44] <= 9'b000000000; // halt // Binary Search From 7715bb2a9cf629f2f91f23ca5b07830813ff566d Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Sat, 6 Apr 2019 14:19:10 -0400 Subject: [PATCH 07/17] Fixed simulation graphs --- CPU9bits_tb_behav.wcfg | 298 +++++++++++++++-------------------------- 1 file changed, 107 insertions(+), 191 deletions(-) diff --git a/CPU9bits_tb_behav.wcfg b/CPU9bits_tb_behav.wcfg index 40abd4d..fbb7e7a 100644 --- a/CPU9bits_tb_behav.wcfg +++ b/CPU9bits_tb_behav.wcfg @@ -3,249 +3,165 @@ - + - + - - - + + + - + - - - clk - clk - - + + reset reset - - done - done - - - instr[8:0] - instr[8:0] - BINARYRADIX - - - AddrOut[8:0] - AddrOut[8:0] - UNSIGNEDDECRADIX - - + Registers label - - - label + + reset + reset + + + op0_idx[1:0] + op0_idx[1:0] + + + op1_idx[1:0] + op1_idx[1:0] + + + write_data[8:0] + write_data[8:0] + + + op0[8:0] + op0[8:0] + + + op1[8:0] + op1[8:0] + + r0_out[8:0] r0_out[8:0] - RegisterA - UNSIGNEDDECRADIX - - label + r1_out[8:0] r1_out[8:0] - RegisterB - UNSIGNEDDECRADIX - - label + r2_out[8:0] r2_out[8:0] - RegisterC - UNSIGNEDDECRADIX - - label + r3_out[8:0] r3_out[8:0] - RegisterD - UNSIGNEDDECRADIX - + Banks label - - - label + + reset + reset + + + write_index[1:0] + write_index[1:0] + + + op0_idx[1:0] + op0_idx[1:0] + + + op1_idx[1:0] + op1_idx[1:0] + + + write_data[8:0] + write_data[8:0] + + + op0[8:0] + op0[8:0] + + + op1[8:0] + op1[8:0] + + + decOut[3:0] + decOut[3:0] + + r0_out[8:0] r0_out[8:0] - Bank0 - UNSIGNEDDECRADIX - - label + r1_out[8:0] r1_out[8:0] - Bank1 - UNSIGNEDDECRADIX - - label + r2_out[8:0] r2_out[8:0] - Bank2 - UNSIGNEDDECRADIX - - label + r3_out[8:0] r3_out[8:0] - Bank3 - UNSIGNEDDECRADIX Divider label - + + Instruction Memory label - memory[23:0][8:0] - memory[23:0][8:0] + + address[8:0] + address[8:0] + + + readData[8:0] + readData[8:0] + + + label + memory[100:0][8:0] + memory[100:0][8:0] + Instruction Memory + + + Data Memory - UNSIGNEDDECRADIX - - - [23][8:0] - [23][8:0] - UNSIGNEDDECRADIX + label + + address[8:0] + address[8:0] - - [22][8:0] - [22][8:0] - UNSIGNEDDECRADIX + + writeData[8:0] + writeData[8:0] - - [21][8:0] - [21][8:0] - UNSIGNEDDECRADIX + + readData[8:0] + readData[8:0] - - [20][8:0] - [20][8:0] - UNSIGNEDDECRADIX + + label + memory[100:0][8:0] + memory[100:0][8:0] + Data Memory - - [19][8:0] - [19][8:0] - UNSIGNEDDECRADIX - - - [18][8:0] - [18][8:0] - UNSIGNEDDECRADIX - - - [17][8:0] - [17][8:0] - UNSIGNEDDECRADIX - - - [16][8:0] - [16][8:0] - UNSIGNEDDECRADIX - - - [15][8:0] - [15][8:0] - UNSIGNEDDECRADIX - - - [14][8:0] - [14][8:0] - UNSIGNEDDECRADIX - - - [13][8:0] - [13][8:0] - UNSIGNEDDECRADIX - - - [12][8:0] - [12][8:0] - UNSIGNEDDECRADIX - - - [11][8:0] - [11][8:0] - UNSIGNEDDECRADIX - - - [10][8:0] - [10][8:0] - UNSIGNEDDECRADIX - - - [9][8:0] - [9][8:0] - UNSIGNEDDECRADIX - - - [8][8:0] - [8][8:0] - UNSIGNEDDECRADIX - - - [7][8:0] - [7][8:0] - UNSIGNEDDECRADIX - - - [6][8:0] - [6][8:0] - UNSIGNEDDECRADIX - - - [5][8:0] - [5][8:0] - UNSIGNEDDECRADIX - - - [4][8:0] - [4][8:0] - UNSIGNEDDECRADIX - - - [3][8:0] - [3][8:0] - UNSIGNEDDECRADIX - - - [2][8:0] - [2][8:0] - UNSIGNEDDECRADIX - - - [1][8:0] - [1][8:0] - UNSIGNEDDECRADIX - - - [0][8:0] - [0][8:0] - UNSIGNEDDECRADIX - - - - readData[8:0] - readData[8:0] - - - AddrIn[8:0] - AddrIn[8:0] From 2c2132fb9f3e5d778ece8c13c7f6e931ceacb22b Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Sat, 6 Apr 2019 14:19:20 -0400 Subject: [PATCH 08/17] Vivado metadata --- lab2CA.xpr | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/lab2CA.xpr b/lab2CA.xpr index 26918b7..e16ecfb 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -31,7 +31,7 @@
@@ -17,7 +17,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -27,17 +27,17 @@ This means code written to parse this file will need to be revisited each subseq - + - - + + - - - - + + + + @@ -46,11 +46,11 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -61,45 +61,45 @@ This means code written to parse this file will need to be revisited each subseq - + - - + + - + - + - - + + - + - + - + - + - + - + - + @@ -109,7 +109,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -119,8 +119,8 @@ This means code written to parse this file will need to be revisited each subseq - - + + @@ -128,26 +128,26 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + - + - + - + @@ -165,26 +165,26 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + - - - + + + - + @@ -192,7 +192,7 @@ This means code written to parse this file will need to be revisited each subseq - + diff --git a/lab2CA.runs/.jobs/vrs_config_63.xml b/lab2CA.runs/.jobs/vrs_config_63.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_63.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_64.xml b/lab2CA.runs/.jobs/vrs_config_64.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_64.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_65.xml b/lab2CA.runs/.jobs/vrs_config_65.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_65.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_66.xml b/lab2CA.runs/.jobs/vrs_config_66.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_66.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_67.xml 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--- a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt +++ b/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt @@ -1,13 +1,13 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------ +----------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Apr 6 14:01:18 2019 +| Date : Sat Apr 6 16:04:50 2019 | Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb -| Design : CPU9bits +| Command : report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb +| Design : CPU9bits_tb | Device : 7k160tifbg484-2L -| Design State : Synthesized ------------------------------------------------------------------------------------------------------------ +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------------- Utilization Design Information @@ -15,14 +15,15 @@ Table of Contents ----------------- 1. Slice Logic 1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists 1. Slice Logic -------------- @@ -30,16 +31,15 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 193 | 0 | 101400 | 0.19 | -| LUT as Logic | 193 | 0 | 101400 | 0.19 | +| Slice LUTs | 0 | 0 | 101400 | 0.00 | +| LUT as Logic | 0 | 0 | 101400 | 0.00 | | LUT as Memory | 0 | 0 | 35000 | 0.00 | -| Slice Registers | 81 | 0 | 202800 | 0.04 | -| Register as Flip Flop | 81 | 0 | 202800 | 0.04 | +| Slice Registers | 0 | 0 | 202800 | 0.00 | +| Register as Flip Flop | 0 | 0 | 202800 | 0.00 | | Register as Latch | 0 | 0 | 202800 | 0.00 | -| F7 Muxes | 11 | 0 | 50700 | 0.02 | +| F7 Muxes | 0 | 0 | 50700 | 0.00 | | F8 Muxes | 0 | 0 | 25350 | 0.00 | +-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. 1.1 Summary of Registers by Type @@ -57,25 +57,45 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 0 | Yes | Set | - | -| 81 | Yes | Reset | - | +| 0 | Yes | Reset | - | +-------+--------------+-------------+--------------+ -2. Memory +2. Slice Logic Distribution +--------------------------- + ++------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------------------------------------+------+-------+-----------+-------+ +| Slice | 0 | 0 | 25350 | 0.00 | +| SLICEL | 0 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 0 | 0 | 101400 | 0.00 | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 0 | 0 | 202800 | 0.00 | +| Register driven from within the Slice | 0 | | | | +| Register driven from outside the Slice | 0 | | | | +| Unique Control Sets | 0 | | 25350 | 0.00 | ++------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory --------- -+-------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 0.5 | 0 | 325 | 0.15 | -| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | -| RAMB18 | 1 | 0 | 650 | 0.15 | -| RAMB18E1 only | 1 | | | | -+-------------------+------+-------+-----------+-------+ ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 325 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | +| RAMB18 | 0 | 0 | 650 | 0.00 | ++----------------+------+-------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 -3. DSP +4. DSP ------ +-----------+------+-------+-----------+-------+ @@ -85,13 +105,13 @@ Table of Contents +-----------+------+-------+-----------+-------+ -4. IO and GT Specific +5. IO and GT Specific --------------------- +-----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 12 | 0 | 285 | 4.21 | +| Bonded IOB | 0 | 0 | 285 | 0.00 | | Bonded IPADs | 0 | 0 | 14 | 0.00 | | Bonded OPADs | 0 | 0 | 8 | 0.00 | | PHY_CONTROL | 0 | 0 | 8 | 0.00 | @@ -112,13 +132,13 @@ Table of Contents +-----------------------------+------+-------+-----------+-------+ -5. Clocking +6. Clocking ----------- +------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +------------+------+-------+-----------+-------+ -| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFGCTRL | 0 | 0 | 32 | 0.00 | | BUFIO | 0 | 0 | 32 | 0.00 | | MMCME2_ADV | 0 | 0 | 8 | 0.00 | | PLLE2_ADV | 0 | 0 | 8 | 0.00 | @@ -128,7 +148,7 @@ Table of Contents +------------+------+-------+-----------+-------+ -6. Specific Feature +7. Specific Feature ------------------- +-------------+------+-------+-----------+-------+ @@ -146,27 +166,15 @@ Table of Contents +-------------+------+-------+-----------+-------+ -7. Primitives +8. Primitives ------------- +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| LUT6 | 135 | LUT | -| FDRE | 81 | Flop & Latch | -| LUT5 | 33 | LUT | -| LUT4 | 23 | LUT | -| LUT3 | 21 | LUT | -| LUT2 | 13 | LUT | -| MUXF7 | 11 | MuxFx | -| OBUF | 10 | IO | -| IBUF | 2 | IO | -| RAMB18E1 | 1 | Block Memory | -| BUFG | 1 | Clock | -+----------+------+---------------------+ -8. Black Boxes +9. Black Boxes -------------- +----------+------+ @@ -174,8 +182,8 @@ Table of Contents +----------+------+ -9. Instantiated Netlists ------------------------- +10. Instantiated Netlists +------------------------- +----------+------+ | Ref Name | Used | diff --git a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb deleted file mode 100644 index 14cb01249cafaf1e704987a1ac4492f008326991..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 289 zcmd;LGcqu=&@-OItPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- zKX7#JL#_X;!c9CL3KaeD4#*DJ{Y1a~DFc5t{al>)KX z$}=!HIR2GqXy|i3s<3EJo5NXEps@X1HHL;o&QH~DcFNlI8i7>a1(ISeON~M7wH6Ev z4fcP5B!kmYO9loHhe=i(PN8n@&LKfQXYD{r=Gp@Z$EP5Y;jIgZ-0KP?99!K$>|SpW yc^61FI4t!6u|N4pxrao!8pS*N`}+F(=|DLij(&cwK5GL(O8x@L2K%EyAT|ILDNi8) diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml index 44d18d6..63302f3 100644 --- a/lab2CA.runs/synth_1/gen_run.xml +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -1,12 +1,14 @@ - - - - - - - - + + + + + + + + + + @@ -75,7 +77,7 @@ diff --git a/lab2CA.runs/synth_1/htr.txt b/lab2CA.runs/synth_1/htr.txt index 641d4cb..b59ff1f 100644 --- a/lab2CA.runs/synth_1/htr.txt +++ b/lab2CA.runs/synth_1/htr.txt @@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status. REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. REM -vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl +vivado -log CPU9bits_tb.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl diff --git a/lab2CA.runs/synth_1/vivado.jou b/lab2CA.runs/synth_1/vivado.jou index fe3cd53..4c29279 100644 --- a/lab2CA.runs/synth_1/vivado.jou +++ b/lab2CA.runs/synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Apr 6 14:00:40 2019 -# Process ID: 8416 +# Start of session at: Sat Apr 6 16:04:16 2019 +# Process ID: 22928 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1 -# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl -# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds +# Command line: vivado.exe -log CPU9bits_tb.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl +# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.vds # Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou #----------------------------------------------------------- -source CPU9bits.tcl -notrace +source CPU9bits_tb.tcl -notrace diff --git a/lab2CA.runs/synth_1/vivado.pb b/lab2CA.runs/synth_1/vivado.pb index 6d9392fc435c9a4484d553c31fb285463a73c913..f27f908804bf866d5afb540e33c1a414e725b48e 100644 GIT binary patch delta 2229 zcmb7GeQZ-z6z9HnUH2$s>k4dx(l=S@XxH*S`d-_y1%ZhhbF&*7KL}x6TSl>K$6hxX z6lIVQHA6QJMh%%t3^G3mV>h~K0&e2Rh7k}FKY|HhV$`5c{sH1Y`0guAP{v08>Am;- ze!qL}x#yhwe%!11?JsIMy_Ghsh&MF_VxbboD$`lod`cAT8EuiaKq#IFM)_5=B)7*B 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zbJx3FZgM9=E{?uA-m?#`A1|t&zP+{M&KA0TV?*Lrr4pP??Ti2J9#)&$ztS51XZEj& zt?B(M?c9T!-hX%RS~A{~m)gG4Q`6#pPuo{j?pggE#KPZq9z*`9`}epEuzybx)Vz3c z?A-rNvR1SCGZQr@AP&MobHSX+3KPA1K={r^Ox036los}t-_`L116+|;>cAt67!sm! z+>TZgtJRA?4hs4f-JOnC#($f2zdGnbtKWF-P3Aro(Gwb69xQ^(N3+#8ezfm_=)17F zNImxY_aBI^?Z=AL$v0kkAi8j#>gA)m3`OlTU-%XlORM9HAooN$J=r~S=P*5=;FV|< zLm}FL!*AElqorXME&4$w(bC(#o@&A44!yWU>L@ZBhSy{gn|gbaEe&GJh_R(H$rkPN zneEuqm}E=CWVYi-W0Eb}w`ImS)0kun`<%^@aXu~`;R4B0#7nL@WcKD3*;WQ#7I%i-wYZ@~TwV-ya68ev?Eb7*H zoPLvd*&5_=1zdhA3z!otEO!p4c)U?N0pfWrRj;7q!2Yy$9*wS9G$uJsKbB}$(nPv# zvuW|Gnhl#~bc-NAi-<(G7;KmDgi71=&#v)eR_rup$LJCyQb)#qhmPgu#!h2+jQT%? z#rlcbB_6sKv)Y};^ceMj3hPSRoqN7hj3+Vb{}h%MaCqq)nAL7F2MB2w75`8#N$7W3 zQcw?t>NzwkHkk|5LRTyPP1&{2i%sSPR@F&`U^ z35&%pR*hI@h6KO%fYx3H&Q+fyi%Lj}!!K(po_yNGd(2$2vf9r)RA6AAVfmz@o|quV zQAt>!r5=`uv^u6GD^_-B4!_xwxag0_0sPF1s(E)>^%`|ij;5M-tG7-~FxhUK#f4vA zzh^F0Po5cKFl($ngucSOL*yQDSY!R%eY|TTzLvRajwi{ zw>d0sc*0Wxos0=?o?FNOe17)$R|va6KOS1G7At-xEG}UevpHBZrmVurGmY@ibDhjp z=sdsKxPuMAuJXs>=K0brOTZtcRVGwTmXsgV5BjD`#$KNt8*v`)czn_VKbb6o V?@kut{ly%+*UEW0H>|wi{TITv{Ivi8 From b3e2adb0979cf48a2073e21cb04fdd501dfe370c Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Sat, 6 Apr 2019 16:05:47 -0400 Subject: [PATCH 10/17] Updated simulation --- lab2CA.sim/sim_1/behav/xsim/webtalk.jou | 6 +- ...60.backup.jou => webtalk_10700.backup.jou} | 6 +- ...52.backup.jou => webtalk_16352.backup.jou} | 4 +- lab2CA.sim/sim_1/behav/xsim/xelab.pb | Bin 4262 -> 965 bytes .../CPU9bits_behav/webtalk/xsim_webtalk.tcl | 10 ++-- .../xsim/xsim.dir/CPU9bits_behav/xsim.mem | Bin 20417 -> 20421 bytes .../xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c | 56 ++++++++++-------- .../webtalk/xsim_webtalk.tcl | 32 ++++++++++ .../xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem | Bin 19284 -> 20533 bytes lab2CA.sim/sim_1/behav/xsim/xvlog.pb | Bin 8973 -> 8997 bytes 10 files changed, 75 insertions(+), 39 deletions(-) rename lab2CA.sim/sim_1/behav/xsim/{webtalk_26660.backup.jou => webtalk_10700.backup.jou} (84%) rename lab2CA.sim/sim_1/behav/xsim/{webtalk_14652.backup.jou => webtalk_16352.backup.jou} (92%) create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou index d1b0d25..a067452 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou @@ -2,10 +2,10 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Apr 6 13:17:03 2019 -# Process ID: 10700 +# Start of session at: Sat Apr 6 14:31:56 2019 +# Process ID: 17712 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_26660.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_10700.backup.jou similarity index 84% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_26660.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_10700.backup.jou index 21e9e99..d1b0d25 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_26660.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_10700.backup.jou @@ -2,10 +2,10 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Fri Mar 29 15:21:59 2019 -# Process ID: 26660 +# Start of session at: Sat Apr 6 13:17:03 2019 +# Process ID: 10700 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_14652.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_16352.backup.jou similarity index 92% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_14652.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_16352.backup.jou index 5f01ab3..ebcc5c7 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_14652.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_16352.backup.jou @@ -2,8 +2,8 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Fri Mar 29 15:13:54 2019 -# Process ID: 14652 +# Start of session at: Sat Apr 6 14:28:59 2019 +# Process ID: 16352 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim # Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index 029ca563f54065ea55bee30c779f3173eaad5fc0..530bad80bfc752a2ac6f6d81ba23bec18c3ec400 100644 GIT binary patch delta 155 zcmZ3cc$9s@3&xKVUn;TeVd7donV<14Q%Ta~*Nk#3@g+$LlRxqcZZ$%}XsxEJ;mK$WO{rNXyJg zEmkPWS4b{O1qv!;rxxX<<_NG#F`HUiXmJ*2=9cCpmgE;jv6~p{niv}yXD}47R|5{(yaX@BOAybAY?c9!BK2y<&gA?4??2i900!=#N_Z;4(c#H~@7P~|AW2bCq_}XO zf}?k2ic${WZuTCec!Dab&evbu6L87AO5~~?`R+V z1`ZZAD{P^O#P+u{!&^$CahnvnLuTU)BcRG zp>Og298(lqc#dIjrZ}|GAh10=Ns;gS_8^YkAdV-#7bDljfgQkJkFZ44A1RKj462)w zB#72)Q3K8E&q6^L_Fls|q0!3Gl*D?cVx$g?jHbALf3Yl3BKUeOaZ(9P%EilNQA0_F zN||#7$3I+$F;Oy#agL@fXlwnny`RyzHjMHNYK>eVg)P0h>*i&UeLrma`wARi%i7ts zuc4%9ilNE{M(HxoywRxX`H#V#yA?O|nz$F>@mqz2($G>NMUstugtJ8wd%oKMUs*Q@ znkZxNWXy|_VujOfFmBMSg(Zv^4x2DPG@xyRtZDdpC< z4DBXQ2_9+7b&+PU;Aus19r{I2u?J1m0r>oOa$AH+C8|W*_68SR+<dd>D&3V$sXF*iN6IyiRBoDnJ@9EO{a#^}*OxC-;toxPVksk)BWB7Kn~Hn} z9<@YXy!_FWr9%zqhU^T@J8}m>FJ51p3i`#=ZGG@r%WY%Ml;Cui&d*KRe9)duB*|EW z=L*;L?d@=c{%T5TgU2m_HH#DNc#d{Rko8Pv8oI<(*>mtwOPLf6_d>rpPCNwQB}?n6CE+4H+WQ-ECII;W diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl index 7c2a370..2ce2e0e 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl @@ -1,6 +1,6 @@ webtalk_init -webtalk_dir C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Sat Apr 6 14:02:33 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Sat Apr 6 14:32:16 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" @@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "f67bb5263bf851bf9c1beaa84fe1017c" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "21" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "23" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz" -context "user_environment" @@ -26,7 +26,7 @@ webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" webtalk_add_data -client xsim -key runtime -value "100 us" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.11_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "5928_KB" -context "xsim\\usage" -webtalk_transmit -clientid 4022637463 -regid "" -xml C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key Simulation_Time -value "0.14_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "5932_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2508747890 -regid "" -xml C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/xsim.mem index 09eb4f0749af22b6f042a6f6cbfc6d7920c9bd06..7661257f8b806e5e6820e7208adee341c07a14ae 100644 GIT binary patch literal 20421 zcmeJEc|4Tu+Xs%{)g6`OF3FxsvK3LXj}}xEH$wIz2^l2DGE0(VuPDhfrDP|{Zf2qo zVi2Y*Gxot?VvI4X?{$st`}usH*YEZF{`39w$&1UJ*Lfc2vAmDvJUjgH$AAAb#%|^h z9QghG^mXI&f6w~APyeTZ|I@(#Y2g1f@c)$tGS}DF!S8?QZU5(&-_O4k|M)`?_+1?M zUipuC|7+U+>&Gv@E`IYJ5nRsE1fUb+`7_d zXSIdsXq+&v5ZV~<-PkJr(7VuhrI+o^InFz*x9NR;8)c-&)1V95cx7sE0t<12n@-N< z2V%UajCmMBx1OANgFKn}e)Xh-Dv3QGOyrjMFJSN%FO98&hu+?dz2deeMB=tMx^9yg4ddJ&g}vSBgW1b4L2lIIJLVUG)4c>(Ukt??dH~V8Kx7p zrU^`gtFCy=;vr9Sdb$7gp!fDCb4Pc$%j_x{PY^`Ee7203E@_AF{~J0vUK4bjns0S` zF;~0=Gmj4*KT-T9L0P3MnWEHGQwp1d5=U@c|6#c+C3y3@c2tP8r)*$_%a9V~(Q}6# zHjV>|J|70?7lTSmD71#PFW%R1PG7y4w7kg=R?`?O_^I}=0;^>Q0z`VOE>?8AD|Sbg9R&j^+zHR~X94&+UUw#Fomr)Q6c+lq1o)6-$k9gePH(E(8YJ09R85Ma*$(kt1F8wPi&*=t^wa2?kA!q)1>PiN*3i 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zRNM*@F!uhiniQjkvd&hElwPu6*6MG&kCt8@H z;s)IeoYXHA_!^m~#&JjW*M^_;G@9_6otyBL&0Yw$^>tW8^!Mp}l|zM}jO0ruxn^ zvo14_(C>bpWBn=bpIUu=V!pw9ml}Hc#S*NySMgRIxp>?rd_7NtD*=yP~cc%Q#DM z57nFsPrI{m^QSb_tjr=+yid2dCYzj)dnoV8Hu<>ELrXamyF5GetEO6wc%$`^{-eac zA1bb9!ihid!?jN0U)6&7haQyw$=|75R8`ex{9D3tzX~TsNhlee*k|r2e<$L diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c index 96ac0ee..d071773 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c @@ -45,18 +45,14 @@ typedef void (*funcp)(char *, char *); extern int main(int, char**); extern void execute_2(char*, char *); -extern void execute_3(char*, char *); extern void execute_176(char*, char *); -extern void execute_412(char*, char *); -extern void execute_413(char*, char *); -extern void execute_387(char*, char *); +extern void execute_416(char*, char *); +extern void execute_417(char*, char *); +extern void execute_175(char*, char *); +extern void execute_391(char*, char *); extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); -extern void execute_389(char*, char *); -extern void execute_390(char*, char *); -extern void execute_392(char*, char *); extern void execute_393(char*, char *); extern void execute_394(char*, char *); -extern void execute_395(char*, char *); extern void execute_396(char*, char *); extern void execute_397(char*, char *); extern void execute_398(char*, char *); @@ -73,10 +69,14 @@ extern void execute_408(char*, char *); extern void execute_409(char*, char *); extern void execute_410(char*, char *); extern void execute_411(char*, char *); +extern void execute_412(char*, char *); +extern void execute_413(char*, char *); +extern void execute_414(char*, char *); +extern void execute_415(char*, char *); +extern void execute_5(char*, char *); extern void execute_6(char*, char *); -extern void execute_7(char*, char *); +extern void execute_8(char*, char *); extern void execute_9(char*, char *); -extern void execute_10(char*, char *); extern void execute_181(char*, char *); extern void execute_182(char*, char *); extern void execute_183(char*, char *); @@ -84,17 +84,21 @@ extern void execute_184(char*, char *); extern void execute_185(char*, char *); extern void execute_186(char*, char *); extern void execute_187(char*, char *); -extern void execute_13(char*, char *); -extern void execute_15(char*, char *); -extern void execute_23(char*, char *); +extern void execute_12(char*, char *); +extern void execute_14(char*, char *); +extern void execute_22(char*, char *); extern void execute_214(char*, char *); extern void execute_216(char*, char *); extern void execute_217(char*, char *); extern void execute_195(char*, char *); extern void execute_196(char*, char *); -extern void execute_55(char*, char *); +extern void execute_54(char*, char *); extern void execute_326(char*, char *); extern void execute_327(char*, char *); +extern void execute_328(char*, char *); +extern void execute_329(char*, char *); +extern void execute_330(char*, char *); +extern void execute_331(char*, char *); extern void execute_255(char*, char *); extern void execute_236(char*, char *); extern void execute_276(char*, char *); @@ -105,26 +109,26 @@ extern void execute_280(char*, char *); extern void execute_281(char*, char *); extern void execute_323(char*, char *); extern void execute_324(char*, char *); -extern void execute_123(char*, char *); -extern void execute_125(char*, char *); -extern void execute_367(char*, char *); -extern void execute_156(char*, char *); +extern void execute_122(char*, char *); +extern void execute_124(char*, char *); +extern void execute_371(char*, char *); +extern void execute_155(char*, char *); extern void execute_178(char*, char *); extern void execute_179(char*, char *); extern void execute_180(char*, char *); -extern void execute_414(char*, char *); -extern void execute_415(char*, char *); -extern void execute_416(char*, char *); -extern void execute_417(char*, char *); extern void execute_418(char*, char *); +extern void execute_419(char*, char *); +extern void execute_420(char*, char *); +extern void execute_421(char*, char *); +extern void execute_422(char*, char *); extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); -extern void transaction_60(char*, char*, unsigned, unsigned, unsigned); -funcp funcTab[75] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_176, (funcp)execute_412, (funcp)execute_413, (funcp)execute_387, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_389, (funcp)execute_390, (funcp)execute_392, (funcp)execute_393, (funcp)execute_394, (funcp)execute_395, (funcp)execute_396, (funcp)execute_397, (funcp)execute_398, (funcp)execute_399, (funcp)execute_400, (funcp)execute_401, (funcp)execute_402, (funcp)execute_403, (funcp)execute_404, (funcp)execute_405, (funcp)execute_406, (funcp)execute_407, (funcp)execute_408, (funcp)execute_409, (funcp)execute_410, (funcp)execute_411, (funcp)execute_6, (funcp)execute_7, (funcp)execute_9, (funcp)execute_10, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)execute_184, (funcp)execute_185, (funcp)execute_186, (funcp)execute_187, (funcp)execute_13, (funcp)execute_15, (funcp)execute_23, (funcp)execute_214, (funcp)execute_216, (funcp)execute_217, (funcp)execute_195, (funcp)execute_196, (funcp)execute_55, (funcp)execute_326, (funcp)execute_327, (funcp)execute_255, (funcp)execute_236, (funcp)execute_276, (funcp)execute_277, (funcp)execute_278, (funcp)execute_279, (funcp)execute_280, (funcp)execute_281, (funcp)execute_323, (funcp)execute_324, (funcp)execute_123, (funcp)execute_125, (funcp)execute_367, (funcp)execute_156, (funcp)execute_178, (funcp)execute_179, (funcp)execute_180, (funcp)execute_414, (funcp)execute_415, (funcp)execute_416, (funcp)execute_417, (funcp)execute_418, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_60}; -const int NumRelocateId= 75; +extern void transaction_61(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[79] = {(funcp)execute_2, (funcp)execute_176, (funcp)execute_416, (funcp)execute_417, (funcp)execute_175, (funcp)execute_391, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_393, (funcp)execute_394, (funcp)execute_396, (funcp)execute_397, (funcp)execute_398, (funcp)execute_399, (funcp)execute_400, (funcp)execute_401, (funcp)execute_402, (funcp)execute_403, (funcp)execute_404, (funcp)execute_405, (funcp)execute_406, (funcp)execute_407, (funcp)execute_408, (funcp)execute_409, (funcp)execute_410, (funcp)execute_411, (funcp)execute_412, (funcp)execute_413, (funcp)execute_414, (funcp)execute_415, (funcp)execute_5, (funcp)execute_6, (funcp)execute_8, (funcp)execute_9, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)execute_184, (funcp)execute_185, (funcp)execute_186, (funcp)execute_187, (funcp)execute_12, (funcp)execute_14, (funcp)execute_22, (funcp)execute_214, (funcp)execute_216, (funcp)execute_217, (funcp)execute_195, (funcp)execute_196, (funcp)execute_54, (funcp)execute_326, (funcp)execute_327, (funcp)execute_328, (funcp)execute_329, (funcp)execute_330, (funcp)execute_331, (funcp)execute_255, (funcp)execute_236, (funcp)execute_276, (funcp)execute_277, (funcp)execute_278, (funcp)execute_279, (funcp)execute_280, (funcp)execute_281, (funcp)execute_323, (funcp)execute_324, (funcp)execute_122, (funcp)execute_124, (funcp)execute_371, (funcp)execute_155, (funcp)execute_178, (funcp)execute_179, (funcp)execute_180, (funcp)execute_418, (funcp)execute_419, (funcp)execute_420, (funcp)execute_421, (funcp)execute_422, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_61}; +const int NumRelocateId= 79; void relocate(char *dp) { - iki_relocate(dp, "xsim.dir/CPU9bits_tb_behav/xsim.reloc", (void **)funcTab, 75); + iki_relocate(dp, "xsim.dir/CPU9bits_tb_behav/xsim.reloc", (void **)funcTab, 79); /*Populate the transaction function pointer field in the whole net structure */ } diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..8e54f2a --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Apr 6 15:44:12 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "f67bb5263bf851bf9c1beaa84fe1017c" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "64" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2395 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "50005 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.08_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6332_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1176027589 -regid "" -xml C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


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z{p({ixy-pD@5AUUF-ZRL-S+&0Vp+*9wbT3{^o_O|18oVZv{fD=1QKcr_dFT;aWY$x zWcflNhMT_0WR~{sN*-358My0hoc1{wxZBas%*$);rH(Njp@#i1c5$u{V@JQTmCeg1 kQa=JZGRIzDvu<=`)gzT>kA#g!>IJ1Mg2OuMq;k{v4cbvSR{#J2 delta 327 zcmZ4L*6X%m2JhwoK0n^chuQTe&r&pETsrwCV+_kAMy|Ta@$#jdL8<9(nK`L?Ws@Ju z3s1hlWHH%_Q;!`gI(edi+T;K>J@z7qs>y Date: Sat, 6 Apr 2019 16:06:49 -0400 Subject: [PATCH 11/17] Indented better --- lab2CA.srcs/sources_1/new/ControlUnit.v | 306 ++++++++++++------------ 1 file changed, 154 insertions(+), 152 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v index 9a0c11e..a41e2ae 100644 --- a/lab2CA.srcs/sources_1/new/ControlUnit.v +++ b/lab2CA.srcs/sources_1/new/ControlUnit.v @@ -13,71 +13,72 @@ module ControlUnit( case(instIn) 4'b0000: // Halt/NOP begin - halt <= 1'b1; - RegEn <= 1'b1; - FU <= 3'b001; // Disable Branching - addi <= 1'b0; - dataMemEn <= 1'b0; // Disabled - aluOut <= 4'b0000; - mem <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + halt <= 1'b1; + RegEn <= 1'b1; + FU <= 3'b001; // Disable Branching + addi <= 1'b0; + dataMemEn <= 1'b0; // Disabled + aluOut <= 4'b0000; + mem <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b0001: // Load Byte begin - aluOut <= 4'b0000; - mem <= 1'b1; - dataMemEn <= 1'b0; // Disabled - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - addi <= 1'b0; - halt <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b1; + dataMemEn <= 1'b0; // Disabled + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + addi <= 1'b0; + halt <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b0010: // Store Byte begin - aluOut <= 4'b0000; - mem <= 1'b0; - dataMemEn <= 1'b1; // Enabled - RegEn <= 1'b1; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b0; + dataMemEn <= 1'b1; // Enabled + RegEn <= 1'b1; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b0011: // Link begin - halt <= 1'b0; - RegEn <= 1'b0; - FU <= 3'b001; - addi <= 1'b0; - aluOut <= 4'b0000; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b1; - bank <= 2'b10; - js <= 1'b0; + halt <= 1'b0; + RegEn <= 1'b0; + FU <= 3'b001; + addi <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b1; + bank <= 2'b10; + js <= 1'b0; end 4'b0100: // Zero begin - aluOut <= 4'b1011; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b1011; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b0101: // Add/Subtract - if(functBit == 1) begin // Subtract + if(functBit == 1) // Subtract + begin aluOut <= 4'b0001; RegEn <= 1'b0; FU <= 3'b001; @@ -88,8 +89,9 @@ module ControlUnit( link <= 1'b0; bank <= 2'b10; js <= 1'b0; - end - else begin // Add + end + else // Add + begin aluOut <= 4'b0000; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching @@ -100,114 +102,114 @@ module ControlUnit( link <= 1'b0; bank <= 2'b10; js <= 1'b0; - end + end 4'b0110: // Add Immediate begin - aluOut <= 4'b1010; - addi <= 1'b1; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b1010; + addi <= 1'b1; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b0111: // Set if Less Than begin - aluOut <= 4'b1001; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b1001; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b1000: // Jump to Register begin - aluOut <= 4'b0000; - FU <= 3'b000; - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b0000; + FU <= 3'b000; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b1001: // Jump Forward begin - aluOut <= 4'b0000; - FU <= 3'b010; - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b0000; + FU <= 3'b010; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b1010: // Bank Load/Bank Store begin - halt <= 1'b0; - RegEn <= !functBit; - FU <= 3'b001; // Disable Branching - addi <= 1'b0; - aluOut <= 4'b0000; - dataMemEn <= 1'b0; // Disabled - mem <= 1'b0; - link <= 1'b0; - bank <= {functBit,functBit}; - js <= 1'b0; + halt <= 1'b0; + RegEn <= !functBit; + FU <= 3'b001; // Disable Branching + addi <= 1'b0; + aluOut <= 4'b0000; + dataMemEn <= 1'b0; // Disabled + mem <= 1'b0; + link <= 1'b0; + bank <= {functBit,functBit}; + js <= 1'b0; end 4'b1011: // Jump Backward begin - aluOut <= 4'b0000; - FU <= 3'b010; - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b1; + aluOut <= 4'b0000; + FU <= 3'b010; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b1; end 4'b1100: // Branch if Zero begin - aluOut <= 4'b1010; - FU <= 3'b110; - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b1010; + FU <= 3'b110; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b1101: // NOR begin - aluOut <= 4'b0011; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + aluOut <= 4'b0011; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end 4'b1110: // OR/AND if(functBit == 1) // AND - begin + begin aluOut <= 4'b0100; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching @@ -218,9 +220,9 @@ module ControlUnit( link <= 1'b0; bank <= 2'b10; js <= 1'b0; - end + end else // OR - begin + begin aluOut <= 4'b0010; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching @@ -231,10 +233,10 @@ module ControlUnit( link <= 1'b0; bank <= 2'b10; js <= 1'b0; - end + end 4'b1111: // Shift Right Logical/Shift Left Logical if(functBit == 1) // Shift Right Logical - begin + begin aluOut <= 4'b0110; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching @@ -245,9 +247,9 @@ module ControlUnit( link <= 1'b0; bank <= 2'b10; js <= 1'b0; - end + end else // Shift Left Logical - begin + begin aluOut <= 4'b0101; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching @@ -258,19 +260,19 @@ module ControlUnit( link <= 1'b0; bank <= 2'b10; js <= 1'b0; - end + end default: begin - halt <= 1'b1; - RegEn <= 1'b1; - FU <= 3'b001; - dataMemEn <= 1'b0; // Disabled - addi <= 1'b0; - aluOut <= 4'b0000; - mem <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + halt <= 1'b1; + RegEn <= 1'b1; + FU <= 3'b001; + dataMemEn <= 1'b0; // Disabled + addi <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end endcase end From 3fb02d18e3f1862743e2295460daf5df2d4de94a Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Sat, 6 Apr 2019 16:07:32 -0400 Subject: [PATCH 12/17] Added result, found that waiting 50000 ns is not necessary, as there's a button for it --- lab2CA.srcs/sources_1/new/CPU9bits.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v index abaab48..4f301fd 100644 --- a/lab2CA.srcs/sources_1/new/CPU9bits.v +++ b/lab2CA.srcs/sources_1/new/CPU9bits.v @@ -203,6 +203,7 @@ endmodule module CPU9bits_tb(); reg clk, reset; + reg [8:0] result; wire done; always @@ -211,14 +212,14 @@ module CPU9bits_tb(); CPU9bits CPU9bits0( .reset(reset), .clk(clk), - .done(done)); + .done(done) + ); initial begin clk = 1'b0; reset = 1'b1; #5 reset = 1'b0; - #50000 // instruction = 9'b000100000; // reset = 1'b1; From dd7a319e928b7d006e026ed2c1463ad231e385d0 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Sat, 6 Apr 2019 16:08:02 -0400 Subject: [PATCH 13/17] Better indentation --- lab2CA.srcs/sources_1/new/FetchUnit.v | 11 ++++++----- lab2CA.srcs/sources_1/new/RegFile.v | 10 ++++++---- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/FetchUnit.v b/lab2CA.srcs/sources_1/new/FetchUnit.v index 3e77260..17440c3 100644 --- a/lab2CA.srcs/sources_1/new/FetchUnit.v +++ b/lab2CA.srcs/sources_1/new/FetchUnit.v @@ -1,9 +1,11 @@ `timescale 1ns / 1ps -module FetchUnit(input wire clk, reset, - input wire op_idx, - input wire [8:0] AddrIn, - output wire [8:0] AddrOut); +module FetchUnit( + input wire clk, reset, + input wire op_idx, + input wire [8:0] AddrIn, + output wire [8:0] AddrOut + ); //Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a) wire [8:0] progC_out, result_m; @@ -29,7 +31,6 @@ module FetchUnit(input wire clk, reset, .out(result_m), .switch(op_idx)); - endmodule //testbench diff --git a/lab2CA.srcs/sources_1/new/RegFile.v b/lab2CA.srcs/sources_1/new/RegFile.v index de3ea8e..3a4e24c 100644 --- a/lab2CA.srcs/sources_1/new/RegFile.v +++ b/lab2CA.srcs/sources_1/new/RegFile.v @@ -1,9 +1,11 @@ `timescale 1ns / 1ps -module RegFile(input wire clk, reset, enable, - input wire [1:0] write_index, op0_idx, op1_idx, - input wire [8:0] write_data, - output wire [8:0] op0, op1); +module RegFile( + input wire clk, reset, enable, + input wire [1:0] write_index, op0_idx, op1_idx, + input wire [8:0] write_data, + output wire [8:0] op0, op1 + ); wire [3:0] decOut; wire [8:0] r0_out, r1_out, r2_out, r3_out; From 858c1b8e9861bfbac197fa1edc71cd650968eef3 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Sat, 6 Apr 2019 16:09:05 -0400 Subject: [PATCH 14/17] Added a lot of points --- CPU9bits_tb_behav.wcfg | 477 +++++++++++++++++++++++++++++++++++------ 1 file changed, 417 insertions(+), 60 deletions(-) diff --git a/CPU9bits_tb_behav.wcfg b/CPU9bits_tb_behav.wcfg index fbb7e7a..3a75952 100644 --- a/CPU9bits_tb_behav.wcfg +++ b/CPU9bits_tb_behav.wcfg @@ -3,119 +3,472 @@ - + - + - - - + + + - + - - - reset - reset - - - Registers + + + CPU label - + + reset reset - - op0_idx[1:0] - op0_idx[1:0] + + clk + clk - - op1_idx[1:0] - op1_idx[1:0] + + result[8:0] + result[8:0] - - write_data[8:0] - write_data[8:0] + + done + done - - op0[8:0] - op0[8:0] + + instr[8:0] + instr[8:0] - + op1[8:0] op1[8:0] - + + op0[8:0] + op0[8:0] + + + FUAddr[8:0] + FUAddr[8:0] + + + FUJB[8:0] + FUJB[8:0] + + + PCout[8:0] + PCout[8:0] + + + JBRes[8:0] + JBRes[8:0] + + + FUJ[8:0] + FUJ[8:0] + + + FUB[8:0] + FUB[8:0] + + + AddiOut[8:0] + AddiOut[8:0] + + + AluOut[8:0] + AluOut[8:0] + + + RFIn[8:0] + RFIn[8:0] + + + loadMux[8:0] + loadMux[8:0] + + + dataMemOut[8:0] + dataMemOut[8:0] + + + linkData[8:0] + linkData[8:0] + + + SE1N[8:0] + SE1N[8:0] + + + SE2N[8:0] + SE2N[8:0] + + + SE3N[8:0] + SE3N[8:0] + + + bankData[8:0] + bankData[8:0] + + + bankOP[8:0] + bankOP[8:0] + + + jumpNeg[8:0] + jumpNeg[8:0] + + + aluOp[3:0] + aluOp[3:0] + + + FU[2:0] + FU[2:0] + + + bankS[1:0] + bankS[1:0] + + + addiS + addiS + + + RegEn + RegEn + + + loadS + loadS + + + fetchBranch + fetchBranch + + + halt + halt + + + cout0 + cout0 + + + cout1 + cout1 + + + link + link + + + js + js + + + dataMemEn + dataMemEn + + + + Control Unit + label + + instIn[3:0] + instIn[3:0] + + + functBit + functBit + + + aluOut[3:0] + aluOut[3:0] + + + FU[2:0] + FU[2:0] + + + bank[1:0] + bank[1:0] + + + addi + addi + + + mem + mem + + + dataMemEn + dataMemEn + + + RegEn + RegEn + + + halt + halt + + + link + link + + + js + js + + + + Fetch Unit + label + + clk + clk + + + reset + reset + + + op_idx + op_idx + + + AddrIn[8:0] + AddrIn[8:0] + + + AddrOut[8:0] + AddrOut[8:0] + + + progC_out[8:0] + progC_out[8:0] + + + result_m[8:0] + result_m[8:0] + + + cout + cout + + + + ALU + label + + opcode[3:0] + opcode[3:0] + + + operand0[8:0] + operand0[8:0] + + + operand1[8:0] + operand1[8:0] + + + result[8:0] + result[8:0] + + + result_A[8:0] + result_A[8:0] + + + result_B[8:0] + result_B[8:0] + + + result_C[8:0] + result_C[8:0] + + + result_D[8:0] + result_D[8:0] + + + result_E[8:0] + result_E[8:0] + + + result_F[8:0] + result_F[8:0] + + + result_G[8:0] + result_G[8:0] + + + result_H[8:0] + result_H[8:0] + + + result_I[8:0] + result_I[8:0] + + + result_J[8:0] + result_J[8:0] + + + result_K[8:0] + result_K[8:0] + + + result_L[8:0] + result_L[8:0] + + + result_M[8:0] + result_M[8:0] + + + result_N[8:0] + result_N[8:0] + + + result_O[8:0] + result_O[8:0] + + + result_P[8:0] + result_P[8:0] + + + cout + cout + + + + Registers + label + + clk + clk + + + reset + reset + + + enable + enable + + + write_index[1:0] + write_index[1:0] + + + op0_idx[1:0] + op0_idx[1:0] + + + op1_idx[1:0] + op1_idx[1:0] + + + write_data[8:0] + write_data[8:0] + + + op0[8:0] + op0[8:0] + + + op1[8:0] + op1[8:0] + + + decOut[3:0] + decOut[3:0] + + r0_out[8:0] r0_out[8:0] - + r1_out[8:0] r1_out[8:0] - + r2_out[8:0] r2_out[8:0] - + r3_out[8:0] r3_out[8:0] - + Banks label - + + clk + clk + + reset reset - + + enable + enable + + write_index[1:0] write_index[1:0] - + op0_idx[1:0] op0_idx[1:0] - + op1_idx[1:0] op1_idx[1:0] - + write_data[8:0] write_data[8:0] - + op0[8:0] op0[8:0] - + op1[8:0] op1[8:0] - + decOut[3:0] decOut[3:0] - + r0_out[8:0] r0_out[8:0] - + r1_out[8:0] r1_out[8:0] - + r2_out[8:0] r2_out[8:0] - + r3_out[8:0] r3_out[8:0] @@ -124,44 +477,48 @@ Divider label - + Instruction Memory label - + address[8:0] address[8:0] - + + memory[100:0][8:0] + memory[100:0][8:0] + + readData[8:0] readData[8:0] - - label - memory[100:0][8:0] - memory[100:0][8:0] - Instruction Memory - - + Data Memory label - + + clk + clk + + + writeEnable + writeEnable + + address[8:0] address[8:0] - + writeData[8:0] writeData[8:0] - + readData[8:0] readData[8:0] - - label + memory[100:0][8:0] memory[100:0][8:0] - Data Memory From 809bca06bf1eff9ef5425f1325e1995a7943ac7b Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Sat, 6 Apr 2019 16:09:17 -0400 Subject: [PATCH 15/17] Vivado metadata --- lab2CA.xpr | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/lab2CA.xpr b/lab2CA.xpr index e16ecfb..bfc5aac 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -31,7 +31,7 @@