From 6369170e4178da0aa41c316ca65333178c05f201 Mon Sep 17 00:00:00 2001
From: WilliamMiceli <git@williammiceli.io>
Date: Fri, 15 Feb 2019 17:49:12 -0500
Subject: [PATCH] Comments and slight renames

---
 lab2CA.srcs/sources_1/new/ALU.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v
index b6b50c4..ed0435b 100644
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -1,7 +1,7 @@
 `timescale 1ns / 1ps
 
 module ALU(
-    input wire [2:0] opcode,
+    input wire [2:0] opcode, // NOT the same as the instruction set opcode
     input wire [8:0] operand0,
     input wire [8:0] operand1,
     output wire [8:0] result 
@@ -25,8 +25,8 @@ module ALU(
     // H (111)
     
     
-    // MUX chooses which result to show based on the OPCODE
-    mux_8_1 mux_result(
+    // MUX chooses which result to show based on the ALU's opcode
+    mux_8_1 mux0(
         .switch(opcode),
         .A(result_A),
         .B(result_B),