diff --git a/Bank_behav1.wcfg b/Bank_behav1.wcfg index 6b6b291..33afe34 100644 --- a/Bank_behav1.wcfg +++ b/Bank_behav1.wcfg @@ -3,44 +3,162 @@ - + - + - - - + + + - + - - + + clk clk - - writeEnable - writeEnable + + reset + reset - + + done + done + + + clk + clk + + address[8:0] address[8:0] - + UNSIGNEDDECRADIX - - writeData[8:0] - writeData[8:0] - - - + readData[8:0] readData[8:0] + + enable + enable + + + write_index[1:0] + write_index[1:0] + + + op0[8:0] + op0[8:0] + + + op1[8:0] + op1[8:0] + + + r0_out[8:0] + r0_out[8:0] + UNSIGNEDDECRADIX + + + r1_out[8:0] + r1_out[8:0] + UNSIGNEDDECRADIX + + + r2_out[8:0] + r2_out[8:0] + UNSIGNEDDECRADIX + + + r3_out[8:0] + r3_out[8:0] + UNSIGNEDDECRADIX + + + enable + enable + + + write_index[1:0] + write_index[1:0] + + + op0_idx[1:0] + op0_idx[1:0] + + + write_data[8:0] + write_data[8:0] + + + op0[8:0] + op0[8:0] + + + r0_out[8:0] + r0_out[8:0] + UNSIGNEDDECRADIX + + + r1_out[8:0] + r1_out[8:0] + + + r2_out[8:0] + r2_out[8:0] + UNSIGNEDDECRADIX + + + r3_out[8:0] + r3_out[8:0] + + + AddrIn[8:0] + AddrIn[8:0] + + + AddrOut[8:0] + AddrOut[8:0] + UNSIGNEDDECRADIX + + + progC_out[8:0] + progC_out[8:0] + + + result_m[8:0] + result_m[8:0] + + + A[8:0] + A[8:0] + + + B[8:0] + B[8:0] + + + Sum[8:0] + Sum[8:0] + + + addi + addi + + + A[2:0] + A[2:0] + + + B[8:0] + B[8:0] + diff --git a/CPU9bits_tb_behav.wcfg b/CPU9bits_tb_behav.wcfg index 96973fa..5f82acf 100644 --- a/CPU9bits_tb_behav.wcfg +++ b/CPU9bits_tb_behav.wcfg @@ -11,13 +11,13 @@ - - - + + + - - + + @@ -35,42 +35,59 @@ instr[8:0] instr[8:0] + AddrOut[8:0] AddrOut[8:0] + label r0_out[8:0] r0_out[8:0] + RegisterA + label r1_out[8:0] r1_out[8:0] + RegisterB + label r2_out[8:0] r2_out[8:0] + RegisterC + label r3_out[8:0] r3_out[8:0] + RegisterD + label r0_out[8:0] r0_out[8:0] + Bank0 + label r1_out[8:0] r1_out[8:0] + Bank1 + label r2_out[8:0] r2_out[8:0] + Bank2 + label r3_out[8:0] r3_out[8:0] + Bank3 switch @@ -89,8 +106,11 @@ writeData[8:0] + label memory[15:0][8:0] memory[15:0][8:0] + Data Memory + readData[8:0] diff --git a/lab2CA.runs/.jobs/vrs_config_42.xml b/lab2CA.runs/.jobs/vrs_config_42.xml index b013dc9..c86769b 100644 --- a/lab2CA.runs/.jobs/vrs_config_42.xml +++ b/lab2CA.runs/.jobs/vrs_config_42.xml @@ -1,9 +1,6 @@ - - - - + diff --git a/lab2CA.runs/impl_1/CPU9bits_tb.tcl b/lab2CA.runs/impl_1/CPU9bits_tb.tcl deleted file mode 100644 index e128472..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_tb.tcl +++ /dev/null @@ -1,153 +0,0 @@ -# -# Report generation script generated by Vivado -# - -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -proc start_step { step } { - set stopFile ".stop.rst" - if {[file isfile .stop.rst]} { - puts "" - puts "*** Halting run - EA reset detected ***" - puts "" - puts "" - return -code error - } - set beginFile ".$step.begin.rst" - set platform "$::tcl_platform(platform)" - set user "$::tcl_platform(user)" - set pid [pid] - set host "" - if { [string equal $platform unix] } { - if { [info exist ::env(HOSTNAME)] } { - set host $::env(HOSTNAME) - } - } else { - if { [info exist ::env(COMPUTERNAME)] } { - set host $::env(COMPUTERNAME) - } - } - set ch [open $beginFile w] - puts $ch "" - puts $ch "" - puts $ch " " - puts $ch " " - puts $ch "" - close $ch -} - -proc end_step { step } { - set endFile ".$step.end.rst" - set ch [open $endFile w] - close $ch -} - -proc step_failed { step } { - set endFile ".$step.error.rst" - set ch [open $endFile w] - close $ch -} - -set_msg_config -id {Synth 8-256} -limit 10000 -set_msg_config -id {Synth 8-638} -limit 10000 - -start_step init_design -set ACTIVE_STEP init_design -set rc [catch { - create_msg_db init_design.pb - set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-784-DESKTOP-8QFGS52/incrSyn - create_project -in_memory -part xc7k160tifbg484-2L - set_property design_mode GateLvl [current_fileset] - set_param project.singleFileAddWarning.threshold 0 - set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project] - set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project] - set_property ip_output_repo C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project] - set_property ip_cache_permissions {read write} [current_project] - add_files -quiet C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.dcp - link_design -top CPU9bits_tb -part xc7k160tifbg484-2L - close_msg_db -file init_design.pb -} RESULT] -if {$rc} { - step_failed init_design - return -code error $RESULT -} else { - end_step init_design - unset ACTIVE_STEP -} - -start_step opt_design -set ACTIVE_STEP opt_design -set rc [catch { - create_msg_db opt_design.pb - opt_design - write_checkpoint -force CPU9bits_tb_opt.dcp - create_report "impl_1_opt_report_drc_0" "report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx" - close_msg_db -file opt_design.pb -} RESULT] -if {$rc} { - step_failed opt_design - return -code error $RESULT -} else { - end_step opt_design - unset ACTIVE_STEP -} - -start_step place_design -set ACTIVE_STEP place_design -set rc [catch { - create_msg_db place_design.pb - if { [llength [get_debug_cores -quiet] ] > 0 } { - implement_debug_core - } - place_design - write_checkpoint -force CPU9bits_tb_placed.dcp - create_report "impl_1_place_report_io_0" "report_io -file CPU9bits_tb_io_placed.rpt" - create_report "impl_1_place_report_utilization_0" "report_utilization -file CPU9bits_tb_utilization_placed.rpt -pb CPU9bits_tb_utilization_placed.pb" - create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CPU9bits_tb_control_sets_placed.rpt" - close_msg_db -file place_design.pb -} RESULT] -if {$rc} { - step_failed place_design - return -code error $RESULT -} else { - end_step place_design - unset ACTIVE_STEP -} - -start_step route_design -set ACTIVE_STEP route_design -set rc [catch { - create_msg_db route_design.pb - route_design - write_checkpoint -force CPU9bits_tb_routed.dcp - create_report "impl_1_route_report_drc_0" "report_drc -file CPU9bits_tb_drc_routed.rpt -pb CPU9bits_tb_drc_routed.pb -rpx CPU9bits_tb_drc_routed.rpx" - create_report "impl_1_route_report_methodology_0" "report_methodology -file CPU9bits_tb_methodology_drc_routed.rpt -pb CPU9bits_tb_methodology_drc_routed.pb -rpx CPU9bits_tb_methodology_drc_routed.rpx" - create_report "impl_1_route_report_power_0" "report_power -file CPU9bits_tb_power_routed.rpt -pb CPU9bits_tb_power_summary_routed.pb -rpx CPU9bits_tb_power_routed.rpx" - create_report "impl_1_route_report_route_status_0" "report_route_status -file CPU9bits_tb_route_status.rpt -pb CPU9bits_tb_route_status.pb" - create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file CPU9bits_tb_timing_summary_routed.rpt -pb CPU9bits_tb_timing_summary_routed.pb -rpx CPU9bits_tb_timing_summary_routed.rpx -warn_on_violation " - create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CPU9bits_tb_incremental_reuse_routed.rpt" - create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CPU9bits_tb_clock_utilization_routed.rpt" - create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file CPU9bits_tb_bus_skew_routed.rpt -pb CPU9bits_tb_bus_skew_routed.pb -rpx CPU9bits_tb_bus_skew_routed.rpx" - close_msg_db -file route_design.pb -} RESULT] -if {$rc} { - write_checkpoint -force CPU9bits_tb_routed_error.dcp - step_failed route_design - return -code error $RESULT -} else { - end_step route_design - unset ACTIVE_STEP -} - diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml deleted file mode 100644 index 4a45751..0000000 --- a/lab2CA.runs/impl_1/gen_run.xml +++ /dev/null @@ -1,167 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/lab2CA.runs/impl_1/htr.txt b/lab2CA.runs/impl_1/htr.txt deleted file mode 100644 index eb33653..0000000 --- a/lab2CA.runs/impl_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log CPU9bits_tb.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace diff --git a/lab2CA.runs/synth_1/CPU9bits.dcp b/lab2CA.runs/synth_1/CPU9bits.dcp new file mode 100644 index 0000000..e08a20c Binary files /dev/null and b/lab2CA.runs/synth_1/CPU9bits.dcp differ diff --git a/lab2CA.runs/synth_1/CPU9bits.vds b/lab2CA.runs/synth_1/CPU9bits.vds new file mode 100644 index 0000000..8dd8172 --- /dev/null +++ b/lab2CA.runs/synth_1/CPU9bits.vds @@ -0,0 +1,400 @@ +#----------------------------------------------------------- +# Vivado v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sun Mar 24 16:57:48 2019 +# Process ID: 9320 +# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1 +# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl +# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds +# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source CPU9bits.tcl -notrace +Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 4932 +WARNING: [Synth 8-1958] event expressions must result in a singular type [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81] +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 376.207 ; gain = 113.672 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] +INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] +INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] +INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] +WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81] +WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81] +INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] +INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] +INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268] +INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] +INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777] +INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777] +INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412] +INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407] +INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] +INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] +INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] +INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] +INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] +INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] +INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342] +INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336] +INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] +INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] +INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311] +INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376] +INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687] +INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687] +INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376] +INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311] +INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724] +INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724] +INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643] +INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643] +INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] +INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] +INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] +INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] +INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] +INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] +INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] +INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] +INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541] +INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] +WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] +WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] +WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] +WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] +INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] +INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17] +INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] +INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996] +INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996] +INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356] +INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] +INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] +WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0] +WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0] +WARNING: [Synth 8-3331] design shift_left has unconnected port A[8] +WARNING: [Synth 8-3331] design instructionMemory has unconnected port clk +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tifbg484-2L +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7k160tifbg484-2L +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[15]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[14]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[13]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[12]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[11]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[10]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[9]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[8]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[7]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[6]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[5]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[4]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[3]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[2]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[1]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[0]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] +WARNING: [Synth 8-327] inferring latch for variable 'dataMemEn_reg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:26] +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 461.227 ; gain = 198.691 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_3bit) to 'SE3' + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 162 ++---Registers : + 9 Bit Registers := 9 ++---Muxes : + 2 Input 9 Bit Muxes := 28 + 4 Input 9 Bit Muxes := 4 + 2 Input 4 Bit Muxes := 2 + 4 Input 4 Bit Muxes := 2 + 16 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 2 + 16 Input 3 Bit Muxes := 1 + 16 Input 2 Bit Muxes := 1 + 16 Input 1 Bit Muxes := 24 + 2 Input 1 Bit Muxes := 33 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module dataMemory +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 20 + 16 Input 1 Bit Muxes := 16 + 2 Input 1 Bit Muxes := 32 +Module decoder +Detailed RTL Component Info : ++---Muxes : + 2 Input 4 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 +Module register +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 +Module mux_4_1 +Detailed RTL Component Info : ++---Muxes : + 4 Input 9 Bit Muxes := 1 +Module add_1bit +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module mux_2_1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 1 +Module ControlUnit +Detailed RTL Component Info : ++---Muxes : + 16 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 2 + 16 Input 3 Bit Muxes := 1 + 16 Input 2 Bit Muxes := 1 + 16 Input 1 Bit Muxes := 8 +Module bit1_mux_2_1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 723.004 ; gain = 460.469 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +ROM: ++------------------+------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------------+------------+---------------+----------------+ +|instructionMemory | p_0_out | 64x9 | LUT | +|CPU9bits | p_0_out | 64x9 | LUT | ++------------------+------------+---------------+----------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 723.004 ; gain = 460.469 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 723.004 ; gain = 460.469 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |BUFG | 2| +|2 |LUT2 | 45| +|3 |LUT3 | 50| +|4 |LUT4 | 51| +|5 |LUT5 | 69| +|6 |LUT6 | 439| +|7 |MUXF7 | 6| +|8 |FDRE | 81| +|9 |LD | 154| +|10 |IBUF | 2| +|11 |OBUF | 1| ++------+------+------+ + +Report Instance Areas: ++------+---------+------------+------+ +| |Instance |Module |Cells | ++------+---------+------------+------+ +|1 |top | | 900| +|2 | Bank |RegFile | 45| +|3 | r0 |register_5 | 16| +|4 | r1 |register_6 | 9| +|5 | r2 |register_7 | 10| +|6 | r3 |register_8 | 10| +|7 | CU |ControlUnit | 14| +|8 | FetchU |FetchUnit | 126| +|9 | PC |register_4 | 126| +|10 | RF |RegFile_0 | 345| +|11 | r0 |register | 216| +|12 | r1 |register_1 | 14| +|13 | r2 |register_2 | 100| +|14 | r3 |register_3 | 15| +|15 | dM |dataMemory | 365| ++------+---------+------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 29 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +Synthesis Optimization Complete : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 160 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 723.004 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 154 instances were transformed. + LD => LDCE: 154 instances + +INFO: [Common 17-83] Releasing license: Synthesis +70 Infos, 29 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 723.004 ; gain = 473.363 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 723.004 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 16:58:31 2019... diff --git a/lab2CA.runs/synth_1/CPU9bits_tb.tcl b/lab2CA.runs/synth_1/CPU9bits_tb.tcl index e432b1e..0ff5867 100644 --- a/lab2CA.runs/synth_1/CPU9bits_tb.tcl +++ b/lab2CA.runs/synth_1/CPU9bits_tb.tcl @@ -17,7 +17,7 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } -set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-784-DESKTOP-8QFGS52/incrSyn +set_param synth.incrementalSynthesisCache C:/Users/willi/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-18452-WM-G75VW/incrSyn set_msg_config -id {Synth 8-256} -limit 10000 set_msg_config -id {Synth 8-638} -limit 10000 create_project -in_memory -part xc7k160tifbg484-2L @@ -25,21 +25,21 @@ create_project -in_memory -part xc7k160tifbg484-2L set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true -set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project] -set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project] +set_property webtalk.parent_dir {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/wt} [current_project] +set_property parent.project_path {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr} [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] -set_property ip_output_repo c:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project] +set_property ip_output_repo {c:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/ip} [current_project] set_property ip_cache_permissions {read write} [current_project] read_verilog -library xil_defaultlib { - C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v - C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v - C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v - C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v - C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v - C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v - C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v - C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v} } # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -52,12 +52,12 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { set_param ips.enableIPCacheLiteLoad 1 close [open __synthesis_is_running__ w] -synth_design -top CPU9bits_tb -part xc7k160tifbg484-2L +synth_design -top CPU9bits -part xc7k160tifbg484-2L # disable binary constraint mode for synth run checkpoints set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef CPU9bits_tb.dcp -create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb" +write_checkpoint -force -noxdef CPU9bits.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb" file delete __synthesis_is_running__ close [open __synthesis_is_complete__ w] diff --git a/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt b/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt index f2011a8..eb83468 100644 --- a/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt +++ b/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt @@ -1,13 +1,13 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------ +----------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sun Mar 24 18:38:37 2019 -| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) -| Command : report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb -| Design : CPU9bits_tb +| Date : Sun Mar 24 16:58:30 2019 +| Host : WM-G75VW running 64-bit major release (build 9200) +| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb +| Design : CPU9bits | Device : 7k160tifbg484-2L -| Design State : Fully Placed ------------------------------------------------------------------------------------------------------------------ +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------- Utilization Design Information @@ -15,15 +15,14 @@ Table of Contents ----------------- 1. Slice Logic 1.1 Summary of Registers by Type -2. Slice Logic Distribution -3. Memory -4. DSP -5. IO and GT Specific -6. Clocking -7. Specific Feature -8. Primitives -9. Black Boxes -10. Instantiated Netlists +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists 1. Slice Logic -------------- @@ -31,15 +30,16 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs | 0 | 0 | 101400 | 0.00 | -| LUT as Logic | 0 | 0 | 101400 | 0.00 | +| Slice LUTs* | 578 | 0 | 101400 | 0.57 | +| LUT as Logic | 578 | 0 | 101400 | 0.57 | | LUT as Memory | 0 | 0 | 35000 | 0.00 | -| Slice Registers | 0 | 0 | 202800 | 0.00 | -| Register as Flip Flop | 0 | 0 | 202800 | 0.00 | -| Register as Latch | 0 | 0 | 202800 | 0.00 | -| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| Slice Registers | 235 | 0 | 202800 | 0.12 | +| Register as Flip Flop | 81 | 0 | 202800 | 0.04 | +| Register as Latch | 154 | 0 | 202800 | 0.08 | +| F7 Muxes | 6 | 0 | 50700 | 0.01 | | F8 Muxes | 0 | 0 | 25350 | 0.00 | +-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. 1.1 Summary of Registers by Type @@ -55,34 +55,13 @@ Table of Contents | 0 | _ | Reset | - | | 0 | Yes | - | - | | 0 | Yes | - | Set | -| 0 | Yes | - | Reset | +| 154 | Yes | - | Reset | | 0 | Yes | Set | - | -| 0 | Yes | Reset | - | +| 81 | Yes | Reset | - | +-------+--------------+-------------+--------------+ -2. Slice Logic Distribution ---------------------------- - -+------------------------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------------------------------------+------+-------+-----------+-------+ -| Slice | 0 | 0 | 25350 | 0.00 | -| SLICEL | 0 | 0 | | | -| SLICEM | 0 | 0 | | | -| LUT as Logic | 0 | 0 | 101400 | 0.00 | -| LUT as Memory | 0 | 0 | 35000 | 0.00 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 0 | 0 | | | -| Slice Registers | 0 | 0 | 202800 | 0.00 | -| Register driven from within the Slice | 0 | | | | -| Register driven from outside the Slice | 0 | | | | -| Unique Control Sets | 0 | | 25350 | 0.00 | -+------------------------------------------+------+-------+-----------+-------+ -* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. - - -3. Memory +2. Memory --------- +----------------+------+-------+-----------+-------+ @@ -95,7 +74,7 @@ Table of Contents * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 -4. DSP +3. DSP ------ +-----------+------+-------+-----------+-------+ @@ -105,13 +84,13 @@ Table of Contents +-----------+------+-------+-----------+-------+ -5. IO and GT Specific +4. IO and GT Specific --------------------- +-----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 285 | 0.00 | +| Bonded IOB | 3 | 0 | 285 | 1.05 | | Bonded IPADs | 0 | 0 | 14 | 0.00 | | Bonded OPADs | 0 | 0 | 8 | 0.00 | | PHY_CONTROL | 0 | 0 | 8 | 0.00 | @@ -132,13 +111,13 @@ Table of Contents +-----------------------------+------+-------+-----------+-------+ -6. Clocking +5. Clocking ----------- +------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFGCTRL | 2 | 0 | 32 | 6.25 | | BUFIO | 0 | 0 | 32 | 0.00 | | MMCME2_ADV | 0 | 0 | 8 | 0.00 | | PLLE2_ADV | 0 | 0 | 8 | 0.00 | @@ -148,7 +127,7 @@ Table of Contents +------------+------+-------+-----------+-------+ -7. Specific Feature +6. Specific Feature ------------------- +-------------+------+-------+-----------+-------+ @@ -166,15 +145,27 @@ Table of Contents +-------------+------+-------+-----------+-------+ -8. Primitives +7. Primitives ------------- +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ +| LUT6 | 439 | LUT | +| LDCE | 154 | Flop & Latch | +| FDRE | 81 | Flop & Latch | +| LUT5 | 69 | LUT | +| LUT4 | 51 | LUT | +| LUT3 | 50 | LUT | +| LUT2 | 45 | LUT | +| MUXF7 | 6 | MuxFx | +| IBUF | 2 | IO | +| BUFG | 2 | Clock | +| OBUF | 1 | IO | ++----------+------+---------------------+ -9. Black Boxes +8. Black Boxes -------------- +----------+------+ @@ -182,8 +173,8 @@ Table of Contents +----------+------+ -10. Instantiated Netlists -------------------------- +9. Instantiated Netlists +------------------------ +----------+------+ | Ref Name | Used | diff --git a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb new file mode 100644 index 0000000..8c1d275 Binary files /dev/null and b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb differ diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml index 24a12d9..fbd2015 100644 --- a/lab2CA.runs/synth_1/gen_run.xml +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - - - - - - - - + + + + + + + @@ -77,7 +74,7 @@ diff --git a/lab2CA.runs/synth_1/vivado.jou b/lab2CA.runs/synth_1/vivado.jou index 41f08c9..c45f63a 100644 --- a/lab2CA.runs/synth_1/vivado.jou +++ b/lab2CA.runs/synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 18:28:31 2019 -# Process ID: 5228 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1 -# Command line: vivado.exe -log CPU9bits_tb.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.vds -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou +# Start of session at: Sun Mar 24 16:57:48 2019 +# Process ID: 9320 +# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1 +# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl +# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds +# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou #----------------------------------------------------------- -source CPU9bits_tb.tcl -notrace +source CPU9bits.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou index 365bf7a..fe12bc0 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 17:35:36 2019 -# Process ID: 12488 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +# Start of session at: Sun Mar 24 17:05:08 2019 +# Process ID: 16036 +# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/REPOSITORIES/Educational/Western -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_14824.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_14824.backup.jou new file mode 100644 index 0000000..0520b47 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_14824.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sun Mar 24 16:59:36 2019 +# Process ID: 14824 +# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/REPOSITORIES/Educational/Western -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou deleted file mode 100644 index 9df8652..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 11:08:04 2019 -# Process ID: 15032 -# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/JoseIgnacio/CA -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index 175ab93..2d750dd 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xelab.pb and b/lab2CA.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb index cb4f1a0..912913c 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb and b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/lab2CA.srcs/sources_1/new/instructionMemory.v b/lab2CA.srcs/sources_1/new/instructionMemory.v index 220bca3..3104780 100644 --- a/lab2CA.srcs/sources_1/new/instructionMemory.v +++ b/lab2CA.srcs/sources_1/new/instructionMemory.v @@ -79,120 +79,136 @@ module instructionMemory( // memory[39] <= 9'b000000000; - // Bubble Sort -// memory[0] <= 9'b000000001; -// memory[1] <= 9'b010000000; -// memory[2] <= 9'b000100000; -// memory[3] <= 9'b010001000; -// memory[4] <= 9'b010010000; -// memory[5] <= 9'b010011000; -// memory[6] <= 9'b101001000; -// memory[7] <= 9'b101001010; -// memory[8] <= 9'b100100011; -// memory[9] <= 9'b101001001; -// memory[10] <= 9'b011001001; -// memory[11] <= 9'b101001000; -// memory[12] <= 9'b101001001; -// memory[13] <= 9'b011101000; -// memory[14] <= 9'b110001010; -// memory[15] <= 9'b100100001; -// memory[16] <= 9'b100110100; -// memory[17] <= 9'b101001001; -// memory[18] <= 9'b011001001; -// memory[19] <= 9'b000110010; -// memory[20] <= 9'b011001001; -// memory[21] <= 9'b000111010; -// memory[22] <= 9'b101011110; -// memory[23] <= 9'b011111100; -// memory[24] <= 9'b110011010; -// memory[25] <= 9'b100100001; -// memory[26] <= 9'b101110010; -// memory[27] <= 9'b101001001; -// memory[28] <= 9'b011001001; -// memory[29] <= 9'b101011111; -// memory[30] <= 9'b001011010; -// memory[31] <= 9'b011001001; -// memory[32] <= 9'b001010010; -// memory[33] <= 9'b010001000; -// memory[34] <= 9'b011001001; -// memory[35] <= 9'b101001010; -// memory[36] <= 9'b101111100; -// memory[37] <= 9'b101001011; -// memory[38] <= 9'b110001001; -// memory[39] <= 9'b100100001; -// memory[40] <= 9'b100100011; -// memory[41] <= 9'b010001000; -// memory[42] <= 9'b101001000; -// memory[43] <= 9'b101111011; -// memory[44] <= 9'b000000000; +// Bubble Sort + memory[0] <= 9'b000000001; // nop + // Setup + memory[1] <= 9'b010000000; // zero $a + memory[2] <= 9'b000100000; // lb $a, $a + memory[3] <= 9'b010001000; // zero $b + memory[4] <= 9'b010010000; // zero $c + memory[5] <= 9'b010011000; // zero $d + memory[6] <= 9'b101001000; // banks $b, $0 + memory[7] <= 9'b101001010; // banks $b, $1 + memory[8] <= 9'b100100011; // jf EndChk + // Increment current index to compare next pair of values + // Inc: + memory[9] <= 9'b101001001; // bankl $b, $0 + memory[10] <= 9'b011001001; // addi $b, 1 + memory[11] <= 9'b101001000; // banks $b, $0 + // Check if at the end of the array + // EndChk: + memory[12] <= 9'b101001001; // bankl $b, $0 + memory[13] <= 9'b011101000; // slt $b, $a + memory[14] <= 9'b110001010; // beq $b, JSC + memory[15] <= 9'b100100001; // jf LoadNext + // JSC: + memory[16] <= 9'b100110100; // jf SwapChk + // Load next values for comparison + // LoadNext: + memory[17] <= 9'b101001001; // bankl $b, $0 + memory[18] <= 9'b011001001; // addi $b, 1 + memory[19] <= 9'b000110010; // lb $c, $b + memory[20] <= 9'b011001001; // addi $b, 1 + memory[21] <= 9'b000111010; // lb $d, $b + // Compare loaded values to see if they need to be swapped + memory[22] <= 9'b101011110; // banks $d, $3 + memory[23] <= 9'b011111100; // slt $d, $c + memory[24] <= 9'b110011010; // beq $d, JI + memory[25] <= 9'b100100001; // jf Swap + // JI: + memory[26] <= 9'b101110010; // jb Inc + // Swap values in array + // Swap: + memory[27] <= 9'b101001001; // bankl $b, $0 + memory[28] <= 9'b011001001; // addi $b, 1 + memory[29] <= 9'b101011111; // bankl $d, $3 + memory[30] <= 9'b001011010; // sb $d, $b + memory[31] <= 9'b011001001; // addi $b, 1 + memory[32] <= 9'b001010010; // sb $c, $b + memory[33] <= 9'b010001000; // zero $b + memory[34] <= 9'b011001001; // addi $b, 1 + memory[35] <= 9'b101001010; // banks $b, $1 + memory[36] <= 9'b101111100; // jb Inc + // Check to see if any swaps have been made in the last iteration + // SwapChk: + memory[37] <= 9'b101001011; // bankl $b, $1 + memory[38] <= 9'b110001001; // beq $b, JE + memory[39] <= 9'b100100001; // jf Reset + // JE: + memory[40] <= 9'b100100011; // jf End + // Reset: + memory[41] <= 9'b010001000; // zero $b + memory[42] <= 9'b101001000; // banks $b, $0 + memory[43] <= 9'b101111011; // jb LoadNext + // End: + memory[44] <= 9'b000000000; // halt // Binary Search - -// memory[0] <= 9'b000000000; -// memory[1] <= 9'b000000000; -// memory[2] <= 9'b000000000; -// memory[3] <= 9'b000000000; -// memory[4] <= 9'b000000000; -// memory[5] <= 9'b000000000; -// memory[6] <= 9'b011001011; //addi R1, 3 (N = 3) -// memory[7] <= 9'b011001011; //addi R1, 3 (N = 3) -// memory[8] <= 9'b011001011; //addi R1, 3 (N = 3) -// memory[9] <= 9'b011001011; //addi R1, 3 (N = 3) -// memory[10] <= 9'b011001011; //addi R1, 3 (N = 3) -// memory[11] <= 9'b011010010; //addi R2, 2 (inputAddr = 2) -// memory[12] <= 9'b000111110; //lb R3, R3 -// memory[13] <= 9'b101011010; //banks R3, 1 -// memory[14] <= 9'b011001011; //addi R1, 3 (N = 3) -// memory[15] <= 9'b101000000; //loop: banks R0, 0 -// memory[16] <= 9'b011100010; //slt R0, R1 -// memory[17] <= 9'b110000001; //beq R0, Exit -// memory[18] <= 9'b100100001; //j Skip0 -// memory[19] <= 9'b100101110; //Exit: j Loose -// memory[20] <= 9'b010101000; //Skip0: add R2, R0 -// memory[21] <= 9'b010101010; //add R2, R1 -// memory[22] <= 9'b111110000; //sll R2 -// memory[23] <= 9'b101011011; //bankl R3,1 -// memory[24] <= 9'b010111100; //add R3, R2 -// memory[25] <= 9'b101001100; //banks R1, 2 -// memory[26] <= 9'b000100110; //lb R0, R3 -// memory[27] <= 9'b010001000; //zero R1 -// memory[28] <= 9'b011001010; //addi R1, 1 (numAddr = 1) -// memory[29] <= 9'b000101010; //lb R1, R1 -// memory[30] <= 9'b100100001; //j SkipU -// memory[31] <= 9'b101110001; //j TransLoop -// memory[32] <= 9'b101010110; //SkipU: banks R2, 3 -// memory[33] <= 9'b100100001; //j SkipD -// memory[34] <= 9'b100110111; //j TransLoose -// memory[35] <= 9'b010010000; //SkipD: zero R2 -// memory[36] <= 9'b010110010; //add R2, R1 -// memory[37] <= 9'b010101001; //sub R1, R0 -// memory[38] <= 9'b110001001; //beq R1, Go1 -// memory[39] <= 9'b100100001; //j Skip1 -// memory[40] <= 9'b100101001; //Go1: j Win -// memory[41] <= 9'b010001000; //Skip1: zero R1 -// memory[42] <= 9'b010101100; //add R1, R2 -// memory[43] <= 9'b011100010; //slt R0, R1 -// memory[44] <= 9'b110001001; //beq R1, Go2 -// memory[45] <= 9'b100100110; //j Skip2 -// memory[46] <= 9'b010000000; //Go2: zero R0 -// memory[47] <= 9'b011000010; //addi R0, 1 -// memory[48] <= 9'b101001111; //bankl R1,3 -// memory[49] <= 9'b010100010; //add R0, R1 -// memory[50] <= 9'b101001101; //bankl R1,2 -// memory[51] <= 9'b101110101; //j loop -// memory[52] <= 9'b010001000; //Skip2: zero R1 -// memory[53] <= 9'b011001111; //addi R1, -1 -// memory[54] <= 9'b101000111; //bankl R0, 3 -// memory[55] <= 9'b010101000; //add R1, R0 -// memory[56] <= 9'b101000001; //bankl R0,0 -// memory[57] <= 9'b101111011; //j loop -// memory[58] <= 9'b010000000; //Loose: zero R0 -// memory[59] <= 9'b011000111; //addi R0, -1 -// memory[60] <= 9'b101000110; //banks R0, 3 -// memory[61] <= 9'b100100000; //j Win -// memory[62] <= 9'b000000000; //Win: halt + memory[0] <= 9'b000000000; + memory[1] <= 9'b000000000; + memory[2] <= 9'b000000000; + memory[3] <= 9'b000000000; + memory[4] <= 9'b000000000; + memory[5] <= 9'b011001011; //addi R1, 3 (N = 3) + memory[6] <= 9'b011001011; //addi R1, 3 (N = 3) + memory[7] <= 9'b011001011; //addi R1, 3 (N = 3) + memory[8] <= 9'b011001011; //addi R1, 3 (N = 3) + memory[9] <= 9'b011001011; //addi R1, 3 (N = 3) + memory[10] <= 9'b011011010; //addi R3, 2 (inputAddr = 2) + memory[11] <= 9'b000111110; //lb R3, R3 + memory[12] <= 9'b101011010; //banks R3, 1 + memory[13] <= 9'b011001011; //addi R1, 3 (N = 3) + memory[14] <= 9'b101000000; //loop: banks R0, 0 + memory[15] <= 9'b011100010; //slt R0, R1 + memory[16] <= 9'b110000001; //beq R0, Exit + memory[17] <= 9'b100100001; //j Skip0 + memory[18] <= 9'b100101111; //Exit: j Loose + memory[19] <= 9'b101000001; //Skip0: bankl R0, 0 + memory[20] <= 9'b010110000; //add R2, R0 + memory[21] <= 9'b010110010; //add R2, R1 + memory[22] <= 9'b111110001; //srl R2 + memory[23] <= 9'b101011011; //bankl R3,1 + memory[24] <= 9'b010111100; //add R3, R2 + memory[25] <= 9'b101001100; //banks R1, 2 + memory[26] <= 9'b000100110; //lb R0, R3 + memory[27] <= 9'b010001000; //zero R1 + memory[28] <= 9'b011001001; //addi R1, 1 (numAddr = 1) + memory[29] <= 9'b000101010; //lb R1, R1 + memory[30] <= 9'b100100001; //j SkipU + memory[31] <= 9'b101110010; //j TransLoop + memory[32] <= 9'b101010110; //SkipU: banks R2, 3 + memory[33] <= 9'b100100001; //j SkipD + memory[34] <= 9'b100110111; //j TransLoose + memory[35] <= 9'b010010000; //SkipD: zero R2 + memory[36] <= 9'b010110010; //add R2, R1 + memory[37] <= 9'b010101001; //sub R1, R0 + memory[38] <= 9'b110001001; //beq R1, Go1 + memory[39] <= 9'b100100001; //j Skip1 + memory[40] <= 9'b100101001; //Go1: j Win + memory[41] <= 9'b010001000; //Skip1: zero R1 + memory[42] <= 9'b010101100; //add R1, R2 + memory[43] <= 9'b011100010; //slt R0, R1 + memory[44] <= 9'b110000001; //beq R0, Go2 + memory[45] <= 9'b100100110; //j Skip2 + memory[46] <= 9'b010000000; //Go2: zero R0 + memory[47] <= 9'b011000001; //addi R0, 1 + memory[48] <= 9'b101001111; //bankl R1,3 + memory[49] <= 9'b010100010; //add R0, R1 + memory[50] <= 9'b101001101; //bankl R1,2 + memory[51] <= 9'b101110101; //j loop + memory[52] <= 9'b010001000; //Skip2: zero R1 + memory[53] <= 9'b011001111; //addi R1, -1 + memory[54] <= 9'b101000111; //bankl R0, 3 + memory[55] <= 9'b010101000; //add R1, R0 + memory[56] <= 9'b101000001; //bankl R0,0 + memory[57] <= 9'b101111011; //j loop + memory[58] <= 9'b010000000; //Loose: zero R0 + memory[59] <= 9'b011000111; //addi R0, -1 + memory[60] <= 9'b101000110; //banks R0, 3 + memory[61] <= 9'b100100000; //j Win + memory[62] <= 9'b000000000; //Win: halt end diff --git a/lab2CA.xpr b/lab2CA.xpr index 39dd50e..64c236e 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - + @@ -146,11 +146,6 @@ - - - - -