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Renamed signals on simulation waveforms

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WilliamMiceli
2019-03-24 17:42:38 -04:00
parent 1c44d8d964
commit 681c506eec
53 changed files with 342 additions and 2667 deletions
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38
lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
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@@ -1,8 +1,8 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sun Mar 24 12:09:01 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Date : Sun Mar 24 16:58:30 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits
| Device : 7k160tifbg484-2L
@@ -30,13 +30,13 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 3 | 0 | 101400 | <0.01 |
| LUT as Logic | 3 | 0 | 101400 | <0.01 |
| Slice LUTs* | 578 | 0 | 101400 | 0.57 |
| LUT as Logic | 578 | 0 | 101400 | 0.57 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 5 | 0 | 202800 | <0.01 |
| Register as Flip Flop | 5 | 0 | 202800 | <0.01 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
| Slice Registers | 235 | 0 | 202800 | 0.12 |
| Register as Flip Flop | 81 | 0 | 202800 | 0.04 |
| Register as Latch | 154 | 0 | 202800 | 0.08 |
| F7 Muxes | 6 | 0 | 50700 | 0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
@@ -55,9 +55,9 @@ Table of Contents
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 154 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 5 | Yes | Reset | - |
| 81 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -117,7 +117,7 @@ Table of Contents
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFGCTRL | 2 | 0 | 32 | 6.25 |
| BUFIO | 0 | 0 | 32 | 0.00 |
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
@@ -151,15 +151,17 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 5 | Flop & Latch |
| LUT5 | 2 | LUT |
| LUT6 | 439 | LUT |
| LDCE | 154 | Flop & Latch |
| FDRE | 81 | Flop & Latch |
| LUT5 | 69 | LUT |
| LUT4 | 51 | LUT |
| LUT3 | 50 | LUT |
| LUT2 | 45 | LUT |
| MUXF7 | 6 | MuxFx |
| IBUF | 2 | IO |
| BUFG | 2 | Clock |
| OBUF | 1 | IO |
| LUT4 | 1 | LUT |
| LUT3 | 1 | LUT |
| LUT2 | 1 | LUT |
| LUT1 | 1 | LUT |
| BUFG | 1 | Clock |
+----------+------+---------------------+