From 71c6c2ad55fcdce4c09e9bd0546f22fdfcbe8e61 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 29 Mar 2019 17:28:50 -0400 Subject: [PATCH] Fixed indentations --- lab2CA.srcs/sources_1/new/ControlUnit.v | 527 ++++++++++++------------ 1 file changed, 264 insertions(+), 263 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v index 613709b..9a0c11e 100644 --- a/lab2CA.srcs/sources_1/new/ControlUnit.v +++ b/lab2CA.srcs/sources_1/new/ControlUnit.v @@ -8,269 +8,270 @@ module ControlUnit( output reg [1:0] bank, output reg addi, mem, dataMemEn, RegEn, halt, link, js); - always @(instIn, functBit)begin - case(instIn) - 4'b0000: // Halt/NOP - begin - halt <= 1'b1; - RegEn <= 1'b1; - FU <= 3'b001; // Disable Branching - addi <= 1'b0; - dataMemEn <= 1'b0; // Disabled - aluOut <= 4'b0000; - mem <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b0001: // Load Byte - begin - aluOut <= 4'b0000; - mem <= 1'b1; - dataMemEn <= 1'b0; // Disabled - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - addi <= 1'b0; - halt <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b0010: // Store Byte - begin - aluOut <= 4'b0000; - mem <= 1'b0; - dataMemEn <= 1'b1; // Enabled - RegEn <= 1'b1; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b0011: // Link - begin - halt <= 1'b0; - RegEn <= 1'b0; - FU <= 3'b001; - addi <= 1'b0; - aluOut <= 4'b0000; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b1; - bank <= 2'b10; - js <= 1'b0; - end - 4'b0100: // Zero - begin - aluOut <= 4'b1011; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b0101: // Add/Subtract - if(functBit == 1) begin // Subtract - aluOut <= 4'b0001; - RegEn <= 1'b0; - FU <= 3'b001; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - else begin // Add - aluOut <= 4'b0000; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b0110: // Add Immediate - begin - aluOut <= 4'b1010; - addi <= 1'b1; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b0111: // Set if Less Than - begin - aluOut <= 4'b1001; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b1000: // Jump to Register - begin - aluOut <= 4'b0000; - FU <= 3'b000; - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b1001: // Jump Forward - begin - aluOut <= 4'b0000; - FU <= 3'b010; - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b1010: // Bank Load/Bank Store - begin - halt <= 1'b0; - RegEn <= !functBit; - FU <= 3'b001; // Disable Branching - addi <= 1'b0; - aluOut <= 4'b0000; - dataMemEn <= 1'b0; // Disabled - mem <= 1'b0; - link <= 1'b0; - bank <= {functBit,functBit}; - js <= 1'b0; - end - 4'b1011: // Jump Backward - begin - aluOut <= 4'b0000; - FU <= 3'b010; - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b1; - end - 4'b1100: // Branch if Zero - begin - aluOut <= 4'b1010; - FU <= 3'b110; - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b1101: // NOR - begin - aluOut <= 4'b0011; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b1110: // OR/AND - if(functBit == 1) // AND - begin - aluOut <= 4'b0100; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - else // OR - begin - aluOut <= 4'b0010; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b1111: // Shift Right Logical/Shift Left Logical - if(functBit == 1) // Shift Right Logical - begin - aluOut <= 4'b0110; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - else // Shift Left Logical - begin - aluOut <= 4'b0101; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; // Disabled - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - default: - begin - halt <= 1'b1; - RegEn <= 1'b1; - FU <= 3'b001; - dataMemEn <= 1'b0; // Disabled - addi <= 1'b0; - aluOut <= 4'b0000; - mem <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end + always @(instIn, functBit) + begin + case(instIn) + 4'b0000: // Halt/NOP + begin + halt <= 1'b1; + RegEn <= 1'b1; + FU <= 3'b001; // Disable Branching + addi <= 1'b0; + dataMemEn <= 1'b0; // Disabled + aluOut <= 4'b0000; + mem <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0001: // Load Byte + begin + aluOut <= 4'b0000; + mem <= 1'b1; + dataMemEn <= 1'b0; // Disabled + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + addi <= 1'b0; + halt <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0010: // Store Byte + begin + aluOut <= 4'b0000; + mem <= 1'b0; + dataMemEn <= 1'b1; // Enabled + RegEn <= 1'b1; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0011: // Link + begin + halt <= 1'b0; + RegEn <= 1'b0; + FU <= 3'b001; + addi <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b1; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0100: // Zero + begin + aluOut <= 4'b1011; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0101: // Add/Subtract + if(functBit == 1) begin // Subtract + aluOut <= 4'b0001; + RegEn <= 1'b0; + FU <= 3'b001; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + else begin // Add + aluOut <= 4'b0000; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0110: // Add Immediate + begin + aluOut <= 4'b1010; + addi <= 1'b1; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0111: // Set if Less Than + begin + aluOut <= 4'b1001; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b1000: // Jump to Register + begin + aluOut <= 4'b0000; + FU <= 3'b000; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b1001: // Jump Forward + begin + aluOut <= 4'b0000; + FU <= 3'b010; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b1010: // Bank Load/Bank Store + begin + halt <= 1'b0; + RegEn <= !functBit; + FU <= 3'b001; // Disable Branching + addi <= 1'b0; + aluOut <= 4'b0000; + dataMemEn <= 1'b0; // Disabled + mem <= 1'b0; + link <= 1'b0; + bank <= {functBit,functBit}; + js <= 1'b0; + end + 4'b1011: // Jump Backward + begin + aluOut <= 4'b0000; + FU <= 3'b010; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b1; + end + 4'b1100: // Branch if Zero + begin + aluOut <= 4'b1010; + FU <= 3'b110; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b1101: // NOR + begin + aluOut <= 4'b0011; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b1110: // OR/AND + if(functBit == 1) // AND + begin + aluOut <= 4'b0100; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + else // OR + begin + aluOut <= 4'b0010; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b1111: // Shift Right Logical/Shift Left Logical + if(functBit == 1) // Shift Right Logical + begin + aluOut <= 4'b0110; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + else // Shift Left Logical + begin + aluOut <= 4'b0101; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; // Disabled + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + default: + begin + halt <= 1'b1; + RegEn <= 1'b1; + FU <= 3'b001; + dataMemEn <= 1'b0; // Disabled + addi <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end endcase end endmodule