From 7406cddb64cfd097b1bd9c11dde7ffa234a6d91c Mon Sep 17 00:00:00 2001 From: "jose.rodriguezlabra" Date: Sun, 10 Mar 2019 14:05:21 -0400 Subject: [PATCH] case for control unit --- lab2CA.srcs/sources_1/new/CPU9bits.v | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v index 8d766b6..f158e15 100644 --- a/lab2CA.srcs/sources_1/new/CPU9bits.v +++ b/lab2CA.srcs/sources_1/new/CPU9bits.v @@ -1,8 +1,8 @@ `timescale 1ns / 1ps module CPU9bits(input wire [8:0] instr, - input wire reset, clk, - output reg done + input wire reset, clk, + output reg done ); wire [8:0] op1, op2; @@ -36,7 +36,11 @@ module CPU9bits(input wire [8:0] instr, //Make control unit here - + always @(instr) begin + case (instr) + 9'b000000000: //something + endcase + end //------------------------------