diff --git a/CPU9bits_tb_behav.wcfg b/CPU9bits_tb_behav.wcfg index 5f82acf..40abd4d 100644 --- a/CPU9bits_tb_behav.wcfg +++ b/CPU9bits_tb_behav.wcfg @@ -11,15 +11,15 @@ - - - + + + - + - + clk clk @@ -35,133 +35,217 @@ instr[8:0] instr[8:0] - + BINARYRADIX AddrOut[8:0] AddrOut[8:0] + UNSIGNEDDECRADIX - + + Registers label - r0_out[8:0] - r0_out[8:0] - RegisterA + + + label + r0_out[8:0] + r0_out[8:0] + RegisterA + UNSIGNEDDECRADIX + + + label + r1_out[8:0] + r1_out[8:0] + RegisterB + UNSIGNEDDECRADIX + + + label + r2_out[8:0] + r2_out[8:0] + RegisterC + UNSIGNEDDECRADIX + + + label + r3_out[8:0] + r3_out[8:0] + RegisterD + UNSIGNEDDECRADIX + - + + Banks label - r1_out[8:0] - r1_out[8:0] - RegisterB + + + label + r0_out[8:0] + r0_out[8:0] + Bank0 + UNSIGNEDDECRADIX + + + label + r1_out[8:0] + r1_out[8:0] + Bank1 + UNSIGNEDDECRADIX + + + label + r2_out[8:0] + r2_out[8:0] + Bank2 + UNSIGNEDDECRADIX + + + label + r3_out[8:0] + r3_out[8:0] + Bank3 + UNSIGNEDDECRADIX + - + + Divider label - r2_out[8:0] - r2_out[8:0] - RegisterC - - - label - r3_out[8:0] - r3_out[8:0] - RegisterD - - - label - r0_out[8:0] - r0_out[8:0] - Bank0 - - - label - r1_out[8:0] - r1_out[8:0] - Bank1 - - - label - r2_out[8:0] - r2_out[8:0] - Bank2 - - - label - r3_out[8:0] - r3_out[8:0] - Bank3 - - - switch - switch - - - writeEnable - writeEnable - - - address[8:0] - address[8:0] - - - writeData[8:0] - writeData[8:0] label - memory[15:0][8:0] - memory[15:0][8:0] + memory[23:0][8:0] + memory[23:0][8:0] Data Memory + UNSIGNEDDECRADIX + + [23][8:0] + [23][8:0] + UNSIGNEDDECRADIX + + + [22][8:0] + [22][8:0] + UNSIGNEDDECRADIX + + + [21][8:0] + [21][8:0] + UNSIGNEDDECRADIX + + + [20][8:0] + [20][8:0] + UNSIGNEDDECRADIX + + + [19][8:0] + [19][8:0] + UNSIGNEDDECRADIX + + + [18][8:0] + [18][8:0] + UNSIGNEDDECRADIX + + + [17][8:0] + [17][8:0] + UNSIGNEDDECRADIX + + + [16][8:0] + [16][8:0] + UNSIGNEDDECRADIX + + + [15][8:0] + [15][8:0] + UNSIGNEDDECRADIX + + + [14][8:0] + [14][8:0] + UNSIGNEDDECRADIX + + + [13][8:0] + [13][8:0] + UNSIGNEDDECRADIX + + + [12][8:0] + [12][8:0] + UNSIGNEDDECRADIX + + + [11][8:0] + [11][8:0] + UNSIGNEDDECRADIX + + + [10][8:0] + [10][8:0] + UNSIGNEDDECRADIX + + + [9][8:0] + [9][8:0] + UNSIGNEDDECRADIX + + + [8][8:0] + [8][8:0] + UNSIGNEDDECRADIX + + + [7][8:0] + [7][8:0] + UNSIGNEDDECRADIX + + + [6][8:0] + [6][8:0] + UNSIGNEDDECRADIX + + + [5][8:0] + [5][8:0] + UNSIGNEDDECRADIX + + + [4][8:0] + [4][8:0] + UNSIGNEDDECRADIX + + + [3][8:0] + [3][8:0] + UNSIGNEDDECRADIX + + + [2][8:0] + [2][8:0] + UNSIGNEDDECRADIX + + + [1][8:0] + [1][8:0] + UNSIGNEDDECRADIX + + + [0][8:0] + [0][8:0] + UNSIGNEDDECRADIX + readData[8:0] readData[8:0] - - operand0[8:0] - operand0[8:0] - - - result_K[8:0] - result_K[8:0] - - - op_idx - op_idx - AddrIn[8:0] AddrIn[8:0] - - progC_out[8:0] - progC_out[8:0] - - - result_m[8:0] - result_m[8:0] - - - cout - cout - - - result[8:0] - result[8:0] - - - switch[3:0] - switch[3:0] - - - K[8:0] - K[8:0] - - - out[8:0] - out[8:0] - - - FU[2:0] - FU[2:0] - diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 5dc712a..68c22ae 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -17,7 +17,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -25,49 +25,52 @@ This means code written to parse this file will need to be revisited each subseq - - - - + + + + + - + - - - - - + + + + + - + - + - + - + - + + + - - + + - + - + - - + + @@ -77,104 +80,115 @@ This means code written to parse this file will need to be revisited each subseq + - + - + - + - + - + - + + - - + + + - + + - + - + - + - - + + - - + + - + + - + + - + - + - + - + + + - - - + + + - - - + + + - + + + + - + - +
diff --git a/lab2CA.runs/.jobs/vrs_config_43.xml b/lab2CA.runs/.jobs/vrs_config_43.xml new file mode 100644 index 0000000..99236b3 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_43.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_44.xml b/lab2CA.runs/.jobs/vrs_config_44.xml new file mode 100644 index 0000000..b013dc9 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_44.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/lab2CA.runs/impl_1/CPU9bits_tb.vdi b/lab2CA.runs/impl_1/CPU9bits_tb.vdi new file mode 100644 index 0000000..b2588e7 --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_tb.vdi @@ -0,0 +1,173 @@ +#----------------------------------------------------------- +# Vivado v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sun Mar 24 18:38:44 2019 +# Process ID: 13064 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1 +# Command line: vivado.exe -log CPU9bits_tb.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb.vdi +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source CPU9bits_tb.tcl -notrace +Command: link_design -top CPU9bits_tb -part xc7k160tifbg484-2L +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Project 1-479] Netlist was created with Vivado 2018.3 +INFO: [Device 21-403] Loading part xc7k160tifbg484-2L +INFO: [Project 1-570] Preparing netlist for logic optimization +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 579.477 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 579.477 ; gain = 327.758 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 583.891 ; gain = 4.082 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: f67b9b0d + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1077.012 ; gain = 493.121 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: f67b9b0d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1167.297 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: f67b9b0d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1167.297 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: f67b9b0d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1167.297 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: f67b9b0d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1167.297 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: f67b9b0d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1167.297 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: f67b9b0d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1167.297 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: f67b9b0d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.062 . Memory (MB): peak = 1167.297 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: f67b9b0d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1167.297 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: f67b9b0d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: f67b9b0d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1167.297 ; gain = 587.559 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx +Command: report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1192.641 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1192.641 ; gain = 0.328 +Phase 1 Placer Initialization | Checksum: 00000000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1192.641 ; gain = 0.328 +ERROR: [Place 30-494] The design is empty +Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports. +Ending Placer Task | Checksum: 00000000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1192.641 ; gain = 0.328 +INFO: [Common 17-83] Releasing license: Implementation +36 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered. +place_design failed +ERROR: [Common 17-69] Command failed: Placer could not place all instances +INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 18:39:16 2019... diff --git a/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb b/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb differ diff --git a/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt b/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt new file mode 100644 index 0000000..f3fdc2b --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Sun Mar 24 18:39:15 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx +| Design : CPU9bits_tb +| Device : xc7k160tifbg484-2L +| Speed File : -2L +| Design State : Fully Routed +------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp b/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp new file mode 100644 index 0000000..a888ad7 Binary files /dev/null and b/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp differ diff --git a/lab2CA.runs/impl_1/init_design.pb b/lab2CA.runs/impl_1/init_design.pb new file mode 100644 index 0000000..8dac2cb Binary files /dev/null and b/lab2CA.runs/impl_1/init_design.pb differ diff --git a/lab2CA.runs/impl_1/opt_design.pb b/lab2CA.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..7b26f1d Binary files /dev/null and b/lab2CA.runs/impl_1/opt_design.pb differ diff --git a/lab2CA.runs/impl_1/place_design.pb b/lab2CA.runs/impl_1/place_design.pb new file mode 100644 index 0000000..8278661 Binary files /dev/null and b/lab2CA.runs/impl_1/place_design.pb differ diff --git a/lab2CA.runs/impl_1/route_design.pb b/lab2CA.runs/impl_1/route_design.pb new file mode 100644 index 0000000..921c9c1 Binary files /dev/null and b/lab2CA.runs/impl_1/route_design.pb differ diff --git a/lab2CA.runs/impl_1/vivado.jou b/lab2CA.runs/impl_1/vivado.jou new file mode 100644 index 0000000..9cf4c69 --- /dev/null +++ b/lab2CA.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sun Mar 24 18:38:44 2019 +# Process ID: 13064 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1 +# Command line: vivado.exe -log CPU9bits_tb.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb.vdi +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source CPU9bits_tb.tcl -notrace diff --git a/lab2CA.runs/impl_1/vivado.pb b/lab2CA.runs/impl_1/vivado.pb new file mode 100644 index 0000000..b155e40 --- /dev/null +++ b/lab2CA.runs/impl_1/vivado.pb @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git a/lab2CA.runs/synth_1/CPU9bits_tb.dcp b/lab2CA.runs/synth_1/CPU9bits_tb.dcp new file mode 100644 index 0000000..21db77f Binary files /dev/null and b/lab2CA.runs/synth_1/CPU9bits_tb.dcp differ diff --git a/lab2CA.runs/synth_1/CPU9bits_tb.tcl b/lab2CA.runs/synth_1/CPU9bits_tb.tcl new file mode 100644 index 0000000..0ff5867 --- /dev/null +++ b/lab2CA.runs/synth_1/CPU9bits_tb.tcl @@ -0,0 +1,63 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param synth.incrementalSynthesisCache C:/Users/willi/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-18452-WM-G75VW/incrSyn +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 +create_project -in_memory -part xc7k160tifbg484-2L + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/wt} [current_project] +set_property parent.project_path {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo {c:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/ip} [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v} + {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v} +} +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top CPU9bits -part xc7k160tifbg484-2L + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef CPU9bits.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/lab2CA.runs/synth_1/CPU9bits_tb.vds b/lab2CA.runs/synth_1/CPU9bits_tb.vds new file mode 100644 index 0000000..db1748c --- /dev/null +++ b/lab2CA.runs/synth_1/CPU9bits_tb.vds @@ -0,0 +1,951 @@ +#----------------------------------------------------------- +# Vivado v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sun Mar 24 18:28:31 2019 +# Process ID: 5228 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1 +# Command line: vivado.exe -log CPU9bits_tb.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.vds +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source CPU9bits_tb.tcl -notrace +Command: synth_design -top CPU9bits_tb -part xc7k160tifbg484-2L +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 14244 +WARNING: [Synth 8-1958] event expressions must result in a singular type [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85] +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 372.199 ; gain = 114.445 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'CPU9bits_tb' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:172] +WARNING: [Synth 8-85] always block has no event control specified [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:179] +INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] +INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] +INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] +INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] +WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85] +WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85] +INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] +INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] +INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268] +INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] +INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777] +INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777] +INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412] +INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407] +INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] +INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] +INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] +INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] +INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] +INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] +INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342] +INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336] +INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] +INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] +INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311] +INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376] +INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687] +INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687] +INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376] +INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311] +INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724] +INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724] +INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643] +INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643] +INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] +INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] +INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] +INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] +INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] +INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] +INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] +INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] +INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541] +INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] +WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] +WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] +WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] +WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] +INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] +INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17] +INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] +INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996] +INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996] +INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356] +INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] +INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] +INFO: [Synth 8-6155] done synthesizing module 'CPU9bits_tb' (28#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:172] +WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0] +WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0] +WARNING: [Synth 8-3331] design shift_left has unconnected port A[8] +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:01:51 ; elapsed = 00:01:54 . Memory (MB): peak = 2338.125 ; gain = 2080.371 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:02:04 ; elapsed = 00:02:09 . Memory (MB): peak = 2338.125 ; gain = 2080.371 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tifbg484-2L +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:02:04 ; elapsed = 00:02:09 . Memory (MB): peak = 2338.125 ; gain = 2080.371 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7k160tifbg484-2L +INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +INFO: [Synth 8-5546] ROM "memory_reg[511]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[510]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[509]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[508]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[507]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[506]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[505]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[504]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[503]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[502]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[501]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[500]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[499]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[498]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[497]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[496]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[495]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[494]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[493]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[492]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[491]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[490]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[489]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[488]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[487]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[486]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[485]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[484]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[483]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[482]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[481]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[480]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[479]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[478]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[477]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[476]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[475]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[474]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[473]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[472]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[471]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[470]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[469]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[468]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[467]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[466]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[465]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[464]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[463]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[462]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[461]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[460]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[459]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[458]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[457]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[456]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[455]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[454]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[453]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[452]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[451]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[450]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[449]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[448]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[447]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[446]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[445]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[444]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[443]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[442]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[441]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[440]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[439]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[438]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[437]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[436]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[435]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[434]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[433]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[432]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[431]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[430]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[429]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[428]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[427]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[426]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[425]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[424]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[423]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[422]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[421]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[420]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[419]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[418]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[417]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[416]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[415]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[414]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[413]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[412]" won't be mapped to RAM because it is too sparse +INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:202] +WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[511]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[510]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[509]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[508]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[507]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[506]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[505]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[504]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[503]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[502]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[501]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[500]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[499]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[498]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[497]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[496]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[495]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[494]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[493]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[492]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[491]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[490]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[489]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[488]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[487]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[486]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[485]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[484]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[483]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[482]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[481]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[480]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[479]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[478]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[477]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[476]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[475]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[474]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[473]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[472]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[471]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[470]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[469]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[468]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[467]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[466]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[465]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[464]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[463]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[462]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[461]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[460]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[459]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[458]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[457]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[456]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[455]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[454]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[453]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[452]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[451]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[450]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[449]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[448]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[447]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[446]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[445]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[444]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[443]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[442]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[441]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[440]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[439]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[438]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[437]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[436]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[435]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[434]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[433]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[432]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[431]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[430]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[429]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[428]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[427]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[426]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[425]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[424]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[423]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[422]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[421]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[420]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[419]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[418]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[417]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[416]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[415]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[414]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] +INFO: [Common 17-14] Message 'Synth 8-327' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:04:25 ; elapsed = 00:04:33 . Memory (MB): peak = 2906.012 ; gain = 2648.258 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'CPU9bits0/SE1' (sign_extend_3bit) to 'CPU9bits0/SE3' + +Report RTL Partitions: ++------+----------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++------+----------------+------------+----------+ +|1 |dataMemory__GB0 | 1| 2378380| +|2 |CPU9bits__GC0 | 1| 1169| ++------+----------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 162 ++---Registers : + 9 Bit Registers := 9 ++---Muxes : + 2 Input 9 Bit Muxes := 520 + 8 Input 9 Bit Muxes := 1 + 4 Input 9 Bit Muxes := 4 + 2 Input 4 Bit Muxes := 2 + 4 Input 4 Bit Muxes := 2 + 16 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 2 + 16 Input 3 Bit Muxes := 1 + 16 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 513 + 16 Input 1 Bit Muxes := 8 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module dataMemory +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 512 + 2 Input 1 Bit Muxes := 512 +Module instructionMemory +Detailed RTL Component Info : ++---Muxes : + 8 Input 9 Bit Muxes := 1 +Module decoder__1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 4 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 +Module register__8 +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 +Module register__7 +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 +Module register__6 +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 +Module register__5 +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 +Module mux_4_1__3 +Detailed RTL Component Info : ++---Muxes : + 4 Input 9 Bit Muxes := 1 +Module mux_4_1__2 +Detailed RTL Component Info : ++---Muxes : + 4 Input 9 Bit Muxes := 1 +Module decoder +Detailed RTL Component Info : ++---Muxes : + 2 Input 4 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 +Module register__2 +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 +Module register__3 +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 +Module register__4 +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 +Module register +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 +Module mux_4_1__1 +Detailed RTL Component Info : ++---Muxes : + 4 Input 9 Bit Muxes := 1 +Module mux_4_1 +Detailed RTL Component Info : ++---Muxes : + 4 Input 9 Bit Muxes := 1 +Module register__1 +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 +Module add_1bit__44 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__43 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__42 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__41 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__40 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__39 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__38 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__37 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__36 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module mux_2_1__1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 1 +Module add_1bit__35 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__34 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__33 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__32 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__31 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__30 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__29 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__28 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__27 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__62 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__61 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__60 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__59 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__58 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__57 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__56 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__55 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__54 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__26 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__25 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__24 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__23 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__22 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__21 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__20 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__19 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__18 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__80 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__79 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__78 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__77 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__76 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__75 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__74 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__73 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__72 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__71 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__70 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__69 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__68 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__67 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__66 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__65 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__64 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__63 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module ControlUnit +Detailed RTL Component Info : ++---Muxes : + 16 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 2 + 16 Input 3 Bit Muxes := 1 + 16 Input 2 Bit Muxes := 1 + 16 Input 1 Bit Muxes := 8 +Module add_1bit__53 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__52 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__51 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__50 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__49 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__48 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__47 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__46 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__45 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module mux_2_1__2 +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 1 +Module add_1bit__17 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__16 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__15 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__14 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__13 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__12 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__11 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__10 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__9 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module mux_2_1__3 +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 1 +Module mux_2_1__4 +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 1 +Module bit1_mux_2_1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module add_1bit__1 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__2 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__3 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__4 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__5 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__6 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__7 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit__8 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module add_1bit +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module mux_2_1__5 +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 1 +Module mux_2_1__6 +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 1 +Module mux_2_1__7 +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 1 +Module mux_2_1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[0]' (LD) to 'CPU9bits0i_1/iM/readData_reg[2]' +INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[8]' (LD) to 'CPU9bits0i_1/iM/readData_reg[6]' +INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[2]' (LD) to 'CPU9bits0i_1/iM/readData_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\iM/readData_reg[4] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++-+-----+------+ +| |Cell |Count | ++-+-----+------+ ++-+-----+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 0| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 526 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 +Synthesis Optimization Complete : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3340.348 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +177 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:09:36 ; elapsed = 00:10:01 . Memory (MB): peak = 3340.348 ; gain = 3090.086 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 3340.348 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 18:38:37 2019... diff --git a/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb b/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb new file mode 100644 index 0000000..68f663d Binary files /dev/null and b/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb differ diff --git a/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt b/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt new file mode 100644 index 0000000..eb83468 --- /dev/null +++ b/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt @@ -0,0 +1,183 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Sun Mar 24 16:58:30 2019 +| Host : WM-G75VW running 64-bit major release (build 9200) +| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb +| Design : CPU9bits +| Device : 7k160tifbg484-2L +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 578 | 0 | 101400 | 0.57 | +| LUT as Logic | 578 | 0 | 101400 | 0.57 | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 235 | 0 | 202800 | 0.12 | +| Register as Flip Flop | 81 | 0 | 202800 | 0.04 | +| Register as Latch | 154 | 0 | 202800 | 0.08 | +| F7 Muxes | 6 | 0 | 50700 | 0.01 | +| F8 Muxes | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 154 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 81 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 325 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | +| RAMB18 | 0 | 0 | 650 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 3 | 0 | 285 | 1.05 | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 275 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 1 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 2 | 0 | 32 | 6.25 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT6 | 439 | LUT | +| LDCE | 154 | Flop & Latch | +| FDRE | 81 | Flop & Latch | +| LUT5 | 69 | LUT | +| LUT4 | 51 | LUT | +| LUT3 | 50 | LUT | +| LUT2 | 45 | LUT | +| MUXF7 | 6 | MuxFx | +| IBUF | 2 | IO | +| BUFG | 2 | Clock | +| OBUF | 1 | IO | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/lab2CA.runs/synth_1/htr.txt b/lab2CA.runs/synth_1/htr.txt index 641d4cb..b59ff1f 100644 --- a/lab2CA.runs/synth_1/htr.txt +++ b/lab2CA.runs/synth_1/htr.txt @@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status. REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. REM -vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl +vivado -log CPU9bits_tb.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl diff --git a/lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb.tcl index 1094e45..8243a08 100644 --- a/lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb.tcl @@ -8,4 +8,4 @@ if { [string length $curr_wave] == 0 } { } } -run 1000ns +run 100000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11344.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_11344.backup.jou new file mode 100644 index 0000000..1dd23b5 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_11344.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sun Mar 24 17:25:06 2019 +# Process ID: 11344 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou new file mode 100644 index 0000000..1b4851e --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sun Mar 24 17:34:31 2019 +# Process ID: 12056 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_13536.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_13536.backup.jou new file mode 100644 index 0000000..c58850d --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_13536.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sun Mar 24 17:24:25 2019 +# Process ID: 13536 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index 2d750dd..175ab93 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xelab.pb and b/lab2CA.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl index 0ede6bd..3d5902e 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl @@ -1,10 +1,10 @@ -webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/ +webtalk_init -webtalk_dir C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Sun Mar 24 17:04:55 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Sun Mar 24 19:25:23 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" -webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" @@ -12,21 +12,21 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "f67bb5263bf851bf9c1beaa84fe1017c" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "111" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "48" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" -webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2395 MHz" -context "user_environment" webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment" webtalk_register_client -client xsim webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" -webtalk_add_data -client xsim -key runtime -value "870 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "50020 ns" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "6432_KB" -context "xsim\\usage" -webtalk_transmit -clientid 2385566918 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key Simulation_Time -value "0.30_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "9684_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3966238694 -regid "" -xml C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem index b25dad4..a211095 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml index 97e005a..82b1cd5 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -1,14 +1,14 @@ - +
- + - + @@ -34,9 +34,9 @@
- - - + + +
diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl index 5b4c6e5..1155c64 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl @@ -1,6 +1,6 @@ webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Sat Mar 16 14:16:46 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Sun Mar 24 17:39:03 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" @@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "19" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "22" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" @@ -26,7 +26,7 @@ webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" webtalk_add_data -client xsim -key runtime -value "60 ns" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "6112_KB" -context "xsim\\usage" -webtalk_transmit -clientid 2514989005 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6128_KB" -context "xsim\\usage" +webtalk_transmit -clientid 918939418 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem index acd1f53..a201b29 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml index 0922624..0503ca5 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -1,14 +1,14 @@ - +
- + - + @@ -34,9 +34,9 @@
- - - + + +
diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl index b491427..898bf47 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl @@ -1,6 +1,6 @@ webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Sat Mar 16 13:18:24 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Sun Mar 24 17:39:06 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" @@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "16" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" @@ -24,9 +24,9 @@ webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "us webtalk_register_client -client xsim webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" -webtalk_add_data -client xsim -key runtime -value "40 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "45 ns" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "6108_KB" -context "xsim\\usage" -webtalk_transmit -clientid 3866550317 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6124_KB" -context "xsim\\usage" +webtalk_transmit -clientid 643401725 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/xsim.mem index e849de9..2a447a4 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/xsim.mem and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/xsim.mem differ diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v index e16b212..f04a2f4 100644 --- a/lab2CA.srcs/sources_1/new/CPU9bits.v +++ b/lab2CA.srcs/sources_1/new/CPU9bits.v @@ -190,7 +190,7 @@ module CPU9bits_tb(); reset = 1'b1; #10 reset = 1'b0; - #850 + #50000 diff --git a/lab2CA.srcs/sources_1/new/dataMemory.v b/lab2CA.srcs/sources_1/new/dataMemory.v index c35f3d9..7c55a60 100644 --- a/lab2CA.srcs/sources_1/new/dataMemory.v +++ b/lab2CA.srcs/sources_1/new/dataMemory.v @@ -6,27 +6,10 @@ module dataMemory( output reg [8:0] readData ); - reg [8:0] memory [15:0]; + reg [8:0] memory [23:0]; initial begin // String Compare Memory - memory[0] <= 9'b000000100; - memory[1] <= 9'b000001000; - memory[2] <= 9'b000001100; - memory[3] <= 9'b010101010; - memory[4] <= 9'b000001111; - memory[5] <= 9'b000000100; - memory[6] <= 9'b000000011; - memory[7] <= 9'b000000111; - memory[8] <= 9'b000001111; - memory[9] <= 9'b000000100; - memory[10] <= 9'b000000010; - memory[11] <= 9'b000000000; - memory[12] <= 9'b000000000; - memory[13] <= 9'b000000000; - memory[14] <= 9'b000000000; - memory[15] <= 9'b000000000; -// // String Compare Memory // memory[0] <= 9'b000000100; // memory[1] <= 9'b000001000; // memory[2] <= 9'b000001100; @@ -34,7 +17,7 @@ module dataMemory( // memory[4] <= 9'b000001111; // memory[5] <= 9'b000000100; // memory[6] <= 9'b000000011; -// memory[7] <= 9'b000000000; +// memory[7] <= 9'b000000111; // memory[8] <= 9'b000001111; // memory[9] <= 9'b000000100; // memory[10] <= 9'b000000010; @@ -46,8 +29,8 @@ module dataMemory( // Bubble Sort Initial Memory - memory[0] <= 9'b000011000; - memory[1] <= 9'b000000000; + memory[0] <= 9'b000010110; + memory[1] <= 9'b000100010; memory[2] <= 9'b000100000; memory[3] <= 9'b010001000; memory[4] <= 9'b010010000; diff --git a/lab2CA.srcs/sources_1/new/instructionMemory.v b/lab2CA.srcs/sources_1/new/instructionMemory.v index 047693d..d0b7019 100644 --- a/lab2CA.srcs/sources_1/new/instructionMemory.v +++ b/lab2CA.srcs/sources_1/new/instructionMemory.v @@ -34,57 +34,16 @@ module instructionMemory( //String Compare - memory[0] <= 9'b000000000; - memory[1] <= 9'b010000000; - memory[2] <= 9'b010001000; - memory[3] <= 9'b010010000; - memory[4] <= 9'b010011000; - memory[5] <= 9'b000100000; - memory[6] <= 9'b011001001; - memory[7] <= 9'b000101010; - memory[8] <= 9'b011010010; - memory[9] <= 9'b000110100; - memory[10] <= 9'b011011011; - memory[11] <= 9'b000111110; - memory[12] <= 9'b101010000; - memory[13] <= 9'b101000010; - memory[14] <= 9'b101001100; - memory[15] <= 9'b101011110; //ends initialization - memory[16] <= 9'b101000011; - memory[17] <= 9'b101001101; - memory[18] <= 9'b000110000; - memory[19] <= 9'b000111010; - memory[20] <= 9'b110010001; - memory[21] <= 9'b100100001; - memory[22] <= 9'b100110000; - memory[23] <= 9'b110011001; - memory[24] <= 9'b100100001; - memory[25] <= 9'b100101101; - memory[26] <= 9'b011000001; - memory[27] <= 9'b011001001; - memory[28] <= 9'b101000010; - memory[29] <= 9'b101001100; - memory[30] <= 9'b010110111; - memory[31] <= 9'b110010001; - memory[32] <= 9'b101110001; - memory[33] <= 9'b101000001; - memory[34] <= 9'b101001111; - memory[35] <= 9'b001001000; - memory[36] <= 9'b011000001; - memory[37] <= 9'b101000000; - memory[38] <= 9'b101110111; - memory[39] <= 9'b000000000; - -// memory[0] <= 9'b000000000; -// memory[1] <= 9'b010000000; -// memory[2] <= 9'b010001000; -// memory[3] <= 9'b010010000; -// memory[4] <= 9'b010011000; -// memory[5] <= 9'b000100000; -// memory[6] <= 9'b011001001; -// memory[7] <= 9'b000101010; -// memory[8] <= 9'b011010010; -// memory[9] <= 9'b000110100; +// memory[0] <= 9'b000000000; +// memory[1] <= 9'b010000000; +// memory[2] <= 9'b010001000; +// memory[3] <= 9'b010010000; +// memory[4] <= 9'b010011000; +// memory[5] <= 9'b000100000; +// memory[6] <= 9'b011001001; +// memory[7] <= 9'b000101010; +// memory[8] <= 9'b011010010; +// memory[9] <= 9'b000110100; // memory[10] <= 9'b011011011; // memory[11] <= 9'b000111110; // memory[12] <= 9'b101010000; @@ -107,13 +66,13 @@ module instructionMemory( // memory[29] <= 9'b101001100; // memory[30] <= 9'b010110111; // memory[31] <= 9'b110010001; -// memory[32] <= 9'b101110010; -// memory[33] <= 9'b101000000; -// memory[34] <= 9'b101001110; +// memory[32] <= 9'b101110001; +// memory[33] <= 9'b101000001; +// memory[34] <= 9'b101001111; // memory[35] <= 9'b001001000; // memory[36] <= 9'b011000001; // memory[37] <= 9'b101000000; -// memory[38] <= 9'b101111000; +// memory[38] <= 9'b101110111; // memory[39] <= 9'b000000000; @@ -136,8 +95,8 @@ module instructionMemory( // Check if at the end of the array // EndChk: memory[12] <= 9'b101001001; // bankl $b, $0 - memory[13] <= 9'b011101000; // slt $b, $a - memory[14] <= 9'b110001010; // beq $b, JSC + memory[13] <= 9'b011101000; // slt $b, $a + memory[14] <= 9'b110001001; // beq $b, JSC memory[15] <= 9'b100100001; // jf LoadNext // JSC: memory[16] <= 9'b100110100; // jf SwapChk @@ -150,8 +109,8 @@ module instructionMemory( memory[21] <= 9'b000111010; // lb $d, $b // Compare loaded values to see if they need to be swapped memory[22] <= 9'b101011110; // banks $d, $3 - memory[23] <= 9'b011111100; // slt $d, $c - memory[24] <= 9'b110011010; // beq $d, JI + memory[23] <= 9'b011111100; // slt $d, $c + memory[24] <= 9'b110011001; // beq $d, JI memory[25] <= 9'b100100001; // jf Swap // JI: memory[26] <= 9'b101110010; // jb Inc @@ -170,7 +129,7 @@ module instructionMemory( // Check to see if any swaps have been made in the last iteration // SwapChk: memory[37] <= 9'b101001011; // bankl $b, $1 - memory[38] <= 9'b110001001; // beq $b, JE + memory[38] <= 9'b110001001; // beq $b, JE memory[39] <= 9'b100100001; // jf Reset // JE: memory[40] <= 9'b100100011; // jf End @@ -184,69 +143,69 @@ module instructionMemory( // Binary Search - memory[0] <= 9'b000000000; - memory[1] <= 9'b000000000; - memory[2] <= 9'b000000000; - memory[3] <= 9'b000000000; - memory[4] <= 9'b000000000; - memory[5] <= 9'b011001011; //addi R1, 3 (N = 3) - memory[6] <= 9'b011001011; //addi R1, 3 (N = 3) - memory[7] <= 9'b011001011; //addi R1, 3 (N = 3) - memory[8] <= 9'b011001011; //addi R1, 3 (N = 3) - memory[9] <= 9'b011001011; //addi R1, 3 (N = 3) - memory[10] <= 9'b011011010; //addi R3, 2 (inputAddr = 2) - memory[11] <= 9'b000111110; //lb R3, R3 - memory[12] <= 9'b101011010; //banks R3, 1 - memory[13] <= 9'b011001011; //addi R1, 3 (N = 3) - memory[14] <= 9'b101000000; //loop: banks R0, 0 - memory[15] <= 9'b011100010; //slt R0, R1 - memory[16] <= 9'b110000001; //beq R0, Exit - memory[17] <= 9'b100100001; //j Skip0 - memory[18] <= 9'b100101111; //Exit: j Loose - memory[19] <= 9'b101000001; //Skip0: bankl R0, 0 - memory[20] <= 9'b010110000; //add R2, R0 - memory[21] <= 9'b010110010; //add R2, R1 - memory[22] <= 9'b111110001; //srl R2 - memory[23] <= 9'b101011011; //bankl R3,1 - memory[24] <= 9'b010111100; //add R3, R2 - memory[25] <= 9'b101001100; //banks R1, 2 - memory[26] <= 9'b000100110; //lb R0, R3 - memory[27] <= 9'b010001000; //zero R1 - memory[28] <= 9'b011001001; //addi R1, 1 (numAddr = 1) - memory[29] <= 9'b000101010; //lb R1, R1 - memory[30] <= 9'b100100001; //j SkipU - memory[31] <= 9'b101110010; //j TransLoop - memory[32] <= 9'b101010110; //SkipU: banks R2, 3 - memory[33] <= 9'b100100001; //j SkipD - memory[34] <= 9'b100110111; //j TransLoose - memory[35] <= 9'b010010000; //SkipD: zero R2 - memory[36] <= 9'b010110010; //add R2, R1 - memory[37] <= 9'b010101001; //sub R1, R0 - memory[38] <= 9'b110001001; //beq R1, Go1 - memory[39] <= 9'b100100001; //j Skip1 - memory[40] <= 9'b100101001; //Go1: j Win - memory[41] <= 9'b010001000; //Skip1: zero R1 - memory[42] <= 9'b010101100; //add R1, R2 - memory[43] <= 9'b011100010; //slt R0, R1 - memory[44] <= 9'b110000001; //beq R0, Go2 - memory[45] <= 9'b100100110; //j Skip2 - memory[46] <= 9'b010000000; //Go2: zero R0 - memory[47] <= 9'b011000001; //addi R0, 1 - memory[48] <= 9'b101001111; //bankl R1,3 - memory[49] <= 9'b010100010; //add R0, R1 - memory[50] <= 9'b101001101; //bankl R1,2 - memory[51] <= 9'b101110101; //j loop - memory[52] <= 9'b010001000; //Skip2: zero R1 - memory[53] <= 9'b011001111; //addi R1, -1 - memory[54] <= 9'b101000111; //bankl R0, 3 - memory[55] <= 9'b010101000; //add R1, R0 - memory[56] <= 9'b101000001; //bankl R0,0 - memory[57] <= 9'b101111011; //j loop - memory[58] <= 9'b010000000; //Loose: zero R0 - memory[59] <= 9'b011000111; //addi R0, -1 - memory[60] <= 9'b101000110; //banks R0, 3 - memory[61] <= 9'b100100000; //j Win - memory[62] <= 9'b000000000; //Win: halt +// memory[0] <= 9'b000000000; +// memory[1] <= 9'b000000000; +// memory[2] <= 9'b000000000; +// memory[3] <= 9'b000000000; +// memory[4] <= 9'b000000000; +// memory[5] <= 9'b011001011; //addi R1, 3 (N = 3) +// memory[6] <= 9'b011001011; //addi R1, 3 (N = 3) +// memory[7] <= 9'b011001011; //addi R1, 3 (N = 3) +// memory[8] <= 9'b011001011; //addi R1, 3 (N = 3) +// memory[9] <= 9'b011001011; //addi R1, 3 (N = 3) +// memory[10] <= 9'b011011010; //addi R3, 2 (inputAddr = 2) +// memory[11] <= 9'b000111110; //lb R3, R3 +// memory[12] <= 9'b101011010; //banks R3, 1 +// memory[13] <= 9'b011001011; //addi R1, 3 (N = 3) +// memory[14] <= 9'b101000000; //loop: banks R0, 0 +// memory[15] <= 9'b011100010; //slt R0, R1 +// memory[16] <= 9'b110000001; //beq R0, Exit +// memory[17] <= 9'b100100001; //j Skip0 +// memory[18] <= 9'b100101111; //Exit: j Loose +// memory[19] <= 9'b101000001; //Skip0: bankl R0, 0 +// memory[20] <= 9'b010110000; //add R2, R0 +// memory[21] <= 9'b010110010; //add R2, R1 +// memory[22] <= 9'b111110001; //srl R2 +// memory[23] <= 9'b101011011; //bankl R3,1 +// memory[24] <= 9'b010111100; //add R3, R2 +// memory[25] <= 9'b101001100; //banks R1, 2 +// memory[26] <= 9'b000100110; //lb R0, R3 +// memory[27] <= 9'b010001000; //zero R1 +// memory[28] <= 9'b011001001; //addi R1, 1 (numAddr = 1) +// memory[29] <= 9'b000101010; //lb R1, R1 +// memory[30] <= 9'b100100001; //j SkipU +// memory[31] <= 9'b101110010; //j TransLoop +// memory[32] <= 9'b101010110; //SkipU: banks R2, 3 +// memory[33] <= 9'b100100001; //j SkipD +// memory[34] <= 9'b100110111; //j TransLoose +// memory[35] <= 9'b010010000; //SkipD: zero R2 +// memory[36] <= 9'b010110010; //add R2, R1 +// memory[37] <= 9'b010101001; //sub R1, R0 +// memory[38] <= 9'b110001001; //beq R1, Go1 +// memory[39] <= 9'b100100001; //j Skip1 +// memory[40] <= 9'b100101001; //Go1: j Win +// memory[41] <= 9'b010001000; //Skip1: zero R1 +// memory[42] <= 9'b010101100; //add R1, R2 +// memory[43] <= 9'b011100010; //slt R0, R1 +// memory[44] <= 9'b110000001; //beq R0, Go2 +// memory[45] <= 9'b100100110; //j Skip2 +// memory[46] <= 9'b010000000; //Go2: zero R0 +// memory[47] <= 9'b011000001; //addi R0, 1 +// memory[48] <= 9'b101001111; //bankl R1,3 +// memory[49] <= 9'b010100010; //add R0, R1 +// memory[50] <= 9'b101001101; //bankl R1,2 +// memory[51] <= 9'b101110101; //j loop +// memory[52] <= 9'b010001000; //Skip2: zero R1 +// memory[53] <= 9'b011001111; //addi R1, -1 +// memory[54] <= 9'b101000111; //bankl R0, 3 +// memory[55] <= 9'b010101000; //add R1, R0 +// memory[56] <= 9'b101000001; //bankl R0,0 +// memory[57] <= 9'b101111011; //j loop +// memory[58] <= 9'b010000000; //Loose: zero R0 +// memory[59] <= 9'b011000111; //addi R0, -1 +// memory[60] <= 9'b101000110; //banks R0, 3 +// memory[61] <= 9'b100100000; //j Win +// memory[62] <= 9'b000000000; //Win: halt end diff --git a/lab2CA.xpr b/lab2CA.xpr index 64c236e..b288b98 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - +