Hopefully this is right. Vivado tells me it's fine, then minutes later not...

2019-03-12 21:21:52 -04:00
parent 4a462752e9
commit 76bc5e006e
2 changed files with 38 additions and 3 deletions
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -48,12 +48,19 @@ module ALU(
    shift_right_arithmetic sra(
        .A(operand0),
        .B(result_H));
-    // I (1000)
+    // I (1000) - NOT
    not_9bit not0(
        .A(operand0),
        .B(result_I));
-    // J (1001)
-    // K (1010)
+    // J (1001) - Less Than
+    less_than less0(
+        .A(operand0),
+        .B(operand1),
+        .C(result_J));
+    // K (1010) - Zero
+    zero zero0(
+        .A(operand0),
+        .B(result_K));
    // L (1011)
    // M (1100)
    // N (1101)