Hopefully this is right. Vivado tells me it's fine, then minutes later not...

lab2CA.srcs/sources_1/new/ALU.v

@@ -48,12 +48,19 @@ module ALU(
     shift_right_arithmetic sra(
         .A(operand0),
         .B(result_H));
-    // I (1000)
+    // I (1000) - NOT
     not_9bit not0(
         .A(operand0),
         .B(result_I));
-    // J (1001)
+    // J (1001) - Less Than
-    // K (1010)
+    less_than less0(
+        .A(operand0),
+        .B(operand1),
+        .C(result_J));
+    // K (1010) - Zero
+    zero zero0(
+        .A(operand0),
+        .B(result_K));
     // L (1011)
     // M (1100)
     // N (1101)

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -271,6 +271,22 @@ module gen_clock();
     end
 endmodule
 
+module less_than(
+    input wire [8:0] A,B,
+    output wire [8:0] C);
+    
+    wire [8:0] D;
+    
+    sub_9bit sub0(
+        .A(A),
+        .B(B),
+        .C(D));
+        
+    assign C = {8'b00000000,D[8]};
+    // 1 if A is less than B
+    // 0 if B is greater than or equal to A
+endmodule
+
 module mux_2_1(
     input wire switch,
     input wire [8:0] A,B,
@@ -992,4 +1008,16 @@ module twos_compliment_tb();
         $finish;
 
     end
+endmodule
+
+module zero(
+    input wire [8:0] A,
+    output reg [8:0] B);
+    
+    always @(A) begin
+        if(A == 9'b000000000)
+            B = 9'b000000001;  // 1 if A is zero
+        else
+            B = 9'b000000000;  // 0 if A is non-zero
+    end
 endmodule