diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 2b23520..ea44869 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -25,27 +25,28 @@ This means code written to parse this file will need to be revisited each subseq - - - + + + - - + + - + + - - + + - + - + @@ -58,17 +59,17 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + @@ -81,7 +82,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -104,45 +105,47 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + - + + - + - + - + - + + - - + + - - + + @@ -150,7 +153,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -159,38 +162,39 @@ This means code written to parse this file will need to be revisited each subseq - + + - - + + - - + + - + - + - + - + - +
diff --git a/lab2CA.runs/.jobs/vrs_config_45.xml b/lab2CA.runs/.jobs/vrs_config_45.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_45.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_46.xml b/lab2CA.runs/.jobs/vrs_config_46.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_46.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_47.xml b/lab2CA.runs/.jobs/vrs_config_47.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_47.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_48.xml b/lab2CA.runs/.jobs/vrs_config_48.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_48.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_49.xml b/lab2CA.runs/.jobs/vrs_config_49.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_49.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_50.xml b/lab2CA.runs/.jobs/vrs_config_50.xml new file mode 100644 index 0000000..f7de7f4 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_50.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_51.xml b/lab2CA.runs/.jobs/vrs_config_51.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_51.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_52.xml b/lab2CA.runs/.jobs/vrs_config_52.xml new file mode 100644 index 0000000..f7de7f4 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_52.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_53.xml b/lab2CA.runs/.jobs/vrs_config_53.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_53.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_54.xml b/lab2CA.runs/.jobs/vrs_config_54.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_54.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_55.xml b/lab2CA.runs/.jobs/vrs_config_55.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_55.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/impl_1/init_design.pb b/lab2CA.runs/impl_1/init_design.pb deleted file mode 100644 index 8dac2cb..0000000 Binary files a/lab2CA.runs/impl_1/init_design.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/opt_design.pb b/lab2CA.runs/impl_1/opt_design.pb deleted file mode 100644 index 7b26f1d..0000000 Binary files a/lab2CA.runs/impl_1/opt_design.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/place_design.pb b/lab2CA.runs/impl_1/place_design.pb deleted file mode 100644 index 8278661..0000000 Binary files a/lab2CA.runs/impl_1/place_design.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/route_design.pb b/lab2CA.runs/impl_1/route_design.pb deleted file mode 100644 index 921c9c1..0000000 Binary files a/lab2CA.runs/impl_1/route_design.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/vivado.pb b/lab2CA.runs/impl_1/vivado.pb deleted file mode 100644 index b155e40..0000000 --- a/lab2CA.runs/impl_1/vivado.pb +++ /dev/null @@ -1,4 +0,0 @@ - - - -End Record \ No newline at end of file diff --git a/lab2CA.runs/impl_1/vivado.jou b/lab2CA.runs/impl_1/vivado_13064.backup.jou similarity index 100% rename from lab2CA.runs/impl_1/vivado.jou rename to lab2CA.runs/impl_1/vivado_13064.backup.jou diff --git a/lab2CA.runs/synth_1/CPU9bits.dcp b/lab2CA.runs/synth_1/CPU9bits.dcp index e08a20c..f6812e6 100644 Binary files a/lab2CA.runs/synth_1/CPU9bits.dcp and b/lab2CA.runs/synth_1/CPU9bits.dcp differ diff --git a/lab2CA.runs/synth_1/CPU9bits_tb.tcl b/lab2CA.runs/synth_1/CPU9bits.tcl similarity index 98% rename from lab2CA.runs/synth_1/CPU9bits_tb.tcl rename to lab2CA.runs/synth_1/CPU9bits.tcl index 0ff5867..9896a6c 100644 --- a/lab2CA.runs/synth_1/CPU9bits_tb.tcl +++ b/lab2CA.runs/synth_1/CPU9bits.tcl @@ -17,7 +17,7 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } -set_param synth.incrementalSynthesisCache C:/Users/willi/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-18452-WM-G75VW/incrSyn +set_param synth.incrementalSynthesisCache C:/Users/willi/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-28060-WM-G75VW/incrSyn set_msg_config -id {Synth 8-256} -limit 10000 set_msg_config -id {Synth 8-638} -limit 10000 create_project -in_memory -part xc7k160tifbg484-2L diff --git a/lab2CA.runs/synth_1/CPU9bits.vds b/lab2CA.runs/synth_1/CPU9bits.vds index 8dd8172..7b930ab 100644 --- a/lab2CA.runs/synth_1/CPU9bits.vds +++ b/lab2CA.runs/synth_1/CPU9bits.vds @@ -2,8 +2,8 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 16:57:48 2019 -# Process ID: 9320 +# Start of session at: Fri Mar 29 17:10:12 2019 +# Process ID: 21792 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1 # Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds @@ -15,17 +15,14 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 4932 -WARNING: [Synth 8-1958] event expressions must result in a singular type [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81] +INFO: Helper process launched with PID 15728 --------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 376.207 ; gain = 113.672 +Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 364.047 ; gain = 101.191 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] -WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81] -WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81] INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] @@ -61,10 +58,10 @@ INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] -INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] -INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] -INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] -INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] @@ -72,13 +69,9 @@ INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educ INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541] INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] -WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] -WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] -WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] -WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] -INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:12] INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996] INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996] @@ -86,44 +79,23 @@ INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educati INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356] INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] -WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0] -WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0] -WARNING: [Synth 8-3331] design shift_left has unconnected port A[8] -WARNING: [Synth 8-3331] design instructionMemory has unconnected port clk --------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473 +Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.727 ; gain = 157.871 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473 +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.727 ; gain = 157.871 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k160tifbg484-2L --------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.727 ; gain = 157.871 INFO: [Device 21-403] Loading part xc7k160tifbg484-2L -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473 --------------------------------------------------------------------------------- -WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[15]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[14]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[13]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[12]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[11]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[10]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[9]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[8]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[7]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[6]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[5]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[4]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[3]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[2]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[1]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[0]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83] -WARNING: [Synth 8-327] inferring latch for variable 'dataMemEn_reg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:26] +INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5) --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 461.227 ; gain = 198.691 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.727 ; gain = 157.871 --------------------------------------------------------------------------------- INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_3bit) to 'SE3' @@ -140,18 +112,21 @@ Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 162 +---Registers : - 9 Bit Registers := 9 + 9 Bit Registers := 10 ++---RAMs : + 4K Bit RAMs := 1 +---Muxes : - 2 Input 9 Bit Muxes := 28 + 7 Input 9 Bit Muxes := 1 4 Input 9 Bit Muxes := 4 + 2 Input 9 Bit Muxes := 8 2 Input 4 Bit Muxes := 2 4 Input 4 Bit Muxes := 2 16 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 16 Input 3 Bit Muxes := 1 16 Input 2 Bit Muxes := 1 - 16 Input 1 Bit Muxes := 24 - 2 Input 1 Bit Muxes := 33 + 16 Input 1 Bit Muxes := 7 + 2 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -159,12 +134,16 @@ Finished RTL Component Statistics Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report -Module dataMemory +Module instructionMemory Detailed RTL Component Info : +---Muxes : - 2 Input 9 Bit Muxes := 20 - 16 Input 1 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 32 + 7 Input 9 Bit Muxes := 1 +Module dataMemory +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 ++---RAMs : + 4K Bit RAMs := 1 Module decoder Detailed RTL Component Info : +---Muxes : @@ -193,7 +172,7 @@ Detailed RTL Component Info : 2 Input 3 Bit Muxes := 2 16 Input 3 Bit Muxes := 1 16 Input 2 Bit Muxes := 1 - 16 Input 1 Bit Muxes := 8 + 16 Input 1 Bit Muxes := 7 Module bit1_mux_2_1 Detailed RTL Component Info : +---Muxes : @@ -216,22 +195,7 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 723.004 ; gain = 460.469 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start ROM, RAM, DSP and Shift Register Reporting ---------------------------------------------------------------------------------- - -ROM: -+------------------+------------+---------------+----------------+ -|Module Name | RTL Object | Depth x Width | Implemented As | -+------------------+------------+---------------+----------------+ -|instructionMemory | p_0_out | 64x9 | LUT | -|CPU9bits | p_0_out | 64x9 | LUT | -+------------------+------------+---------------+----------------+ - ---------------------------------------------------------------------------------- -Finished ROM, RAM, DSP and Shift Register Reporting +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 599.770 ; gain = 336.914 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -244,7 +208,7 @@ No constraint files found. Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 723.004 ; gain = 460.469 +Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 599.770 ; gain = 336.914 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -256,7 +220,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 723.004 ; gain = 460.469 +Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 599.770 ; gain = 336.914 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -280,7 +244,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +Finished IO Insertion : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 599.770 ; gain = 336.914 --------------------------------------------------------------------------------- Report Check Netlist: @@ -293,7 +257,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 599.770 ; gain = 336.914 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -305,25 +269,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 599.770 ; gain = 336.914 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 599.770 ; gain = 336.914 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 599.770 ; gain = 336.914 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 599.770 ; gain = 336.914 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -336,65 +300,46 @@ Report BlackBoxes: +-+--------------+----------+ Report Cell Usage: -+------+------+------+ -| |Cell |Count | -+------+------+------+ -|1 |BUFG | 2| -|2 |LUT2 | 45| -|3 |LUT3 | 50| -|4 |LUT4 | 51| -|5 |LUT5 | 69| -|6 |LUT6 | 439| -|7 |MUXF7 | 6| -|8 |FDRE | 81| -|9 |LD | 154| -|10 |IBUF | 2| -|11 |OBUF | 1| -+------+------+------+ ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |BUFG | 1| +|2 |LUT2 | 1| +|3 |LUT3 | 2| +|4 |LUT4 | 1| +|5 |FDRE | 3| +|6 |IBUF | 2| +|7 |OBUF | 1| ++------+-----+------+ Report Instance Areas: -+------+---------+------------+------+ -| |Instance |Module |Cells | -+------+---------+------------+------+ -|1 |top | | 900| -|2 | Bank |RegFile | 45| -|3 | r0 |register_5 | 16| -|4 | r1 |register_6 | 9| -|5 | r2 |register_7 | 10| -|6 | r3 |register_8 | 10| -|7 | CU |ControlUnit | 14| -|8 | FetchU |FetchUnit | 126| -|9 | PC |register_4 | 126| -|10 | RF |RegFile_0 | 345| -|11 | r0 |register | 216| -|12 | r1 |register_1 | 14| -|13 | r2 |register_2 | 100| -|14 | r3 |register_3 | 15| -|15 | dM |dataMemory | 365| -+------+---------+------------+------+ ++------+---------+----------+------+ +| |Instance |Module |Cells | ++------+---------+----------+------+ +|1 |top | | 11| +|2 | FetchU |FetchUnit | 7| +|3 | PC |register | 7| ++------+---------+----------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 599.770 ; gain = 336.914 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 29 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 -Synthesis Optimization Complete : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469 +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 599.770 ; gain = 336.914 +Synthesis Optimization Complete : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 599.770 ; gain = 336.914 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 160 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 723.004 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 683.395 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: - A total of 154 instances were transformed. - LD => LDCE: 154 instances +No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -70 Infos, 29 Warnings, 0 Critical Warnings and 0 Errors encountered. +69 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 723.004 ; gain = 473.363 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 723.004 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 683.395 ; gain = 433.676 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 683.395 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 16:58:31 2019... +INFO: [Common 17-206] Exiting Vivado at Fri Mar 29 17:10:43 2019... diff --git a/lab2CA.runs/synth_1/CPU9bits_tb.dcp b/lab2CA.runs/synth_1/CPU9bits_tb.dcp deleted file mode 100644 index 21db77f..0000000 Binary files a/lab2CA.runs/synth_1/CPU9bits_tb.dcp and /dev/null differ diff --git a/lab2CA.runs/synth_1/CPU9bits_tb.vds b/lab2CA.runs/synth_1/CPU9bits_tb.vds deleted file mode 100644 index db1748c..0000000 --- a/lab2CA.runs/synth_1/CPU9bits_tb.vds +++ /dev/null @@ -1,951 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 18:28:31 2019 -# Process ID: 5228 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1 -# Command line: vivado.exe -log CPU9bits_tb.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.vds -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou -#----------------------------------------------------------- -source CPU9bits_tb.tcl -notrace -Command: synth_design -top CPU9bits_tb -part xc7k160tifbg484-2L -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 14244 -WARNING: [Synth 8-1958] event expressions must result in a singular type [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85] ---------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 372.199 ; gain = 114.445 ---------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'CPU9bits_tb' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:172] -WARNING: [Synth 8-85] always block has no event control specified [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:179] -INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] -INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] -INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] -INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] -WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85] -WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85] -INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] -INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] -INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] -INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268] -INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] -INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777] -INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777] -INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407] -INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412] -INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407] -INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] -INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] -INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] -INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] -INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] -INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] -INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336] -INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342] -INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336] -INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] -INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] -INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311] -INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376] -INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687] -INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687] -INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376] -INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311] -INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724] -INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724] -INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643] -INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643] -INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] -INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] -INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] -INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] -INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] -INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] -INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] -INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] -INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] -INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] -INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] -INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] -INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] -INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541] -INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] -WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] -WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] -WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] -WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] -INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] -INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] -INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17] -INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] -INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996] -INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996] -INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] -INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356] -INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] -INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] -INFO: [Synth 8-6155] done synthesizing module 'CPU9bits_tb' (28#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:172] -WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0] -WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0] -WARNING: [Synth 8-3331] design shift_left has unconnected port A[8] ---------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:01:51 ; elapsed = 00:01:54 . Memory (MB): peak = 2338.125 ; gain = 2080.371 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:02:04 ; elapsed = 00:02:09 . Memory (MB): peak = 2338.125 ; gain = 2080.371 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7k160tifbg484-2L ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:02:04 ; elapsed = 00:02:09 . Memory (MB): peak = 2338.125 ; gain = 2080.371 ---------------------------------------------------------------------------------- -INFO: [Device 21-403] Loading part xc7k160tifbg484-2L -INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5) -INFO: [Synth 8-5546] ROM "memory_reg[511]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[510]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[509]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[508]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[507]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[506]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[505]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[504]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[503]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[502]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[501]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[500]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[499]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[498]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[497]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[496]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[495]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[494]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[493]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[492]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[491]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[490]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[489]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[488]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[487]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[486]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[485]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[484]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[483]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[482]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[481]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[480]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[479]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[478]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[477]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[476]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[475]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[474]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[473]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[472]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[471]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[470]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[469]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[468]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[467]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[466]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[465]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[464]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[463]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[462]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[461]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[460]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[459]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[458]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[457]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[456]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[455]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[454]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[453]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[452]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[451]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[450]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[449]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[448]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[447]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[446]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[445]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[444]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[443]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[442]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[441]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[440]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[439]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[438]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[437]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[436]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[435]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[434]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[433]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[432]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[431]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[430]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[429]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[428]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[427]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[426]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[425]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[424]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[423]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[422]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[421]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[420]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[419]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[418]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[417]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[416]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[415]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[414]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[413]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "memory_reg[412]" won't be mapped to RAM because it is too sparse -INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:202] -WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[511]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[510]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[509]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[508]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[507]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[506]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[505]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[504]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[503]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[502]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[501]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[500]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[499]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[498]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[497]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[496]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[495]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[494]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[493]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[492]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[491]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[490]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[489]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[488]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[487]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[486]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[485]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[484]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[483]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[482]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[481]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[480]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[479]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[478]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[477]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[476]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[475]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[474]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[473]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[472]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[471]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[470]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[469]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[468]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[467]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[466]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[465]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[464]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[463]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[462]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[461]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[460]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[459]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[458]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[457]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[456]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[455]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[454]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[453]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[452]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[451]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[450]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[449]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[448]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[447]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[446]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[445]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[444]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[443]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[442]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[441]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[440]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[439]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[438]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[437]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[436]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[435]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[434]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[433]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[432]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[431]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[430]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[429]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[428]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[427]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[426]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[425]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[424]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[423]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[422]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[421]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[420]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[419]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[418]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[417]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[416]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[415]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[414]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87] -INFO: [Common 17-14] Message 'Synth 8-327' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:04:25 ; elapsed = 00:04:33 . Memory (MB): peak = 2906.012 ; gain = 2648.258 ---------------------------------------------------------------------------------- -INFO: [Synth 8-223] decloning instance 'CPU9bits0/SE1' (sign_extend_3bit) to 'CPU9bits0/SE3' - -Report RTL Partitions: -+------+----------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+------+----------------+------------+----------+ -|1 |dataMemory__GB0 | 1| 2378380| -|2 |CPU9bits__GC0 | 1| 1169| -+------+----------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 162 -+---Registers : - 9 Bit Registers := 9 -+---Muxes : - 2 Input 9 Bit Muxes := 520 - 8 Input 9 Bit Muxes := 1 - 4 Input 9 Bit Muxes := 4 - 2 Input 4 Bit Muxes := 2 - 4 Input 4 Bit Muxes := 2 - 16 Input 4 Bit Muxes := 1 - 2 Input 3 Bit Muxes := 2 - 16 Input 3 Bit Muxes := 1 - 16 Input 2 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 513 - 16 Input 1 Bit Muxes := 8 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module dataMemory -Detailed RTL Component Info : -+---Muxes : - 2 Input 9 Bit Muxes := 512 - 2 Input 1 Bit Muxes := 512 -Module instructionMemory -Detailed RTL Component Info : -+---Muxes : - 8 Input 9 Bit Muxes := 1 -Module decoder__1 -Detailed RTL Component Info : -+---Muxes : - 2 Input 4 Bit Muxes := 1 - 4 Input 4 Bit Muxes := 1 -Module register__8 -Detailed RTL Component Info : -+---Registers : - 9 Bit Registers := 1 -Module register__7 -Detailed RTL Component Info : -+---Registers : - 9 Bit Registers := 1 -Module register__6 -Detailed RTL Component Info : -+---Registers : - 9 Bit Registers := 1 -Module register__5 -Detailed RTL Component Info : -+---Registers : - 9 Bit Registers := 1 -Module mux_4_1__3 -Detailed RTL Component Info : -+---Muxes : - 4 Input 9 Bit Muxes := 1 -Module mux_4_1__2 -Detailed RTL Component Info : -+---Muxes : - 4 Input 9 Bit Muxes := 1 -Module decoder -Detailed RTL Component Info : -+---Muxes : - 2 Input 4 Bit Muxes := 1 - 4 Input 4 Bit Muxes := 1 -Module register__2 -Detailed RTL Component Info : -+---Registers : - 9 Bit Registers := 1 -Module register__3 -Detailed RTL Component Info : -+---Registers : - 9 Bit Registers := 1 -Module register__4 -Detailed RTL Component Info : -+---Registers : - 9 Bit Registers := 1 -Module register -Detailed RTL Component Info : -+---Registers : - 9 Bit Registers := 1 -Module mux_4_1__1 -Detailed RTL Component Info : -+---Muxes : - 4 Input 9 Bit Muxes := 1 -Module mux_4_1 -Detailed RTL Component Info : -+---Muxes : - 4 Input 9 Bit Muxes := 1 -Module register__1 -Detailed RTL Component Info : -+---Registers : - 9 Bit Registers := 1 -Module add_1bit__44 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__43 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__42 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__41 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__40 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__39 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__38 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__37 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__36 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module mux_2_1__1 -Detailed RTL Component Info : -+---Muxes : - 2 Input 9 Bit Muxes := 1 -Module add_1bit__35 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__34 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__33 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__32 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__31 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__30 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__29 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__28 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__27 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__62 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__61 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__60 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__59 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__58 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__57 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__56 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__55 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__54 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__26 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__25 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__24 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__23 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__22 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__21 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__20 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__19 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__18 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__80 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__79 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__78 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__77 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__76 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__75 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__74 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__73 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__72 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__71 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__70 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__69 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__68 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__67 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__66 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__65 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__64 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__63 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module ControlUnit -Detailed RTL Component Info : -+---Muxes : - 16 Input 4 Bit Muxes := 1 - 2 Input 3 Bit Muxes := 2 - 16 Input 3 Bit Muxes := 1 - 16 Input 2 Bit Muxes := 1 - 16 Input 1 Bit Muxes := 8 -Module add_1bit__53 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__52 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__51 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__50 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__49 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__48 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__47 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__46 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__45 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module mux_2_1__2 -Detailed RTL Component Info : -+---Muxes : - 2 Input 9 Bit Muxes := 1 -Module add_1bit__17 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__16 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__15 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__14 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__13 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__12 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__11 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__10 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__9 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module mux_2_1__3 -Detailed RTL Component Info : -+---Muxes : - 2 Input 9 Bit Muxes := 1 -Module mux_2_1__4 -Detailed RTL Component Info : -+---Muxes : - 2 Input 9 Bit Muxes := 1 -Module bit1_mux_2_1 -Detailed RTL Component Info : -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module add_1bit__1 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__2 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__3 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__4 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__5 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__6 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__7 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit__8 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module add_1bit -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 2 -Module mux_2_1__5 -Detailed RTL Component Info : -+---Muxes : - 2 Input 9 Bit Muxes := 1 -Module mux_2_1__6 -Detailed RTL Component Info : -+---Muxes : - 2 Input 9 Bit Muxes := 1 -Module mux_2_1__7 -Detailed RTL Component Info : -+---Muxes : - 2 Input 9 Bit Muxes := 1 -Module mux_2_1 -Detailed RTL Component Info : -+---Muxes : - 2 Input 9 Bit Muxes := 1 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 600 (col length:100) -BRAMs: 650 (col length: RAMB18 100 RAMB36 50) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[0]' (LD) to 'CPU9bits0i_1/iM/readData_reg[2]' -INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[8]' (LD) to 'CPU9bits0i_1/iM/readData_reg[6]' -INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[2]' (LD) to 'CPU9bits0i_1/iM/readData_reg[4]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\iM/readData_reg[4] ) ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+-+-----+------+ -| |Cell |Count | -+-+-----+------+ -+-+-----+------+ - -Report Instance Areas: -+------+---------+-------+------+ -| |Instance |Module |Cells | -+------+---------+-------+------+ -|1 |top | | 0| -+------+---------+-------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 526 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 -Synthesis Optimization Complete : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3340.348 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -177 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:09:36 ; elapsed = 00:10:01 . Memory (MB): peak = 3340.348 ; gain = 3090.086 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 3340.348 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 18:38:37 2019... diff --git a/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb b/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb deleted file mode 100644 index 68f663d..0000000 Binary files a/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb and /dev/null differ diff --git a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb index 8c1d275..cc59513 100644 Binary files a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb and b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb differ diff --git a/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt similarity index 86% rename from lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt rename to lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt index eb83468..9e9e859 100644 --- a/lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt +++ b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sun Mar 24 16:58:30 2019 +| Date : Fri Mar 29 17:10:43 2019 | Host : WM-G75VW running 64-bit major release (build 9200) | Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb | Design : CPU9bits @@ -30,13 +30,13 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 578 | 0 | 101400 | 0.57 | -| LUT as Logic | 578 | 0 | 101400 | 0.57 | +| Slice LUTs* | 2 | 0 | 101400 | <0.01 | +| LUT as Logic | 2 | 0 | 101400 | <0.01 | | LUT as Memory | 0 | 0 | 35000 | 0.00 | -| Slice Registers | 235 | 0 | 202800 | 0.12 | -| Register as Flip Flop | 81 | 0 | 202800 | 0.04 | -| Register as Latch | 154 | 0 | 202800 | 0.08 | -| F7 Muxes | 6 | 0 | 50700 | 0.01 | +| Slice Registers | 3 | 0 | 202800 | <0.01 | +| Register as Flip Flop | 3 | 0 | 202800 | <0.01 | +| Register as Latch | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 50700 | 0.00 | | F8 Muxes | 0 | 0 | 25350 | 0.00 | +-------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -55,9 +55,9 @@ Table of Contents | 0 | _ | Reset | - | | 0 | Yes | - | - | | 0 | Yes | - | Set | -| 154 | Yes | - | Reset | +| 0 | Yes | - | Reset | | 0 | Yes | Set | - | -| 81 | Yes | Reset | - | +| 3 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -117,7 +117,7 @@ Table of Contents +------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +------------+------+-------+-----------+-------+ -| BUFGCTRL | 2 | 0 | 32 | 6.25 | +| BUFGCTRL | 1 | 0 | 32 | 3.13 | | BUFIO | 0 | 0 | 32 | 0.00 | | MMCME2_ADV | 0 | 0 | 8 | 0.00 | | PLLE2_ADV | 0 | 0 | 8 | 0.00 | @@ -151,17 +151,13 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| LUT6 | 439 | LUT | -| LDCE | 154 | Flop & Latch | -| FDRE | 81 | Flop & Latch | -| LUT5 | 69 | LUT | -| LUT4 | 51 | LUT | -| LUT3 | 50 | LUT | -| LUT2 | 45 | LUT | -| MUXF7 | 6 | MuxFx | +| FDRE | 3 | Flop & Latch | +| LUT3 | 2 | LUT | | IBUF | 2 | IO | -| BUFG | 2 | Clock | | OBUF | 1 | IO | +| LUT4 | 1 | LUT | +| LUT2 | 1 | LUT | +| BUFG | 1 | Clock | +----------+------+---------------------+ diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml index fbd2015..81c742a 100644 --- a/lab2CA.runs/synth_1/gen_run.xml +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -1,11 +1,14 @@ - + + + + diff --git a/lab2CA.runs/synth_1/htr.txt b/lab2CA.runs/synth_1/htr.txt index b59ff1f..641d4cb 100644 --- a/lab2CA.runs/synth_1/htr.txt +++ b/lab2CA.runs/synth_1/htr.txt @@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status. REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. REM -vivado -log CPU9bits_tb.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl +vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl diff --git a/lab2CA.runs/synth_1/vivado.jou b/lab2CA.runs/synth_1/vivado.jou index c45f63a..8a85c6e 100644 --- a/lab2CA.runs/synth_1/vivado.jou +++ b/lab2CA.runs/synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 16:57:48 2019 -# Process ID: 9320 +# Start of session at: Fri Mar 29 17:10:12 2019 +# Process ID: 21792 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1 # Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds diff --git a/lab2CA.runs/synth_1/vivado.pb b/lab2CA.runs/synth_1/vivado.pb index 02439a4..37d6053 100644 Binary files a/lab2CA.runs/synth_1/vivado.pb and b/lab2CA.runs/synth_1/vivado.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/dataMemory_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/dataMemory_tb.tcl index 1094e45..8243a08 100644 --- a/lab2CA.sim/sim_1/behav/xsim/dataMemory_tb.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/dataMemory_tb.tcl @@ -8,4 +8,4 @@ if { [string length $curr_wave] == 0 } { } } -run 1000ns +run 100000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou index fe12bc0..b4e6d63 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou @@ -2,10 +2,10 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 17:05:08 2019 -# Process ID: 16036 +# Start of session at: Fri Mar 29 15:28:37 2019 +# Process ID: 28052 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_13536.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_13536.backup.jou deleted file mode 100644 index c58850d..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_13536.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 17:24:25 2019 -# Process ID: 13536 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_14824.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_14652.backup.jou similarity index 92% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_14824.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_14652.backup.jou index 0520b47..5f01ab3 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_14824.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_14652.backup.jou @@ -2,8 +2,8 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 16:59:36 2019 -# Process ID: 14824 +# Start of session at: Fri Mar 29 15:13:54 2019 +# Process ID: 14652 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim # Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_26660.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_26660.backup.jou new file mode 100644 index 0000000..21e9e99 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_26660.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Fri Mar 29 15:21:59 2019 +# Process ID: 26660 +# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/REPOSITORIES/Educational/Western -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_42696.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_5080.backup.jou similarity index 92% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_42696.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_5080.backup.jou index 9e45a86..cbfef31 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_42696.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_5080.backup.jou @@ -2,8 +2,8 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Fri Mar 22 17:35:57 2019 -# Process ID: 42696 +# Start of session at: Fri Mar 29 15:24:02 2019 +# Process ID: 5080 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim # Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index 175ab93..a4feb66 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xelab.pb and b/lab2CA.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl deleted file mode 100644 index 3d5902e..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl +++ /dev/null @@ -1,32 +0,0 @@ -webtalk_init -webtalk_dir C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/ -webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Sun Mar 24 19:25:23 2019" -context "software_version_and_target_device" -webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" -webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" -webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" -webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" -webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" -webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" -webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key random_id -value "f67bb5263bf851bf9c1beaa84fe1017c" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "48" -context "software_version_and_target_device" -webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" -webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" -webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "2395 MHz" -context "user_environment" -webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment" -webtalk_register_client -client xsim -webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" -webtalk_add_data -client xsim -key runtime -value "50020 ns" -context "xsim\\usage" -webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.30_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "9684_KB" -context "xsim\\usage" -webtalk_transmit -clientid 3966238694 -regid "" -xml C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" -webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem index a211095..c66adf9 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/obj/xsim_1.c index 594dd97..864eb8c 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/obj/xsim_1.c +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/obj/xsim_1.c @@ -45,30 +45,29 @@ typedef void (*funcp)(char *, char *); extern int main(int, char**); extern void execute_2(char*, char *); -extern void execute_3(char*, char *); -extern void execute_7(char*, char *); +extern void execute_6(char*, char *); +extern void execute_11(char*, char *); extern void execute_12(char*, char *); extern void execute_13(char*, char *); extern void execute_14(char*, char *); extern void execute_15(char*, char *); -extern void execute_16(char*, char *); +extern void execute_4(char*, char *); extern void execute_5(char*, char *); -extern void execute_6(char*, char *); +extern void execute_8(char*, char *); extern void execute_9(char*, char *); extern void execute_10(char*, char *); -extern void execute_11(char*, char *); +extern void execute_16(char*, char *); extern void execute_17(char*, char *); extern void execute_18(char*, char *); extern void execute_19(char*, char *); extern void execute_20(char*, char *); -extern void execute_21(char*, char *); extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); -funcp funcTab[19] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_7, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_5, (funcp)execute_6, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)vlog_transfunc_eventcallback}; -const int NumRelocateId= 19; +funcp funcTab[18] = {(funcp)execute_2, (funcp)execute_6, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_4, (funcp)execute_5, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 18; void relocate(char *dp) { - iki_relocate(dp, "xsim.dir/dataMemory_tb_behav/xsim.reloc", (void **)funcTab, 19); + iki_relocate(dp, "xsim.dir/dataMemory_tb_behav/xsim.reloc", (void **)funcTab, 18); /*Populate the transaction function pointer field in the whole net structure */ } diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl index 1155c64..4e5cbf1 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl @@ -1,10 +1,10 @@ -webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/ +webtalk_init -webtalk_dir C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Sun Mar 24 17:39:03 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Fri Mar 29 15:35:47 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" -webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" @@ -12,21 +12,21 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "f67bb5263bf851bf9c1beaa84fe1017c" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "22" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "5" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" -webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2395 MHz" -context "user_environment" webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment" webtalk_register_client -client xsim webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" webtalk_add_data -client xsim -key runtime -value "60 ns" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "6128_KB" -context "xsim\\usage" -webtalk_transmit -clientid 918939418 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key Simulation_Time -value "0.08_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "5520_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3479297430 -regid "" -xml C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem index a201b29..af03532 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb index 912913c..b155e40 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb and b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/lab2CA.xpr b/lab2CA.xpr index b288b98..3ecd428 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -31,7 +31,7 @@