diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v new file mode 100644 index 0000000..dab1d73 --- /dev/null +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -0,0 +1,79 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/15/2019 12:18:27 PM +// Design Name: +// Module Name: BasicModules +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module BasicModules(); +endmodule + +module gen_clock(); + + reg clk; + + initial begin + clk = 1'b0; + end + + always begin + #5 clk = ~clk; // Period to be determined + end + +endmodule + +module register(input wire clk, reset, + input wire [1:0] En, + input wire [8:0] Din, + output reg [8:0] Dout); + + always @(posedge clk) begin + if (reset == 1'b1) begin + Dout <= 9'b000000000; + end + else if (En == 2'b00) begin + Dout <= Din; + end + else begin + Dout <= "ZZZZZZZZZ"; + end + end + +endmodule + +module mux(input wire [1:0] switch, + input wire [8:0] A,B,C,D, + output reg [8:0] out); + + always @(A,B,C,D,switch) begin + if (switch == 2'b00) begin + out = A; + end + else if (switch == 2'b01) begin + out = B; + end + else if (switch == 2'b11) begin + out = C; + end + else begin + out = D; + end + end + +endmodule + diff --git a/lab2CA.srcs/sources_1/new/FetchUnit.v b/lab2CA.srcs/sources_1/new/FetchUnit.v new file mode 100644 index 0000000..6da1ad6 --- /dev/null +++ b/lab2CA.srcs/sources_1/new/FetchUnit.v @@ -0,0 +1,27 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/15/2019 12:19:52 PM +// Design Name: +// Module Name: FetchUnit +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module FetchUnit(input wire clk, + input wire [8:0] AddrIn, + output wire [8:0] AddrOut); + +endmodule diff --git a/lab2CA.srcs/sources_1/new/RegFile.v b/lab2CA.srcs/sources_1/new/RegFile.v new file mode 100644 index 0000000..b1c1386 --- /dev/null +++ b/lab2CA.srcs/sources_1/new/RegFile.v @@ -0,0 +1,74 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/15/2019 12:21:16 PM +// Design Name: +// Module Name: RegFile +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module RegFile(input wire clk, reset, + input wire [1:0] write_index, op0_idx, op1_idx, + input wire [8:0] write_data, + output wire [8:0] op0, op1); + + wire [8:0] r0_out, r1_out, r2_out, r3_out; + + // To select a register En input must be 2'b00 + + register r0( + .clk(clk), + .reset(reset), + .En({write_index[0], write_index[1]}), + .Din(write_data), + .Dout(r0_out)); + + register r1( + .clk(clk), + .reset(reset), + .En({write_index[0], ~write_index[1]}), + .Din(write_data), + .Dout(r1_out)); + + register r2( + .clk(clk), + .reset(reset), + .En({~write_index[0], write_index[1]}), + .Din(write_data), + .Dout(r2_out)); + + register r3( + .clk(clk), + .reset(reset), + .En({~write_index[0], ~write_index[1]}), + .Din(write_data), + .Dout(r3_out)); + + mux m0( + .A(r0_out), + .B(r1_out), + .C(r2_out), + .D(r3_out), + .switch(op0_idx)); + + mux m1( + .A(r0_out), + .B(r1_out), + .C(r2_out), + .D(r3_out), + .switch(op1_idx)); + +endmodule diff --git a/lab2CA.srcs/sources_1/new/lab2testing.v b/lab2CA.srcs/sources_1/new/lab2testing.v index 4bacf92..f03b13a 100644 --- a/lab2CA.srcs/sources_1/new/lab2testing.v +++ b/lab2CA.srcs/sources_1/new/lab2testing.v @@ -3,7 +3,6 @@ module lab2testing(); - endmodule module regFile(input wire clk, reset, @@ -13,6 +12,8 @@ module regFile(input wire clk, reset, wire [8:0] r0_out, r1_out, r2_out, r3_out; + // To select a register En input must be 2'b00 + register r0( .clk(clk), .reset(reset), @@ -55,21 +56,4 @@ module regFile(input wire clk, reset, .D(r3_out), .switch(op1_idx)); -endmodule - -module register(input wire clk, reset, - input wire [1:0] En, - input wire [8:0] Din, - output reg [8:0] Dout); - -endmodule - -module MUX(); - -endmodule - -module fetchUnit(input wire clk, - input wire [8:0] AddrIn, - output wire [8:0] AddrOut); - -endmodule +endmodule \ No newline at end of file diff --git a/lab2CA.xpr b/lab2CA.xpr index 56299b9..c1369d1 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - +