diff --git a/README.md b/README.md
index 24dc63d..b485079 100644
--- a/README.md
+++ b/README.md
@@ -10,7 +10,7 @@
 * Need to allow for signed numbers
 * Remove subtraction from ALU
 * Have arithmetic shift left and right
-* Uncomment all testbenches
+* <strike>Uncomment all testbenches</strike>
   * We can have multiple testbenches active at once
 * Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only
 * Comparator needed
diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v
index 604c2f5..06c12db 100644
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -62,47 +62,47 @@ module ALU(
 
 endmodule
 
-//testbench
-//module alu_tb();
-//reg [8:0] a;
-//reg [8:0] b;
-//reg [2:0] c;
-//wire [8:0] d;
+testbench
+module alu_tb();
+reg [8:0] a;
+reg [8:0] b;
+reg [2:0] c;
+wire [8:0] d;
 
-//ALU alu0(
-//.operand0(a),
-//.operand1(b),
-//.opcode(c),
-//.result(d));
+ALU alu0(
+.operand0(a),
+.operand1(b),
+.opcode(c),
+.result(d));
     
-//    initial begin
-//    a = 9'b000000111;
-//    b = 9'b000111000;
-//    c = 3'b000;
-//    #5
-//    a = 9'b000011000;
-//    b = 9'b000011000;
-//    c = 3'b001;
-//    #5
-//    a = 9'b101010100;
-//    b = 9'b010101011;
-//    c = 3'b010;
-//    #5
-//    a = 9'b101010100;
-//    b = 9'b010101000;
-//    c = 3'b011;
-//    #5
-//    a = 9'b000110000;
-//    b = 9'b000111000;
-//    c = 3'b100;
-//    #5
-//    a = 9'b01011000;
-//    c = 3'b101;
-//    #5
-//    a = 9'b00001010;
-//    c = 3'b110;
-//    #5
-//    #5 $finish;
+   initial begin
+   a = 9'b000000111;
+   b = 9'b000111000;
+   c = 3'b000;
+   #5
+   a = 9'b000011000;
+   b = 9'b000011000;
+   c = 3'b001;
+   #5
+   a = 9'b101010100;
+   b = 9'b010101011;
+   c = 3'b010;
+   #5
+   a = 9'b101010100;
+   b = 9'b010101000;
+   c = 3'b011;
+   #5
+   a = 9'b000110000;
+   b = 9'b000111000;
+   c = 3'b100;
+   #5
+   a = 9'b01011000;
+   c = 3'b101;
+   #5
+   a = 9'b00001010;
+   c = 3'b110;
+   #5
+   #5 $finish;
 
-//    end
-//endmodule
+   end
+endmodule
diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index fefe221..1dee8a1 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -13,42 +13,42 @@ module add_1bit(
 endmodule
 
 //testbench
-//module add1bit_tb();
-//reg v;
-//reg w;
-//reg x;
-//wire y;
-//wire z;
+module add1bit_tb();
+reg v;
+reg w;
+reg x;
+wire y;
+wire z;
 
-//add_1bit add0(
-//    .A(v),
-//    .B(w),
-//    .Cin(x),
-//    .S(y),
-//    .Cout(z));
+add_1bit add0(
+   .A(v),
+   .B(w),
+   .Cin(x),
+   .S(y),
+   .Cout(z));
     
-//    initial begin
-//    v = 0;
-//    w = 0;
-//    x = 0;
-//    #5
-//    v = 0;
-//    w = 1;
-//    x = 0;
-//    #5
-//    v = 0;
-//    w = 0;
-//    x = 1;
-//    #5
-//    v = 1;
-//    w = 1;
-//    x = 0;
-//    #5
-//    v = 1;
-//    w = 1;
-//    x = 1;
-//    end
-//endmodule
+   initial begin
+   v = 0;
+   w = 0;
+   x = 0;
+   #5
+   v = 0;
+   w = 1;
+   x = 0;
+   #5
+   v = 0;
+   w = 0;
+   x = 1;
+   #5
+   v = 1;
+   w = 1;
+   x = 0;
+   #5
+   v = 1;
+   w = 1;
+   x = 1;
+   end
+endmodule
 
 module add_9bit(
     input wire [8:0] A,
@@ -132,43 +132,43 @@ module add_9bit(
 endmodule
 
 //testbench
-//module add9bit_tb();
-//reg [8:0] a;
-//reg [8:0] b;
-//reg cin;
-//wire [8:0] s;
-//wire cout;
+module add9bit_tb();
+reg [8:0] a;
+reg [8:0] b;
+reg cin;
+wire [8:0] s;
+wire cout;
 
-//add_9bit add0(
-//    .A(a),
-//    .B(b),
-//    .Cin(cin),
-//    .Sum(s),
-//    .Cout(cout));
+add_9bit add0(
+   .A(a),
+   .B(b),
+   .Cin(cin),
+   .Sum(s),
+   .Cout(cout));
     
     
-//    initial begin
-//    a = 9'b000000000;
-//    b = 9'b000000000;
-//    cin = 0;
-//    #5
-//    a = 9'b000000001;
-//    b = 9'b000000000;
-//    cin = 0;
-//    #5
-//    a = 9'b000000000;
-//    b = 9'b000000001;
-//    cin = 1;
-//    #5
-//    a = 9'b000000001;
-//    b = 9'b000000001;
-//    cin = 0;
-//    #5
-//    a = 9'b000001000;
-//    b = 9'b000000001;
-//    cin = 1;
-//    end
-//endmodule
+   initial begin
+   a = 9'b000000000;
+   b = 9'b000000000;
+   cin = 0;
+   #5
+   a = 9'b000000001;
+   b = 9'b000000000;
+   cin = 0;
+   #5
+   a = 9'b000000000;
+   b = 9'b000000001;
+   cin = 1;
+   #5
+   a = 9'b000000001;
+   b = 9'b000000001;
+   cin = 0;
+   #5
+   a = 9'b000001000;
+   b = 9'b000000001;
+   cin = 1;
+   end
+endmodule
 
 module and_1bit(
     input wire A,
@@ -180,32 +180,32 @@ module and_1bit(
 endmodule
 
 //testbench
-//module and1bit_tb();
-//reg a;
-//reg b;
-//wire c;
+module and1bit_tb();
+reg a;
+reg b;
+wire c;
 
-//and_1bit and0(
-//.A(a),
-//.B(b),
-//.C(c));
+and_1bit and0(
+.A(a),
+.B(b),
+.C(c));
     
-//    initial begin
-//    a = 0;
-//    b = 0;
-//    #5
-//    a = 0;
-//    b = 1;
-//    #5
-//    a = 1;
-//    b = 0;
-//    #5
-//    a = 1;
-//    b = 1;
-//    #5 $finish;
+   initial begin
+   a = 0;
+   b = 0;
+   #5
+   a = 0;
+   b = 1;
+   #5
+   a = 1;
+   b = 0;
+   #5
+   a = 1;
+   b = 1;
+   #5 $finish;
 
-//    end
-//endmodule
+   end
+endmodule
 
 module and_9bit(
     input wire [8:0] A,
@@ -260,38 +260,38 @@ module and_9bit(
 endmodule
 
 //testbench
-//module and9bit_tb();
-//reg [8:0] a;
-//reg [8:0] b;
-//wire [8:0] c;
+module and9bit_tb();
+reg [8:0] a;
+reg [8:0] b;
+wire [8:0] c;
 
-//and_9bit and0(
-//.A(a),
-//.B(b),
-//.C(c));
+and_9bit and0(
+.A(a),
+.B(b),
+.C(c));
     
-//    initial begin
-//    a = 9'b000000000;
-//    b = 9'b000000000;
-//    #5
-//    a = 9'b000000000;
-//    b = 9'b000000001;
-//    #5
-//    a = 9'b000000001;
-//    b = 9'b000000000;
-//    #5
-//    a = 9'b000000001;
-//    b = 9'b000000001;
-//    #5
-//    a = 9'b000100001;
-//    b = 9'b000000001;
-//    #5
-//    a = 9'b000100001;
-//    b = 9'b000100001;
-//    #5 $finish;
+   initial begin
+   a = 9'b000000000;
+   b = 9'b000000000;
+   #5
+   a = 9'b000000000;
+   b = 9'b000000001;
+   #5
+   a = 9'b000000001;
+   b = 9'b000000000;
+   #5
+   a = 9'b000000001;
+   b = 9'b000000001;
+   #5
+   a = 9'b000100001;
+   b = 9'b000000001;
+   #5
+   a = 9'b000100001;
+   b = 9'b000100001;
+   #5 $finish;
 
-//    end
-//endmodule
+   end
+endmodule
 
 module gen_clock();
     reg clk;
@@ -303,11 +303,11 @@ module gen_clock();
     end
 endmodule
 
-// testbench
-//module gen_clock_tb();
+testbench
+module gen_clock_tb();
 
-//reg clk;
-//    gen
+reg clk;
+   gen
 
 module mux_2_1(input wire switch,
            input wire [8:0] A,B,
@@ -324,46 +324,46 @@ module mux_2_1(input wire switch,
 endmodule
 
 //testbench
-//module mux_2_1_tb();
-//reg s;
-//reg [8:0] a;
-//reg [8:0] b;
-//wire [8:0] c;
+module mux_2_1_tb();
+reg s;
+reg [8:0] a;
+reg [8:0] b;
+wire [8:0] c;
 
-//mux_2_1 mux0(
-//.switch(s),
-//.A(a),
-//.B(b),
-//.out(c));
+mux_2_1 mux0(
+.switch(s),
+.A(a),
+.B(b),
+.out(c));
     
-//    initial begin
-//    s = 0;
-//    a = 9'b000000101;
-//    b = 9'b000000000;
-//    #5
-//    s = 1;
-//    a = 9'b000000001;
-//    b = 9'b000100001;
-//    #5
-//    s = 0;
-//    a = 9'b000000000;
-//    b = 9'b000000001;
-//    #5
-//    s = 1;
-//    a = 9'b000000001;
-//    b = 9'b000000001;
-//    #5
-//    s = 0;
-//    a = 9'b000010001;
-//    b = 9'b000000001;
-//    #5
-//    s = 1;
-//    a = 9'b000010001;
-//    b = 9'b000010111;
-//    #5 $finish;
+   initial begin
+   s = 0;
+   a = 9'b000000101;
+   b = 9'b000000000;
+   #5
+   s = 1;
+   a = 9'b000000001;
+   b = 9'b000100001;
+   #5
+   s = 0;
+   a = 9'b000000000;
+   b = 9'b000000001;
+   #5
+   s = 1;
+   a = 9'b000000001;
+   b = 9'b000000001;
+   #5
+   s = 0;
+   a = 9'b000010001;
+   b = 9'b000000001;
+   #5
+   s = 1;
+   a = 9'b000010001;
+   b = 9'b000010111;
+   #5 $finish;
 
-//    end
-//endmodule
+   end
+endmodule
 
 module mux_4_1(input wire [1:0] switch,
            input wire [8:0] A,B,C,D,
@@ -382,50 +382,50 @@ module mux_4_1(input wire [1:0] switch,
 endmodule
 
 //testbench
-//module mux_4_1_tb();
-//reg [1:0] s;
-//reg [8:0] a;
-//reg [8:0] b;
-//reg [8:0] c;
-//reg [8:0] d;
-//wire [8:0] e;
+module mux_4_1_tb();
+reg [1:0] s;
+reg [8:0] a;
+reg [8:0] b;
+reg [8:0] c;
+reg [8:0] d;
+wire [8:0] e;
 
-//mux_4_1 mux1(
-//.switch(s),
-//.A(a),
-//.B(b),
-//.C(c),
-//.D(d),
-//.out(e));
+mux_4_1 mux1(
+.switch(s),
+.A(a),
+.B(b),
+.C(c),
+.D(d),
+.out(e));
     
-//    initial begin
-//    s = 2'b00;
-//    a = 9'b000000101;
-//    b = 9'b000111100;
-//    c = 9'b001001001;
-//    d = 9'b100000000;
-//    #5
-//    s = 2'b01;
-//    a = 9'b000000101;
-//    b = 9'b000111100;
-//    c = 9'b001001001;
-//    d = 9'b100000000;
-//    #5
-//    s = 2'b10;
-//    a = 9'b000000101;
-//    b = 9'b000111100;
-//    c = 9'b001001001;
-//    d = 9'b100000000;
-//    #5
-//    s = 2'b11;
-//    a = 9'b000000101;
-//    b = 9'b000111100;
-//    c = 9'b001001001;
-//    d = 9'b100000000;
-//    #5 $finish;
+   initial begin
+   s = 2'b00;
+   a = 9'b000000101;
+   b = 9'b000111100;
+   c = 9'b001001001;
+   d = 9'b100000000;
+   #5
+   s = 2'b01;
+   a = 9'b000000101;
+   b = 9'b000111100;
+   c = 9'b001001001;
+   d = 9'b100000000;
+   #5
+   s = 2'b10;
+   a = 9'b000000101;
+   b = 9'b000111100;
+   c = 9'b001001001;
+   d = 9'b100000000;
+   #5
+   s = 2'b11;
+   a = 9'b000000101;
+   b = 9'b000111100;
+   c = 9'b001001001;
+   d = 9'b100000000;
+   #5 $finish;
 
-//    end
-//endmodule
+   end
+endmodule
 
 module mux_8_1(
     input wire [2:0] switch,
@@ -449,87 +449,87 @@ module mux_8_1(
 endmodule
 
 //testbench
-//module mux_8_1_tb();
-//reg [2:0] s;
-//reg [8:0] a;
-//reg [8:0] b;
-//reg [8:0] c;
-//reg [8:0] d;
-//reg [8:0] e;
-//reg [8:0] f;
-//reg [8:0] g;
-//reg [8:0] h;
-//wire [8:0] out;
+module mux_8_1_tb();
+reg [2:0] s;
+reg [8:0] a;
+reg [8:0] b;
+reg [8:0] c;
+reg [8:0] d;
+reg [8:0] e;
+reg [8:0] f;
+reg [8:0] g;
+reg [8:0] h;
+wire [8:0] out;
 
-//mux_8_1 mux1(
-//.switch(s),
-//.A(a),
-//.B(b),
-//.C(c),
-//.D(d),
-//.E(e),
-//.F(f),
-//.G(g),
-//.H(h),
-//.out(out));
+mux_8_1 mux1(
+.switch(s),
+.A(a),
+.B(b),
+.C(c),
+.D(d),
+.E(e),
+.F(f),
+.G(g),
+.H(h),
+.out(out));
     
-//    initial begin
-//    s = 3'b000;
-//    a = 9'b000000101;
-//    b = 9'b000111100;
-//    c = 9'b001001001;
-//    d = 9'b100110000;
-//    e = 9'b010000101;
-//    f = 9'b010111100;
-//    g = 9'b011001001;
-//    h = 9'b111000000;
-//    #5
-//    s = 3'b001;
-//    #5
-//    s = 3'b010;
-//    #5
-//    s = 3'b011;
-//    #5
-//    s = 3'b100;
-//    #5
-//    s = 3'b101;
-//    #5
-//    s = 3'b110;
-//    #5
-//    s = 3'b111;
-//    #5 $finish;
+   initial begin
+   s = 3'b000;
+   a = 9'b000000101;
+   b = 9'b000111100;
+   c = 9'b001001001;
+   d = 9'b100110000;
+   e = 9'b010000101;
+   f = 9'b010111100;
+   g = 9'b011001001;
+   h = 9'b111000000;
+   #5
+   s = 3'b001;
+   #5
+   s = 3'b010;
+   #5
+   s = 3'b011;
+   #5
+   s = 3'b100;
+   #5
+   s = 3'b101;
+   #5
+   s = 3'b110;
+   #5
+   s = 3'b111;
+   #5 $finish;
 
-//    end
-//endmodule
+   end
+endmodule
 
-//module mux_16_1(
-//    input wire [3:0] switch,
-//    input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,
-//    output reg [8:0] out);
+module mux_16_1(
+   input wire [3:0] switch,
+   input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,
+   output reg [8:0] out);
            
-//    always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin
-//        case (switch)
-//            4'b0000 : out = A;
-//            4'b0001 : out = B;
-//            4'b0010 : out = C;
-//            4'b0011 : out = D;
-//            4'b0100 : out = E;
-//            4'b0101 : out = F;
-//            4'b0110 : out = G;
-//            4'b0111 : out = H;
-//            4'b1000 : out = I;
-//            4'b1001 : out = J;
-//            4'b1010 : out = K;
-//            4'b1011 : out = L;
-//            4'b1100 : out = M;
-//            4'b1101 : out = N;
-//            4'b1110 : out = O;
-//            4'b1111 : out = P;
-//            default : out = 9'bxxxxxxxxx;
-//        endcase
-//    end
+   always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin
+       case (switch)
+           4'b0000 : out = A;
+           4'b0001 : out = B;
+           4'b0010 : out = C;
+           4'b0011 : out = D;
+           4'b0100 : out = E;
+           4'b0101 : out = F;
+           4'b0110 : out = G;
+           4'b0111 : out = H;
+           4'b1000 : out = I;
+           4'b1001 : out = J;
+           4'b1010 : out = K;
+           4'b1011 : out = L;
+           4'b1100 : out = M;
+           4'b1101 : out = N;
+           4'b1110 : out = O;
+           4'b1111 : out = P;
+           default : out = 9'bxxxxxxxxx;
+       endcase
+   end
 
-//endmodule
+endmodule
 
 module nor_1bit(
     input wire A,
@@ -542,32 +542,32 @@ module nor_1bit(
 endmodule
 
 //testbench
-//module nor_1bit_tb();
-//reg a;
-//reg b;
-//wire c;
+module nor_1bit_tb();
+reg a;
+reg b;
+wire c;
 
-//nor_1bit nor0(
-//.A(a),
-//.B(b),
-//.C(c));
+nor_1bit nor0(
+.A(a),
+.B(b),
+.C(c));
     
-//    initial begin
-//    a = 0;
-//    b = 0;
-//    #5
-//    a = 0;
-//    b = 1;
-//    #5
-//    a = 1;
-//    b = 0;
-//    #5
-//    a = 1;
-//    b = 1;
-//    #5 $finish;
+   initial begin
+   a = 0;
+   b = 0;
+   #5
+   a = 0;
+   b = 1;
+   #5
+   a = 1;
+   b = 0;
+   #5
+   a = 1;
+   b = 1;
+   #5 $finish;
 
-//    end
-//endmodule
+   end
+endmodule
 
 module nor_9bit(
     input wire [8:0] A,
@@ -622,38 +622,38 @@ module nor_9bit(
 endmodule
 
 //testbench
-//module nor_9bit_tb();
-//reg [8:0] a;
-//reg [8:0] b;
-//wire [8:0] c;
+module nor_9bit_tb();
+reg [8:0] a;
+reg [8:0] b;
+wire [8:0] c;
 
-//nor_9bit nor0(
-//.A(a),
-//.B(b),
-//.C(c));
+nor_9bit nor0(
+.A(a),
+.B(b),
+.C(c));
     
-//    initial begin
-//    a = 9'b000000000;
-//    b = 9'b000000000;
-//    #5
-//    a = 9'b000000000;
-//    b = 9'b000000001;
-//    #5
-//    a = 9'b000000001;
-//    b = 9'b000000000;
-//    #5
-//    a = 9'b000000001;
-//    b = 9'b000000001;
-//    #5
-//    a = 9'b000100001;
-//    b = 9'b000000001;
-//    #5
-//    a = 9'b000100001;
-//    b = 9'b000100001;
-//    #5 $finish;
+   initial begin
+   a = 9'b000000000;
+   b = 9'b000000000;
+   #5
+   a = 9'b000000000;
+   b = 9'b000000001;
+   #5
+   a = 9'b000000001;
+   b = 9'b000000000;
+   #5
+   a = 9'b000000001;
+   b = 9'b000000001;
+   #5
+   a = 9'b000100001;
+   b = 9'b000000001;
+   #5
+   a = 9'b000100001;
+   b = 9'b000100001;
+   #5 $finish;
 
-//    end
-//endmodule
+   end
+endmodule
 
 
 module not_1bit(
@@ -665,22 +665,22 @@ module not_1bit(
 endmodule
 
 //testbench
-//module not_1bit_tb();
-//reg a;
-//wire b;
+module not_1bit_tb();
+reg a;
+wire b;
 
-//not_1bit not0(
-//.A(a),
-//.B(b));
+not_1bit not0(
+.A(a),
+.B(b));
     
-//    initial begin
-//    a = 0;
-//    #5
-//    a = 1;
-//    #5 $finish;
+   initial begin
+   a = 0;
+   #5
+   a = 1;
+   #5 $finish;
 
-//    end
-//endmodule
+   end
+endmodule
 
 module not_9bit(
     input wire [8:0] A,
@@ -725,33 +725,33 @@ module not_9bit(
 endmodule
 
 //testbench
-//module not_9bit_tb();
-//reg [8:0] a;
-//wire [8:0] b;
+module not_9bit_tb();
+reg [8:0] a;
+wire [8:0] b;
 
-//    not_9bit not0(
-//        .A(a),
-//        .B(b));
+   not_9bit not0(
+       .A(a),
+       .B(b));
     
-//    initial begin
-//    a = 9'b000000000;
-//    #5
-//    a = 9'b000000001;
-//    #5
-//    a = 9'b000111000;
-//    #5
-//    a = 9'b010101010;
-//    #5
-//    a = 9'b101010101;
-//    #5
-//    a = 9'b111111111;
-//    #5
-//    a = 9'b100000001;
-//    #5 $finish;
+   initial begin
+   a = 9'b000000000;
+   #5
+   a = 9'b000000001;
+   #5
+   a = 9'b000111000;
+   #5
+   a = 9'b010101010;
+   #5
+   a = 9'b101010101;
+   #5
+   a = 9'b111111111;
+   #5
+   a = 9'b100000001;
+   #5 $finish;
 
-//    end
+   end
 
-//endmodule
+endmodule
 
 module or_1bit(
     input wire A,
@@ -763,33 +763,33 @@ module or_1bit(
 endmodule
 
 //testbench
-//module or_1bit_tb();
-//reg a;
-//reg b;
-//wire c;
+module or_1bit_tb();
+reg a;
+reg b;
+wire c;
 
-//    or_1bit or0(
-//        .A(a),
-//        .B(b),
-//        .C(c));
+   or_1bit or0(
+       .A(a),
+       .B(b),
+       .C(c));
     
-//    initial begin
-//    a = 0;
-//    b = 0;
-//    #5
-//    a = 0;
-//    b = 1;
-//    #5
-//    a = 1;
-//    b = 0;
-//    #5
-//    a = 1;
-//    b = 1;
-//    #5 $finish;
+   initial begin
+   a = 0;
+   b = 0;
+   #5
+   a = 0;
+   b = 1;
+   #5
+   a = 1;
+   b = 0;
+   #5
+   a = 1;
+   b = 1;
+   #5 $finish;
 
-//    end
+   end
 
-//endmodule
+endmodule
 
 module or_9bit(
     input wire [8:0] A,
@@ -844,48 +844,48 @@ module or_9bit(
 endmodule
 
 //testbench
-//module or_9bit_tb();
-//reg [8:0] a;
-//reg [8:0] b;
-//wire [8:0] c;
+module or_9bit_tb();
+reg [8:0] a;
+reg [8:0] b;
+wire [8:0] c;
 
-//    or_9bit tb0(
-//        .A(a),
-//        .B(b),
-//        .C(c));
+   or_9bit tb0(
+       .A(a),
+       .B(b),
+       .C(c));
     
-//    initial begin
-//    a = 9'b000000000;
-//    b = 9'b000000000;
-//    #5
-//    a = 9'b111111111;
-//    b = 9'b111111111;
-//    #5
-//    a = 9'b111111111;
-//    b = 9'b000000000;
-//    #5
-//    a = 9'b000000000;
-//    b = 9'b111111111;
-//    #5
-//    a = 9'b000000000;
-//    b = 9'b111111111;
-//    #5
-//    a = 9'b010101010;
-//    b = 9'b111111111;
-//    #5
-//    a = 9'b010101010;
-//    b = 9'b101010101;
-//    #5
-//    a = 9'b000011111;
-//    b = 9'b111111111;
-//    #5
-//    a = 9'b000000000;
-//    b = 9'b000010000;
-//    #5 $finish;
+   initial begin
+   a = 9'b000000000;
+   b = 9'b000000000;
+   #5
+   a = 9'b111111111;
+   b = 9'b111111111;
+   #5
+   a = 9'b111111111;
+   b = 9'b000000000;
+   #5
+   a = 9'b000000000;
+   b = 9'b111111111;
+   #5
+   a = 9'b000000000;
+   b = 9'b111111111;
+   #5
+   a = 9'b010101010;
+   b = 9'b111111111;
+   #5
+   a = 9'b010101010;
+   b = 9'b101010101;
+   #5
+   a = 9'b000011111;
+   b = 9'b111111111;
+   #5
+   a = 9'b000000000;
+   b = 9'b000010000;
+   #5 $finish;
 
-//    end
+   end
 
-//endmodule
+endmodule
 
 module register(input wire clk, reset,
                 input wire [1:0] En,
@@ -907,61 +907,61 @@ module register(input wire clk, reset,
 endmodule
 
 //testbench
-//module register_tb();
-//reg clk,reset;
-//reg [1:0] En;
-//reg [8:0] Din;
-//wire [8:0] Dout;
+module register_tb();
+reg clk,reset;
+reg [1:0] En;
+reg [8:0] Din;
+wire [8:0] Dout;
 
-//    register tb0(
-//        .clk(clk),
-//        .reset(reset),
-//        .En(En),
-//        .Din(Din),
-//        .Dout(Dout));
+   register tb0(
+       .clk(clk),
+       .reset(reset),
+       .En(En),
+       .Din(Din),
+       .Dout(Dout));
     
-//    initial begin
-//    clk = 0;
-//    reset = 0;
-//    En = 2'b00;
-//    Din = 9'b000000000;
-//    #5
-//    clk = 1;
-//    #5
-//    clk = 0;
-//    reset = 0;
-//    En = 2'b00;
-//    Din = 9'b010101010;
-//    #5
-//    clk = 1;
-//    #5
-//    clk = 0;
-//    reset = 1;
-//    En = 2'b00;
-//    Din = 9'b010101010;
-//    #5
-//    clk = 1;
-//    #5
-//    clk = 0;
-//    reset = 0;
-//    En = 2'b01;
-//    Din = 9'b101010101;
-//    #5
-//    clk = 1;
-//    #5
-//    clk = 0;
-//    reset = 0;
-//    En = 2'b00;
-//    Din = 9'b000011111;
-//    #5
-//    clk = 1;
-//    #5
-//    clk = 0;
-//    #5 $finish;
+   initial begin
+   clk = 0;
+   reset = 0;
+   En = 2'b00;
+   Din = 9'b000000000;
+   #5
+   clk = 1;
+   #5
+   clk = 0;
+   reset = 0;
+   En = 2'b00;
+   Din = 9'b010101010;
+   #5
+   clk = 1;
+   #5
+   clk = 0;
+   reset = 1;
+   En = 2'b00;
+   Din = 9'b010101010;
+   #5
+   clk = 1;
+   #5
+   clk = 0;
+   reset = 0;
+   En = 2'b01;
+   Din = 9'b101010101;
+   #5
+   clk = 1;
+   #5
+   clk = 0;
+   reset = 0;
+   En = 2'b00;
+   Din = 9'b000011111;
+   #5
+   clk = 1;
+   #5
+   clk = 0;
+   #5 $finish;
 
-//    end
+   end
 
-//endmodule 
+endmodule 
     
 module shift_logical_left(
     input wire [8:0] A,
@@ -972,33 +972,33 @@ module shift_logical_left(
 endmodule
 
 //testbench
-//module shift_logical_left_tb();
-//reg [8:0] a;
-//wire [8:0] b;
+module shift_logical_left_tb();
+reg [8:0] a;
+wire [8:0] b;
 
-//    shift_logical_left tb0(
-//        .A(a),
-//        .B(b));
+   shift_logical_left tb0(
+       .A(a),
+       .B(b));
     
-//    initial begin
-//    a = 9'b000000000;
-//    #5
-//    a = 9'b000000001;
-//    #5
-//    a = 9'b000111000;
-//    #5
-//    a = 9'b010101010;
-//    #5
-//    a = 9'b101010101;
-//    #5
-//    a = 9'b111111111;
-//    #5
-//    a = 9'b100000001;
-//    #5 $finish;
+   initial begin
+   a = 9'b000000000;
+   #5
+   a = 9'b000000001;
+   #5
+   a = 9'b000111000;
+   #5
+   a = 9'b010101010;
+   #5
+   a = 9'b101010101;
+   #5
+   a = 9'b111111111;
+   #5
+   a = 9'b100000001;
+   #5 $finish;
 
-//    end
+   end
 
-//endmodule
+endmodule
 
 module shift_logical_right(
     input wire [8:0] A,
@@ -1009,33 +1009,33 @@ module shift_logical_right(
 endmodule
 
 //testbench
-//module shift_logical_right_tb();
-//reg [8:0] a;
-//wire [8:0] b;
+module shift_logical_right_tb();
+reg [8:0] a;
+wire [8:0] b;
 
-//    shift_logical_right tb0(
-//        .A(a),
-//        .B(b));
+   shift_logical_right tb0(
+       .A(a),
+       .B(b));
     
-//    initial begin
-//    a = 9'b000000000;
-//    #5
-//    a = 9'b000000001;
-//    #5
-//    a = 9'b000111000;
-//    #5
-//    a = 9'b010101010;
-//    #5
-//    a = 9'b101010101;
-//    #5
-//    a = 9'b111111111;
-//    #5
-//    a = 9'b100000001;
-//    #5 $finish;
+   initial begin
+   a = 9'b000000000;
+   #5
+   a = 9'b000000001;
+   #5
+   a = 9'b000111000;
+   #5
+   a = 9'b010101010;
+   #5
+   a = 9'b101010101;
+   #5
+   a = 9'b111111111;
+   #5
+   a = 9'b100000001;
+   #5 $finish;
 
-//    end
+   end
 
-//endmodule
+endmodule
 
 module sub_9bit(
     input wire [8:0] A,
@@ -1057,48 +1057,49 @@ module sub_9bit(
 endmodule
 
 //testbench
-//module sub_9bit_tb();
-//reg [8:0] a;
-//reg [8:0] b;
-//wire [8:0] c;
+module sub_9bit_tb();
+reg [8:0] a;
+reg [8:0] b;
+wire [8:0] c;
 
-//    sub_9bit tb0(
-//        .A(a),
-//        .B(b),
-//        .C(c));
+   sub_9bit tb0(
+       .A(a),
+       .B(b),
+       .C(c));
     
-//    initial begin
-//    a = 9'b000000000;
-//    b = 9'b000000000;
-//    #5
-//    a = 9'b111111111;
-//    b = 9'b111111111;
-//    #5
-//    a = 9'b111111111;
-//    b = 9'b000000000;
-//    #5
-//    a = 9'b000000000;
-//    b = 9'b111111111;
-//    #5
-//    a = 9'b000000000;
-//    b = 9'b111111111;
-//    #5
-//    a = 9'b010101010;
-//    b = 9'b111111111;
-//    #5
-//    a = 9'b010101010;
-//    b = 9'b101010101;
-//    #5
-//    a = 9'b000011111;
-//    b = 9'b111111111;
-//    #5
-//    a = 9'b000000000;
-//    b = 9'b000010000;
-//    #5 $finish;
+   initial begin
+   a = 9'b000000000;
+   b = 9'b000000000;
+   #5
+   a = 9'b111111111;
+   b = 9'b111111111;
+   #5
+   a = 9'b111111111;
+   b = 9'b000000000;
+   #5
+   a = 9'b000000000;
+   b = 9'b111111111;
+   #5
+   a = 9'b000000000;
+   b = 9'b111111111;
+   #5
+   a = 9'b010101010;
+   b = 9'b111111111;
+   #5
+   a = 9'b010101010;
+   b = 9'b101010101;
+   #5
+   a = 9'b000011111;
+   b = 9'b111111111;
+   #5
+   a = 9'b000000000;
+   b = 9'b000010000;
+   #5
+   $finish;
 
-//    end
+   end
 
-//endmodule
+endmodule
 
 module twos_compliment_9bit(
     input wire [8:0] A,
@@ -1119,30 +1120,31 @@ module twos_compliment_9bit(
 endmodule
 
 //testbench
-//module twos_compliment_tb();
-//reg [8:0] a;
-//wire [8:0] b;
+module twos_compliment_tb();
+reg [8:0] a;
+wire [8:0] b;
 
-//    twos_compliment_9bit tb0(
-//        .A(a),
-//        .B(b));
+   twos_compliment_9bit tb0(
+       .A(a),
+       .B(b));
     
-//    initial begin
-//    a = 9'b000000000;
-//    #5
-//    a = 9'b000000001;
-//    #5
-//    a = 9'b000111000;
-//    #5
-//    a = 9'b010101010;
-//    #5
-//    a = 9'b101010101;
-//    #5
-//    a = 9'b111111111;
-//    #5
-//    a = 9'b100000001;
-//    #5 $finish;
+   initial begin
+   a = 9'b000000000;
+   #5
+   a = 9'b000000001;
+   #5
+   a = 9'b000111000;
+   #5
+   a = 9'b010101010;
+   #5
+   a = 9'b101010101;
+   #5
+   a = 9'b111111111;
+   #5
+   a = 9'b100000001;
+   #5
+   $finish;
 
-//    end
+   end
 
-//endmodule
\ No newline at end of file
+endmodule
\ No newline at end of file
diff --git a/lab2CA.srcs/sources_1/new/FetchUnit.v b/lab2CA.srcs/sources_1/new/FetchUnit.v
index 8937c7c..a7ccaf9 100644
--- a/lab2CA.srcs/sources_1/new/FetchUnit.v
+++ b/lab2CA.srcs/sources_1/new/FetchUnit.v
@@ -85,7 +85,8 @@ FetchUnit fetchUnit0(
     #5
     #5
     #5
-    #5 $finish;
+    #5
+    $finish;
 
     end
 endmodule
\ No newline at end of file