diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 7660bf8..ae8a1a9 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,25 +17,26 @@ This means code written to parse this file will need to be revisited each subseq - - + + - - - - - + + + + + + - + - + - + - +
diff --git a/lab2CA.runs/.jobs/vrs_config_10.xml b/lab2CA.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..99b94d7 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_11.xml b/lab2CA.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..99b94d7 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_12.xml b/lab2CA.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..99b94d7 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_13.xml b/lab2CA.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..99b94d7 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_9.xml b/lab2CA.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..99b94d7 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/synth_1/ALU.vds b/lab2CA.runs/synth_1/ALU.vds index e37141e..7152285 100644 --- a/lab2CA.runs/synth_1/ALU.vds +++ b/lab2CA.runs/synth_1/ALU.vds @@ -2,8 +2,8 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 12:49:31 2019 -# Process ID: 18228 +# Start of session at: Sat Feb 16 13:03:34 2019 +# Process ID: 11092 # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1 # Command line: vivado.exe -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/ALU.vds @@ -15,9 +15,9 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 8848 +INFO: Helper process launched with PID 18316 --------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 363.309 ; gain = 101.105 +Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 363.020 ; gain = 100.695 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3] INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15] @@ -25,25 +25,40 @@ INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/JoseIgnacio/CA Lab INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15] WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:14] -INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:483] -WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:490] -INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:502] -INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:319] -INFO: [Synth 8-6157] synthesizing module 'not_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:311] -INFO: [Synth 8-6155] done synthesizing module 'not_1bit' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:311] -INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:319] -WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:512] -INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:502] -ERROR: [Synth 8-448] named port connection 'C' does not exist for instance 'two_comp0' of module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:492] -WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:494] -ERROR: [Synth 8-6156] failed synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:483] +INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:480] +INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:499] +INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316] +INFO: [Synth 8-6157] synthesizing module 'not_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:308] +INFO: [Synth 8-6155] done synthesizing module 'not_1bit' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:308] +INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316] +WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:509] +INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:499] +WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:491] +INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (6#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:480] +INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:367] +INFO: [Synth 8-6157] synthesizing module 'or_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:358] +INFO: [Synth 8-6155] done synthesizing module 'or_1bit' (7#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:358] +INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (8#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:367] +INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:256] +INFO: [Synth 8-6157] synthesizing module 'nor_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:247] +INFO: [Synth 8-6155] done synthesizing module 'nor_1bit' (9#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:247] +INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (10#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:256] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:35] +INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:105] +INFO: [Synth 8-6157] synthesizing module 'and_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:96] +INFO: [Synth 8-6155] done synthesizing module 'and_1bit' (11#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:96] +INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (12#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:105] +ERROR: [Synth 8-448] named port connection 'Cin' does not exist for instance 'and0' of module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:38] +ERROR: [Synth 8-448] named port connection 'Sum' does not exist for instance 'and0' of module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:39] +INFO: [Synth 8-6157] synthesizing module 'shift_logical_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:462] +ERROR: [Synth 8-6156] failed synthesizing module 'shift_logical_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:462] ERROR: [Synth 8-6156] failed synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3] --------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 419.434 ; gain = 157.230 +Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 419.512 ; gain = 157.188 --------------------------------------------------------------------------------- synthesize failed INFO: [Common 17-83] Releasing license: Synthesis -14 Infos, 4 Warnings, 0 Critical Warnings and 4 Errors encountered. +28 Infos, 4 Warnings, 0 Critical Warnings and 5 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Vivado Synthesis failed -INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 12:49:41 2019... +INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 13:03:44 2019... diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml index 8920cfc..dd771bf 100644 --- a/lab2CA.runs/synth_1/gen_run.xml +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/lab2CA.runs/synth_1/vivado.jou b/lab2CA.runs/synth_1/vivado.jou index 4f75250..38475ab 100644 --- a/lab2CA.runs/synth_1/vivado.jou +++ b/lab2CA.runs/synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 12:49:31 2019 -# Process ID: 18228 +# Start of session at: Sat Feb 16 13:03:34 2019 +# Process ID: 11092 # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1 # Command line: vivado.exe -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/ALU.vds diff --git a/lab2CA.runs/synth_1/vivado.pb b/lab2CA.runs/synth_1/vivado.pb index 17e8f1a..c77a056 100644 Binary files a/lab2CA.runs/synth_1/vivado.pb and b/lab2CA.runs/synth_1/vivado.pb differ diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index 1bb53d4..001f115 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -164,9 +164,6 @@ module gen_clock(); end endmodule - -//To enable register, input 00 to En, register is always outputting contents - module mux_2_1(input wire switch, input wire [8:0] A,B, output reg [8:0] out); @@ -426,13 +423,13 @@ module register(input wire clk, reset, always @(posedge clk) begin if (reset == 1'b1) begin - Dout <= 9'b000000000; + Dout = 9'b000000000; end else if (En == 2'b00) begin - Dout <= Din; + Dout = Din; end else begin - Dout <= "ZZZZZZZZZ"; + Dout = "ZZZZZZZZZ"; end end @@ -489,7 +486,7 @@ module sub_9bit( twos_compliment_9bit two_comp0( .A(B), - .C(D)); + .B(D)); add_9bit add0( .A(A), diff --git a/vivado.jou b/vivado.jou index 08d690b..e100eaa 100644 --- a/vivado.jou +++ b/vivado.jou @@ -2,10 +2,10 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 12:39:38 2019 -# Process ID: 15076 +# Start of session at: Sat Feb 16 12:51:25 2019 +# Process ID: 14124 # Current directory: C:/Users/JoseIgnacio/CA Lab -# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16632 C:\Users\JoseIgnacio\CA Lab\lab2CA.xpr +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent19396 C:\Users\JoseIgnacio\CA Lab\lab2CA.xpr # Log file: C:/Users/JoseIgnacio/CA Lab/vivado.log # Journal file: C:/Users/JoseIgnacio/CA Lab\vivado.jou #----------------------------------------------------------- diff --git a/vivado_15076.backup.jou b/vivado_15076.backup.jou new file mode 100644 index 0000000..08d690b --- /dev/null +++ b/vivado_15076.backup.jou @@ -0,0 +1,29 @@ +#----------------------------------------------------------- +# Vivado v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Feb 16 12:39:38 2019 +# Process ID: 15076 +# Current directory: C:/Users/JoseIgnacio/CA Lab +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16632 C:\Users\JoseIgnacio\CA Lab\lab2CA.xpr +# Log file: C:/Users/JoseIgnacio/CA Lab/vivado.log +# Journal file: C:/Users/JoseIgnacio/CA Lab\vivado.jou +#----------------------------------------------------------- +start_gui +open_project {C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr} +update_compile_order -fileset sources_1 +reset_run synth_1 +launch_runs synth_1 -jobs 4 +wait_on_run synth_1 +reset_run synth_1 +launch_runs synth_1 -jobs 4 +wait_on_run synth_1 +reset_run synth_1 +launch_runs synth_1 -jobs 4 +wait_on_run synth_1 +reset_run synth_1 +launch_runs synth_1 -jobs 4 +wait_on_run synth_1 +reset_run synth_1 +launch_runs synth_1 -jobs 4 +wait_on_run synth_1