diff --git a/.gitignore b/.gitignore index 7134ebe..60dd983 100644 --- a/.gitignore +++ b/.gitignore @@ -84,3 +84,9 @@ !*.elf !*.bmm !*.xmp + +######## +# Custom +######## +# We want markdown files +!*.md \ No newline at end of file diff --git a/README.md b/README.md new file mode 100644 index 0000000..d4c4a24 --- /dev/null +++ b/README.md @@ -0,0 +1,17 @@ +# ECE 3570 Lab + +## Fixes To Be Implemented + +* Get rid of the double zero for the enable on the registers + * Make decoder for it +* Redo simulations with other registers using internal signals +* Fix simulation waveforms for Registers, as we are currently changing inputs too quickly (multiple times within a clock cycle) +* Only two registers are being written to, first two within simulation is not being written to +* Need to allow for signed numbers +* Remove subtraction from ALU +* Have arithmetic shift left and right +* Uncomment all testbenches (We can have multiple testbenches active at once) +* Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only +* Comparator needed +* Make subtraction more efficient +* Need to verify that FetchUnit is working properly as Martin had some concerns that it probably wasn't functioning properly \ No newline at end of file diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 3f15c00..50c4710 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -24,54 +24,54 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + - + - + - + - + - + - + - - + + - + @@ -85,14 +85,19 @@ This means code written to parse this file will need to be revisited each subseq - + - + + + + + +
diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml index db16262..faca896 100644 --- a/lab2CA.runs/impl_1/gen_run.xml +++ b/lab2CA.runs/impl_1/gen_run.xml @@ -1,74 +1,55 @@ - - - - - - - - - - - - - - - - + + + - - - - - - - - + - - + - - - - + - - - - - - - - - - - - + + + + + + + + + + + + + + + + + diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml index 2ceb5d4..60496de 100644 --- a/lab2CA.runs/synth_1/gen_run.xml +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -1,14 +1,11 @@ - + - - - diff --git a/lab2CA.sim/sim_1/behav/xsim/decoder_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/decoder_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/decoder_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/decoder_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/decoder_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/decoder_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou index d926d13..dcabd11 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou @@ -2,8 +2,8 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 20 11:30:13 2019 -# Process ID: 10344 +# Start of session at: Wed Feb 27 11:47:34 2019 +# Process ID: 6784 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim # Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11568.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_11568.backup.jou deleted file mode 100644 index 9130792..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_11568.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 20 10:48:52 2019 -# Process ID: 11568 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11844.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_11844.backup.jou deleted file mode 100644 index bd6c6c5..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_11844.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 20 10:53:42 2019 -# Process ID: 11844 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_5680.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_1408.backup.jou similarity index 92% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_5680.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_1408.backup.jou index 1450c74..29a40e1 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_5680.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_1408.backup.jou @@ -2,8 +2,8 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 17:35:22 2019 -# Process ID: 5680 +# Start of session at: Wed Feb 27 11:43:09 2019 +# Process ID: 1408 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim # Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11820.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_14864.backup.jou similarity index 77% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_11820.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_14864.backup.jou index 783e38b..6e967bd 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_11820.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_14864.backup.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 17:37:48 2019 -# Process ID: 11820 +# Start of session at: Wed Feb 27 11:39:16 2019 +# Process ID: 14864 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_16620.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_16620.backup.jou new file mode 100644 index 0000000..11d2a60 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_16620.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Thu Feb 21 14:46:02 2019 +# Process ID: 16620 +# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/REPOSITORIES/Educational/Western -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_13504.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou similarity index 77% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_13504.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou index 1a02c75..bbb2a8d 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_13504.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 20 11:27:03 2019 -# Process ID: 13504 +# Start of session at: Wed Feb 27 11:36:59 2019 +# Process ID: 7276 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index 4ca6d1d..5862552 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xelab.pb and b/lab2CA.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..3dc91ba --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "decoder_tb_behav" "xil_defaultlib.decoder_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..c836e28 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/obj/xsim_1.c @@ -0,0 +1,108 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[14] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 14; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/decoder_tb_behav/xsim.reloc", (void **)funcTab, 14); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/decoder_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/decoder_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/decoder_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/decoder_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/decoder_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..24e7748 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl similarity index 55% rename from lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl rename to lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl index 051e4df..c375aa4 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl @@ -1,6 +1,6 @@ -webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Wed Feb 20 11:22:46 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Wed Feb 27 11:44:18 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" @@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "21" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" @@ -22,21 +22,11 @@ webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" webtalk_register_client -client xsim -webtalk_add_data -client xsim -key File_Counter -value "3" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Simulation_Image_Code -value "69 KB" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Image_Data -value "4 KB" -context "xsim\\usage" -webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Total_Processes -value "45" -context "xsim\\usage" -webtalk_add_data -client xsim -key Total_Instances -value "15" -context "xsim\\usage" -webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage" -webtalk_add_data -client xsim -key Compiler_Time -value "0.78_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Compiler_Memory -value "41208_KB" -context "xsim\\usage" -webtalk_transmit -clientid 1004531601 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "25 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6064_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1469323063 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/xsim.mem new file mode 100644 index 0000000..951ac9b Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/xsim.mem index 3101817..d79f70c 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/xsim.mem and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/obj/xsim_1.c index c143067..828618b 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/obj/xsim_1.c +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/obj/xsim_1.c @@ -46,15 +46,14 @@ typedef void (*funcp)(char *, char *); extern int main(int, char**); extern void execute_2(char*, char *); extern void execute_3(char*, char *); -extern void execute_17(char*, char *); +extern void execute_19(char*, char *); extern void execute_31(char*, char *); extern void execute_32(char*, char *); extern void execute_33(char*, char *); extern void execute_34(char*, char *); extern void execute_35(char*, char *); extern void execute_36(char*, char *); -extern void execute_22(char*, char *); -extern void execute_23(char*, char *); +extern void execute_37(char*, char *); extern void execute_24(char*, char *); extern void execute_25(char*, char *); extern void execute_26(char*, char *); @@ -63,23 +62,23 @@ extern void execute_28(char*, char *); extern void execute_29(char*, char *); extern void execute_30(char*, char *); extern void execute_6(char*, char *); -extern void execute_14(char*, char *); -extern void execute_19(char*, char *); -extern void execute_20(char*, char *); +extern void execute_8(char*, char *); +extern void execute_16(char*, char *); extern void execute_21(char*, char *); -extern void execute_37(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); extern void execute_38(char*, char *); extern void execute_39(char*, char *); extern void execute_40(char*, char *); extern void execute_41(char*, char *); +extern void execute_42(char*, char *); extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); -extern void transaction_10(char*, char*, unsigned, unsigned, unsigned); -funcp funcTab[30] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_17, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_6, (funcp)execute_14, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_10}; -const int NumRelocateId= 30; +funcp funcTab[29] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_19, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_6, (funcp)execute_8, (funcp)execute_16, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 29; void relocate(char *dp) { - iki_relocate(dp, "xsim.dir/regFile_tb_behav/xsim.reloc", (void **)funcTab, 30); + iki_relocate(dp, "xsim.dir/regFile_tb_behav/xsim.reloc", (void **)funcTab, 29); /*Populate the transaction function pointer field in the whole net structure */ } diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml index d8948fc..c070826 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -1,14 +1,14 @@ - +
- + - + @@ -35,8 +35,8 @@
- - + +
diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl index 5396adb..625d097 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl @@ -1,6 +1,6 @@ webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Wed Feb 20 11:30:23 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Wed Feb 27 12:02:56 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" @@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "7" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "17" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" @@ -22,21 +22,11 @@ webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" webtalk_register_client -client xsim -webtalk_add_data -client xsim -key File_Counter -value "3" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Simulation_Image_Code -value "73 KB" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Image_Data -value "4 KB" -context "xsim\\usage" -webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Total_Processes -value "37" -context "xsim\\usage" -webtalk_add_data -client xsim -key Total_Instances -value "9" -context "xsim\\usage" -webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage" -webtalk_add_data -client xsim -key Compiler_Time -value "0.65_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Compiler_Memory -value "38732_KB" -context "xsim\\usage" -webtalk_transmit -clientid 3938710361 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "70 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.08_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6104_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1751969665 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/xsim.mem index 453a28e..14fbda9 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/xsim.mem and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb index 11bc220..bf58768 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb and b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v index 604c2f5..664cd6e 100644 --- a/lab2CA.srcs/sources_1/new/ALU.v +++ b/lab2CA.srcs/sources_1/new/ALU.v @@ -63,46 +63,46 @@ module ALU( endmodule //testbench -//module alu_tb(); -//reg [8:0] a; -//reg [8:0] b; -//reg [2:0] c; -//wire [8:0] d; +module alu_tb(); + reg [8:0] a; + reg [8:0] b; + reg [2:0] c; + wire [8:0] d; -//ALU alu0( -//.operand0(a), -//.operand1(b), -//.opcode(c), -//.result(d)); + ALU alu0( + .operand0(a), + .operand1(b), + .opcode(c), + .result(d)); -// initial begin -// a = 9'b000000111; -// b = 9'b000111000; -// c = 3'b000; -// #5 -// a = 9'b000011000; -// b = 9'b000011000; -// c = 3'b001; -// #5 -// a = 9'b101010100; -// b = 9'b010101011; -// c = 3'b010; -// #5 -// a = 9'b101010100; -// b = 9'b010101000; -// c = 3'b011; -// #5 -// a = 9'b000110000; -// b = 9'b000111000; -// c = 3'b100; -// #5 -// a = 9'b01011000; -// c = 3'b101; -// #5 -// a = 9'b00001010; -// c = 3'b110; -// #5 -// #5 $finish; + initial begin + a = 9'b000000111; + b = 9'b000111000; + c = 3'b000; + #5 + a = 9'b000011000; + b = 9'b000011000; + c = 3'b001; + #5 + a = 9'b101010100; + b = 9'b010101011; + c = 3'b010; + #5 + a = 9'b101010100; + b = 9'b010101000; + c = 3'b011; + #5 + a = 9'b000110000; + b = 9'b000111000; + c = 3'b100; + #5 + a = 9'b01011000; + c = 3'b101; + #5 + a = 9'b00001010; + c = 3'b110; + #5 + $finish; -// end -//endmodule + end +endmodule diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index fefe221..a4ea6c7 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -13,42 +13,45 @@ module add_1bit( endmodule //testbench -//module add1bit_tb(); -//reg v; -//reg w; -//reg x; -//wire y; -//wire z; +module add1bit_tb(); + reg v; + reg w; + reg x; + wire y; + wire z; -//add_1bit add0( -// .A(v), -// .B(w), -// .Cin(x), -// .S(y), -// .Cout(z)); - -// initial begin -// v = 0; -// w = 0; -// x = 0; -// #5 -// v = 0; -// w = 1; -// x = 0; -// #5 -// v = 0; -// w = 0; -// x = 1; -// #5 -// v = 1; -// w = 1; -// x = 0; -// #5 -// v = 1; -// w = 1; -// x = 1; -// end -//endmodule + add_1bit tb0( + .A(v), + .B(w), + .Cin(x), + .S(y), + .Cout(z)); + + initial begin + v = 0; + w = 0; + x = 0; + #5 + v = 0; + w = 1; + x = 0; + #5 + v = 0; + w = 0; + x = 1; + #5 + v = 1; + w = 1; + x = 0; + #5 + v = 1; + w = 1; + x = 1; + #5 + $finish; + + end +endmodule module add_9bit( input wire [8:0] A, @@ -132,43 +135,42 @@ module add_9bit( endmodule //testbench -//module add9bit_tb(); -//reg [8:0] a; -//reg [8:0] b; -//reg cin; -//wire [8:0] s; -//wire cout; +module add9bit_tb(); + reg [8:0] a,b; + reg cin; + wire [8:0] s; + wire cout; -//add_9bit add0( -// .A(a), -// .B(b), -// .Cin(cin), -// .Sum(s), -// .Cout(cout)); + add_9bit tb0( + .A(a), + .B(b), + .Cin(cin), + .Sum(s), + .Cout(cout)); -// initial begin -// a = 9'b000000000; -// b = 9'b000000000; -// cin = 0; -// #5 -// a = 9'b000000001; -// b = 9'b000000000; -// cin = 0; -// #5 -// a = 9'b000000000; -// b = 9'b000000001; -// cin = 1; -// #5 -// a = 9'b000000001; -// b = 9'b000000001; -// cin = 0; -// #5 -// a = 9'b000001000; -// b = 9'b000000001; -// cin = 1; -// end -//endmodule + initial begin + a = 9'b000000000; + b = 9'b000000000; + cin = 0; + #5 + a = 9'b000000001; + b = 9'b000000000; + cin = 0; + #5 + a = 9'b000000000; + b = 9'b000000001; + cin = 1; + #5 + a = 9'b000000001; + b = 9'b000000001; + cin = 0; + #5 + a = 9'b000001000; + b = 9'b000000001; + cin = 1; + end +endmodule module and_1bit( input wire A, @@ -180,32 +182,32 @@ module and_1bit( endmodule //testbench -//module and1bit_tb(); -//reg a; -//reg b; -//wire c; +module and1bit_tb(); + reg a,b; + wire c; -//and_1bit and0( -//.A(a), -//.B(b), -//.C(c)); + and_1bit and0( + .A(a), + .B(b), + .C(c)); -// initial begin -// a = 0; -// b = 0; -// #5 -// a = 0; -// b = 1; -// #5 -// a = 1; -// b = 0; -// #5 -// a = 1; -// b = 1; -// #5 $finish; + initial begin + a = 0; + b = 0; + #5 + a = 0; + b = 1; + #5 + a = 1; + b = 0; + #5 + a = 1; + b = 1; + #5 + $finish; -// end -//endmodule + end +endmodule module and_9bit( input wire [8:0] A, @@ -260,38 +262,84 @@ module and_9bit( endmodule //testbench -//module and9bit_tb(); -//reg [8:0] a; -//reg [8:0] b; -//wire [8:0] c; +module and9bit_tb(); + reg [8:0] a,b; + wire [8:0] c; -//and_9bit and0( -//.A(a), -//.B(b), -//.C(c)); + and_9bit and0( + .A(a), + .B(b), + .C(c)); -// initial begin -// a = 9'b000000000; -// b = 9'b000000000; -// #5 -// a = 9'b000000000; -// b = 9'b000000001; -// #5 -// a = 9'b000000001; -// b = 9'b000000000; -// #5 -// a = 9'b000000001; -// b = 9'b000000001; -// #5 -// a = 9'b000100001; -// b = 9'b000000001; -// #5 -// a = 9'b000100001; -// b = 9'b000100001; -// #5 $finish; + initial begin + a = 9'b000000000; + b = 9'b000000000; + #5 + a = 9'b000000000; + b = 9'b000000001; + #5 + a = 9'b000000001; + b = 9'b000000000; + #5 + a = 9'b000000001; + b = 9'b000000001; + #5 + a = 9'b000100001; + b = 9'b000000001; + #5 + a = 9'b000100001; + b = 9'b000100001; + #5 + $finish; -// end -//endmodule + end +endmodule + +module decoder ( + input wire en, + input wire [1:0] index, + output reg [3:0] regOut); + + always @(en, index)begin + if(en == 1)begin + case(index) + 2'b00: regOut <= 4'b0001; + 2'b01: regOut <= 4'b0010; + 2'b10: regOut <= 4'b0100; + 2'b11: regOut <= 4'b1000; + default: regOut <= 4'bxxxx; + endcase + end + end +endmodule + +//testbench +module decoder_tb(); + reg enable; + reg [1:0] indexIn; + wire [3:0] regOut; + + decoder dec0( + .en(enable), + .index(indexIn), + .regOut(regOut)); + + initial begin + enable = 0; + indexIn = 2'b00; + #5 + enable = 1; + #5 + indexIn = 2'b01; + #5 + indexIn = 2'b10; + #5 + indexIn = 2'b11; + #5 + $finish; + + end +endmodule module gen_clock(); reg clk; @@ -303,15 +351,10 @@ module gen_clock(); end endmodule -// testbench -//module gen_clock_tb(); - -//reg clk; -// gen - -module mux_2_1(input wire switch, - input wire [8:0] A,B, - output reg [8:0] out); +module mux_2_1( + input wire switch, + input wire [8:0] A,B, + output reg [8:0] out); always @(A,B,switch) begin case (switch) @@ -320,50 +363,49 @@ module mux_2_1(input wire switch, default : out = 9'bxxxxxxxxx; endcase end - endmodule //testbench -//module mux_2_1_tb(); -//reg s; -//reg [8:0] a; -//reg [8:0] b; -//wire [8:0] c; +module mux_2_1_tb(); + reg s; + reg [8:0] a,b; + wire [8:0] c; -//mux_2_1 mux0( -//.switch(s), -//.A(a), -//.B(b), -//.out(c)); + mux_2_1 tb0( + .switch(s), + .A(a), + .B(b), + .out(c)); -// initial begin -// s = 0; -// a = 9'b000000101; -// b = 9'b000000000; -// #5 -// s = 1; -// a = 9'b000000001; -// b = 9'b000100001; -// #5 -// s = 0; -// a = 9'b000000000; -// b = 9'b000000001; -// #5 -// s = 1; -// a = 9'b000000001; -// b = 9'b000000001; -// #5 -// s = 0; -// a = 9'b000010001; -// b = 9'b000000001; -// #5 -// s = 1; -// a = 9'b000010001; -// b = 9'b000010111; -// #5 $finish; + initial begin + s = 0; + a = 9'b000000101; + b = 9'b000000000; + #5 + s = 1; + a = 9'b000000001; + b = 9'b000100001; + #5 + s = 0; + a = 9'b000000000; + b = 9'b000000001; + #5 + s = 1; + a = 9'b000000001; + b = 9'b000000001; + #5 + s = 0; + a = 9'b000010001; + b = 9'b000000001; + #5 + s = 1; + a = 9'b000010001; + b = 9'b000010111; + #5 + $finish; -// end -//endmodule + end +endmodule module mux_4_1(input wire [1:0] switch, input wire [8:0] A,B,C,D, @@ -382,50 +424,48 @@ module mux_4_1(input wire [1:0] switch, endmodule //testbench -//module mux_4_1_tb(); -//reg [1:0] s; -//reg [8:0] a; -//reg [8:0] b; -//reg [8:0] c; -//reg [8:0] d; -//wire [8:0] e; +module mux_4_1_tb(); + reg [1:0] s; + reg [8:0] a,b,c,d; + wire [8:0] e; -//mux_4_1 mux1( -//.switch(s), -//.A(a), -//.B(b), -//.C(c), -//.D(d), -//.out(e)); + mux_4_1 tb0( + .switch(s), + .A(a), + .B(b), + .C(c), + .D(d), + .out(e)); -// initial begin -// s = 2'b00; -// a = 9'b000000101; -// b = 9'b000111100; -// c = 9'b001001001; -// d = 9'b100000000; -// #5 -// s = 2'b01; -// a = 9'b000000101; -// b = 9'b000111100; -// c = 9'b001001001; -// d = 9'b100000000; -// #5 -// s = 2'b10; -// a = 9'b000000101; -// b = 9'b000111100; -// c = 9'b001001001; -// d = 9'b100000000; -// #5 -// s = 2'b11; -// a = 9'b000000101; -// b = 9'b000111100; -// c = 9'b001001001; -// d = 9'b100000000; -// #5 $finish; + initial begin + s = 2'b00; + a = 9'b000000101; + b = 9'b000111100; + c = 9'b001001001; + d = 9'b100000000; + #5 + s = 2'b01; + a = 9'b000000101; + b = 9'b000111100; + c = 9'b001001001; + d = 9'b100000000; + #5 + s = 2'b10; + a = 9'b000000101; + b = 9'b000111100; + c = 9'b001001001; + d = 9'b100000000; + #5 + s = 2'b11; + a = 9'b000000101; + b = 9'b000111100; + c = 9'b001001001; + d = 9'b100000000; + #5 + $finish; -// end -//endmodule + end +endmodule module mux_8_1( input wire [2:0] switch, @@ -445,91 +485,55 @@ module mux_8_1( default : out = 9'bxxxxxxxxx; endcase end - endmodule //testbench -//module mux_8_1_tb(); -//reg [2:0] s; -//reg [8:0] a; -//reg [8:0] b; -//reg [8:0] c; -//reg [8:0] d; -//reg [8:0] e; -//reg [8:0] f; -//reg [8:0] g; -//reg [8:0] h; -//wire [8:0] out; +module mux_8_1_tb(); + reg [2:0] s; + reg [8:0] a,b,c,d,e,f,g,h; + wire [8:0] out; -//mux_8_1 mux1( -//.switch(s), -//.A(a), -//.B(b), -//.C(c), -//.D(d), -//.E(e), -//.F(f), -//.G(g), -//.H(h), -//.out(out)); + mux_8_1 tb0( + .switch(s), + .A(a), + .B(b), + .C(c), + .D(d), + .E(e), + .F(f), + .G(g), + .H(h), + .out(out)); -// initial begin -// s = 3'b000; -// a = 9'b000000101; -// b = 9'b000111100; -// c = 9'b001001001; -// d = 9'b100110000; -// e = 9'b010000101; -// f = 9'b010111100; -// g = 9'b011001001; -// h = 9'b111000000; -// #5 -// s = 3'b001; -// #5 -// s = 3'b010; -// #5 -// s = 3'b011; -// #5 -// s = 3'b100; -// #5 -// s = 3'b101; -// #5 -// s = 3'b110; -// #5 -// s = 3'b111; -// #5 $finish; + initial begin + s = 3'b000; + a = 9'b000000101; + b = 9'b000111100; + c = 9'b001001001; + d = 9'b100110000; + e = 9'b010000101; + f = 9'b010111100; + g = 9'b011001001; + h = 9'b111000000; + #5 + s = 3'b001; + #5 + s = 3'b010; + #5 + s = 3'b011; + #5 + s = 3'b100; + #5 + s = 3'b101; + #5 + s = 3'b110; + #5 + s = 3'b111; + #5 + $finish; -// end -//endmodule - -//module mux_16_1( -// input wire [3:0] switch, -// input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P, -// output reg [8:0] out); - -// always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin -// case (switch) -// 4'b0000 : out = A; -// 4'b0001 : out = B; -// 4'b0010 : out = C; -// 4'b0011 : out = D; -// 4'b0100 : out = E; -// 4'b0101 : out = F; -// 4'b0110 : out = G; -// 4'b0111 : out = H; -// 4'b1000 : out = I; -// 4'b1001 : out = J; -// 4'b1010 : out = K; -// 4'b1011 : out = L; -// 4'b1100 : out = M; -// 4'b1101 : out = N; -// 4'b1110 : out = O; -// 4'b1111 : out = P; -// default : out = 9'bxxxxxxxxx; -// endcase -// end - -//endmodule + end +endmodule module nor_1bit( input wire A, @@ -542,32 +546,33 @@ module nor_1bit( endmodule //testbench -//module nor_1bit_tb(); -//reg a; -//reg b; -//wire c; +module nor_1bit_tb(); + reg a; + reg b; + wire c; -//nor_1bit nor0( -//.A(a), -//.B(b), -//.C(c)); + nor_1bit nor0( + .A(a), + .B(b), + .C(c)); -// initial begin -// a = 0; -// b = 0; -// #5 -// a = 0; -// b = 1; -// #5 -// a = 1; -// b = 0; -// #5 -// a = 1; -// b = 1; -// #5 $finish; + initial begin + a = 0; + b = 0; + #5 + a = 0; + b = 1; + #5 + a = 1; + b = 0; + #5 + a = 1; + b = 1; + #5 + $finish; -// end -//endmodule + end +endmodule module nor_9bit( input wire [8:0] A, @@ -622,38 +627,39 @@ module nor_9bit( endmodule //testbench -//module nor_9bit_tb(); -//reg [8:0] a; -//reg [8:0] b; -//wire [8:0] c; +module nor_9bit_tb(); + reg [8:0] a; + reg [8:0] b; + wire [8:0] c; -//nor_9bit nor0( -//.A(a), -//.B(b), -//.C(c)); + nor_9bit nor0( + .A(a), + .B(b), + .C(c)); -// initial begin -// a = 9'b000000000; -// b = 9'b000000000; -// #5 -// a = 9'b000000000; -// b = 9'b000000001; -// #5 -// a = 9'b000000001; -// b = 9'b000000000; -// #5 -// a = 9'b000000001; -// b = 9'b000000001; -// #5 -// a = 9'b000100001; -// b = 9'b000000001; -// #5 -// a = 9'b000100001; -// b = 9'b000100001; -// #5 $finish; + initial begin + a = 9'b000000000; + b = 9'b000000000; + #5 + a = 9'b000000000; + b = 9'b000000001; + #5 + a = 9'b000000001; + b = 9'b000000000; + #5 + a = 9'b000000001; + b = 9'b000000001; + #5 + a = 9'b000100001; + b = 9'b000000001; + #5 + a = 9'b000100001; + b = 9'b000100001; + #5 + $finish; -// end -//endmodule + end +endmodule module not_1bit( @@ -665,22 +671,23 @@ module not_1bit( endmodule //testbench -//module not_1bit_tb(); -//reg a; -//wire b; +module not_1bit_tb(); + reg a; + wire b; -//not_1bit not0( -//.A(a), -//.B(b)); - -// initial begin -// a = 0; -// #5 -// a = 1; -// #5 $finish; + not_1bit not0( + .A(a), + .B(b)); + + initial begin + a = 0; + #5 + a = 1; + #5 + $finish; -// end -//endmodule + end +endmodule module not_9bit( input wire [8:0] A, @@ -725,33 +732,33 @@ module not_9bit( endmodule //testbench -//module not_9bit_tb(); -//reg [8:0] a; -//wire [8:0] b; +module not_9bit_tb(); + reg [8:0] a; + wire [8:0] b; -// not_9bit not0( -// .A(a), -// .B(b)); + not_9bit not0( + .A(a), + .B(b)); -// initial begin -// a = 9'b000000000; -// #5 -// a = 9'b000000001; -// #5 -// a = 9'b000111000; -// #5 -// a = 9'b010101010; -// #5 -// a = 9'b101010101; -// #5 -// a = 9'b111111111; -// #5 -// a = 9'b100000001; -// #5 $finish; + initial begin + a = 9'b000000000; + #5 + a = 9'b000000001; + #5 + a = 9'b000111000; + #5 + a = 9'b010101010; + #5 + a = 9'b101010101; + #5 + a = 9'b111111111; + #5 + a = 9'b100000001; + #5 + $finish; -// end - -//endmodule + end +endmodule module or_1bit( input wire A, @@ -763,33 +770,33 @@ module or_1bit( endmodule //testbench -//module or_1bit_tb(); -//reg a; -//reg b; -//wire c; +module or_1bit_tb(); + reg a; + reg b; + wire c; -// or_1bit or0( -// .A(a), -// .B(b), -// .C(c)); + or_1bit or0( + .A(a), + .B(b), + .C(c)); -// initial begin -// a = 0; -// b = 0; -// #5 -// a = 0; -// b = 1; -// #5 -// a = 1; -// b = 0; -// #5 -// a = 1; -// b = 1; -// #5 $finish; + initial begin + a = 0; + b = 0; + #5 + a = 0; + b = 1; + #5 + a = 1; + b = 0; + #5 + a = 1; + b = 1; + #5 + $finish; -// end - -//endmodule + end +endmodule module or_9bit( input wire [8:0] A, @@ -844,124 +851,124 @@ module or_9bit( endmodule //testbench -//module or_9bit_tb(); -//reg [8:0] a; -//reg [8:0] b; -//wire [8:0] c; +module or_9bit_tb(); + reg [8:0] a; + reg [8:0] b; + wire [8:0] c; -// or_9bit tb0( -// .A(a), -// .B(b), -// .C(c)); + or_9bit tb0( + .A(a), + .B(b), + .C(c)); -// initial begin -// a = 9'b000000000; -// b = 9'b000000000; -// #5 -// a = 9'b111111111; -// b = 9'b111111111; -// #5 -// a = 9'b111111111; -// b = 9'b000000000; -// #5 -// a = 9'b000000000; -// b = 9'b111111111; -// #5 -// a = 9'b000000000; -// b = 9'b111111111; -// #5 -// a = 9'b010101010; -// b = 9'b111111111; -// #5 -// a = 9'b010101010; -// b = 9'b101010101; -// #5 -// a = 9'b000011111; -// b = 9'b111111111; -// #5 -// a = 9'b000000000; -// b = 9'b000010000; -// #5 $finish; + initial begin + a = 9'b000000000; + b = 9'b000000000; + #5 + a = 9'b111111111; + b = 9'b111111111; + #5 + a = 9'b111111111; + b = 9'b000000000; + #5 + a = 9'b000000000; + b = 9'b111111111; + #5 + a = 9'b000000000; + b = 9'b111111111; + #5 + a = 9'b010101010; + b = 9'b111111111; + #5 + a = 9'b010101010; + b = 9'b101010101; + #5 + a = 9'b000011111; + b = 9'b111111111; + #5 + a = 9'b000000000; + b = 9'b000010000; + #5 + $finish; -// end + end +endmodule -//endmodule - -module register(input wire clk, reset, - input wire [1:0] En, - input wire [8:0] Din, - output reg [8:0] Dout); +module register( + input wire clk, reset, + input wire En, + input wire [8:0] Din, + output reg [8:0] Dout); always @(posedge clk) begin if (reset == 1'b1) begin Dout = 9'b000000000; end - else if (En == 2'b00) begin + else if (En == 1'b0) begin Dout = Din; end else begin Dout = Dout; end end - endmodule //testbench -//module register_tb(); -//reg clk,reset; -//reg [1:0] En; -//reg [8:0] Din; -//wire [8:0] Dout; +module register_tb(); + reg clk,reset; + reg [1:0] En; + reg [8:0] Din; + wire [8:0] Dout; -// register tb0( -// .clk(clk), -// .reset(reset), -// .En(En), -// .Din(Din), -// .Dout(Dout)); + register tb0( + .clk(clk), + .reset(reset), + .En(En), + .Din(Din), + .Dout(Dout)); -// initial begin -// clk = 0; -// reset = 0; -// En = 2'b00; -// Din = 9'b000000000; -// #5 -// clk = 1; -// #5 -// clk = 0; -// reset = 0; -// En = 2'b00; -// Din = 9'b010101010; -// #5 -// clk = 1; -// #5 -// clk = 0; -// reset = 1; -// En = 2'b00; -// Din = 9'b010101010; -// #5 -// clk = 1; -// #5 -// clk = 0; -// reset = 0; -// En = 2'b01; -// Din = 9'b101010101; -// #5 -// clk = 1; -// #5 -// clk = 0; -// reset = 0; -// En = 2'b00; -// Din = 9'b000011111; -// #5 -// clk = 1; -// #5 -// clk = 0; -// #5 $finish; + initial begin + clk = 0; + reset = 0; + En = 2'b00; + Din = 9'b000000000; + #5 + clk = 1; + #5 + clk = 0; + reset = 0; + En = 2'b00; + Din = 9'b010101010; + #5 + clk = 1; + #5 + clk = 0; + reset = 1; + En = 2'b00; + Din = 9'b010101010; + #5 + clk = 1; + #5 + clk = 0; + reset = 0; + En = 2'b01; + Din = 9'b101010101; + #5 + clk = 1; + #5 + clk = 0; + reset = 0; + En = 2'b00; + Din = 9'b000011111; + #5 + clk = 1; + #5 + clk = 0; + #5 + $finish; -// end - -//endmodule + end +endmodule module shift_logical_left( input wire [8:0] A, @@ -972,33 +979,33 @@ module shift_logical_left( endmodule //testbench -//module shift_logical_left_tb(); -//reg [8:0] a; -//wire [8:0] b; +module shift_logical_left_tb(); + reg [8:0] a; + wire [8:0] b; -// shift_logical_left tb0( -// .A(a), -// .B(b)); + shift_logical_left tb0( + .A(a), + .B(b)); -// initial begin -// a = 9'b000000000; -// #5 -// a = 9'b000000001; -// #5 -// a = 9'b000111000; -// #5 -// a = 9'b010101010; -// #5 -// a = 9'b101010101; -// #5 -// a = 9'b111111111; -// #5 -// a = 9'b100000001; -// #5 $finish; + initial begin + a = 9'b000000000; + #5 + a = 9'b000000001; + #5 + a = 9'b000111000; + #5 + a = 9'b010101010; + #5 + a = 9'b101010101; + #5 + a = 9'b111111111; + #5 + a = 9'b100000001; + #5 + $finish; -// end - -//endmodule + end +endmodule module shift_logical_right( input wire [8:0] A, @@ -1009,33 +1016,33 @@ module shift_logical_right( endmodule //testbench -//module shift_logical_right_tb(); -//reg [8:0] a; -//wire [8:0] b; +module shift_logical_right_tb(); + reg [8:0] a; + wire [8:0] b; -// shift_logical_right tb0( -// .A(a), -// .B(b)); - -// initial begin -// a = 9'b000000000; -// #5 -// a = 9'b000000001; -// #5 -// a = 9'b000111000; -// #5 -// a = 9'b010101010; -// #5 -// a = 9'b101010101; -// #5 -// a = 9'b111111111; -// #5 -// a = 9'b100000001; -// #5 $finish; + shift_logical_right tb0( + .A(a), + .B(b)); -// end + initial begin + a = 9'b000000000; + #5 + a = 9'b000000001; + #5 + a = 9'b000111000; + #5 + a = 9'b010101010; + #5 + a = 9'b101010101; + #5 + a = 9'b111111111; + #5 + a = 9'b100000001; + #5 + $finish; -//endmodule + end +endmodule module sub_9bit( input wire [8:0] A, @@ -1057,48 +1064,48 @@ module sub_9bit( endmodule //testbench -//module sub_9bit_tb(); -//reg [8:0] a; -//reg [8:0] b; -//wire [8:0] c; +module sub_9bit_tb(); + reg [8:0] a; + reg [8:0] b; + wire [8:0] c; -// sub_9bit tb0( -// .A(a), -// .B(b), -// .C(c)); + sub_9bit tb0( + .A(a), + .B(b), + .C(c)); -// initial begin -// a = 9'b000000000; -// b = 9'b000000000; -// #5 -// a = 9'b111111111; -// b = 9'b111111111; -// #5 -// a = 9'b111111111; -// b = 9'b000000000; -// #5 -// a = 9'b000000000; -// b = 9'b111111111; -// #5 -// a = 9'b000000000; -// b = 9'b111111111; -// #5 -// a = 9'b010101010; -// b = 9'b111111111; -// #5 -// a = 9'b010101010; -// b = 9'b101010101; -// #5 -// a = 9'b000011111; -// b = 9'b111111111; -// #5 -// a = 9'b000000000; -// b = 9'b000010000; -// #5 $finish; + initial begin + a = 9'b000000000; + b = 9'b000000000; + #5 + a = 9'b111111111; + b = 9'b111111111; + #5 + a = 9'b111111111; + b = 9'b000000000; + #5 + a = 9'b000000000; + b = 9'b111111111; + #5 + a = 9'b000000000; + b = 9'b111111111; + #5 + a = 9'b010101010; + b = 9'b111111111; + #5 + a = 9'b010101010; + b = 9'b101010101; + #5 + a = 9'b000011111; + b = 9'b111111111; + #5 + a = 9'b000000000; + b = 9'b000010000; + #5 + $finish; -// end - -//endmodule + end +endmodule module twos_compliment_9bit( input wire [8:0] A, @@ -1119,30 +1126,30 @@ module twos_compliment_9bit( endmodule //testbench -//module twos_compliment_tb(); -//reg [8:0] a; -//wire [8:0] b; +module twos_compliment_tb(); + reg [8:0] a; + wire [8:0] b; -// twos_compliment_9bit tb0( -// .A(a), -// .B(b)); + twos_compliment_9bit tb0( + .A(a), + .B(b)); -// initial begin -// a = 9'b000000000; -// #5 -// a = 9'b000000001; -// #5 -// a = 9'b000111000; -// #5 -// a = 9'b010101010; -// #5 -// a = 9'b101010101; -// #5 -// a = 9'b111111111; -// #5 -// a = 9'b100000001; -// #5 $finish; + initial begin + a = 9'b000000000; + #5 + a = 9'b000000001; + #5 + a = 9'b000111000; + #5 + a = 9'b010101010; + #5 + a = 9'b101010101; + #5 + a = 9'b111111111; + #5 + a = 9'b100000001; + #5 + $finish; -// end - -//endmodule \ No newline at end of file + end +endmodule \ No newline at end of file diff --git a/lab2CA.srcs/sources_1/new/FetchUnit.v b/lab2CA.srcs/sources_1/new/FetchUnit.v index a344dee..5647473 100644 --- a/lab2CA.srcs/sources_1/new/FetchUnit.v +++ b/lab2CA.srcs/sources_1/new/FetchUnit.v @@ -11,7 +11,7 @@ module FetchUnit(input wire clk, reset, register PC( .clk(clk), .reset(reset), - .En(2'b00), + .En(1'b0), .Din(result_m), .Dout(progC_out)); //Adds 1 to the program counter @@ -31,61 +31,60 @@ module FetchUnit(input wire clk, reset, endmodule //testbench -//module fetchUnit_tb(); -//reg [8:0] addr_in; -//reg opidx; -//reg reset; -//wire [8:0] addr_out; +module fetchUnit_tb(); + reg [8:0] addr_in; + reg opidx,reset,clk; + wire [8:0] addr_out; -// reg clk; -// initial begin -// clk = 1'b0; -// end -// always begin -// #5 clk = ~clk; // Period to be determined -// end + initial begin + clk = 1'b0; + end + always begin + #5 clk = ~clk; // Period to be determined + end -//FetchUnit fetchUnit0( -//.clk(clk), -//.reset(reset), -//.op_idx(opidx), -//.AddrIn(addr_in), -//.AddrOut(addr_out)); + FetchUnit tb0( + .clk(clk), + .reset(reset), + .op_idx(opidx), + .AddrIn(addr_in), + .AddrOut(addr_out)); -// initial begin -// reset = 0; -// opidx = 1'b1; -// addr_in = 0'b000000000; -// #5 -// reset = 1; -// #5 -// reset = 0; -// opidx = 1'b0; -// addr_in = 9'b000001111; -// #5 -// #5 -// addr_in = 9'b011000011; -// #5 -// #5 -// opidx = 1'b1; -// #5 -// #5 -// #5 -// #5 -// opidx = 1'b0; -// addr_in = 9'b000001111; -// #5 -// #5 -// addr_in = 9'b010010011; -// #5 -// opidx = 1'b1; -// #5 -// #5 -// #5 -// #5 -// #5 $finish; + initial begin + reset = 0; + opidx = 1'b1; + addr_in = 9'b000000000; + #5 + reset = 1; + #5 + reset = 0; + opidx = 1'b0; + addr_in = 9'b000001111; + #5 + #5 + addr_in = 9'b011000011; + #5 + #5 + opidx = 1'b1; + #5 + #5 + #5 + #5 + opidx = 1'b0; + addr_in = 9'b000001111; + #5 + #5 + addr_in = 9'b010010011; + #5 + opidx = 1'b1; + #5 + #5 + #5 + #5 + #5 + $finish; -// end -//endmodule \ No newline at end of file + end +endmodule \ No newline at end of file diff --git a/lab2CA.srcs/sources_1/new/RegFile.v b/lab2CA.srcs/sources_1/new/RegFile.v index c61c879..fd51315 100644 --- a/lab2CA.srcs/sources_1/new/RegFile.v +++ b/lab2CA.srcs/sources_1/new/RegFile.v @@ -1,39 +1,46 @@ `timescale 1ns / 1ps -module RegFile(input wire clk, reset, +module RegFile(input wire clk, reset, enable, input wire [1:0] write_index, op0_idx, op1_idx, input wire [8:0] write_data, output wire [8:0] op0, op1); + wire [3:0] decOut; wire [8:0] r0_out, r1_out, r2_out, r3_out; // To select a register En input must be 2'b00 + decoder d0( + .en(enable), + .index(write_index), + .regOut(decOut) + ); + register r0( .clk(clk), .reset(reset), - .En({write_index[0], write_index[1]}), + .En(decOut[0]), .Din(write_data), .Dout(r0_out)); register r1( .clk(clk), .reset(reset), - .En({write_index[0], ~write_index[1]}), + .En(decOut[1]), .Din(write_data), .Dout(r1_out)); register r2( .clk(clk), .reset(reset), - .En({~write_index[0], write_index[1]}), + .En(decOut[2]), .Din(write_data), .Dout(r2_out)); register r3( .clk(clk), .reset(reset), - .En({~write_index[0], ~write_index[1]}), + .En(decOut[4]), .Din(write_data), .Dout(r3_out)); @@ -57,12 +64,11 @@ endmodule //testbench module regFile_tb(); -reg [8:0] write_d; -reg [1:0] w_idx, op0_idx, op1_idx; -reg reset; -wire [8:0] op0,op1; + reg [8:0] write_d; + reg [1:0] w_idx, op0_idx, op1_idx; + reg reset,clk, enable; + wire [8:0] op0,op1; - reg clk; initial begin clk = 1'b0; end @@ -70,66 +76,69 @@ wire [8:0] op0,op1; #5 clk = ~clk; // Period to be determined end -RegFile regFile0( -.clk(clk), -.reset(reset), -.write_index(w_idx), -.op0_idx(op0_idx), -.op1_idx(op1_idx), -.write_data(write_d), -.op0(op0), -.op1(op1)); + RegFile regFile0( + .clk(clk), + .enable(enable), + .reset(reset), + .write_index(w_idx), + .op0_idx(op0_idx), + .op1_idx(op1_idx), + .write_data(write_d), + .op0(op0), + .op1(op1)); initial begin - reset = 0; - #5 - reset = 1; - #5 - reset = 0; - w_idx = 2'b00; - op0_idx = 2'b00; - op1_idx = 2'b00; - write_d = 9'b000000011; - #5 - w_idx = 2'b01; - #5 - w_idx = 2'b10; - #5 - w_idx = 2'b11; - #5 - reset = 0; - w_idx = 2'b00; - op0_idx = 2'b10; - op1_idx = 2'b11; - write_d = 9'b001111000; - #5 - reset = 0; - w_idx = 2'b01; - op0_idx = 2'b00; - op1_idx = 2'b01; - write_d = 9'b000001111; - #5 - reset = 0; - w_idx = 2'b10; - op0_idx = 2'b00; - op1_idx = 2'b10; - write_d = 9'b111000001; - #5 - reset = 0; - w_idx = 2'b11; - op0_idx = 2'b11; - op1_idx = 2'b10; - write_d = 9'b100110001; - #5 - reset = 1; - w_idx = 2'b00; - #5 - w_idx = 2'b10; - #5 - w_idx = 2'b01; - #5 - w_idx = 2'b11; - #5 $finish; + reset = 0; + #5 + reset = 1; + #5 + reset = 0; + enable = 1; + w_idx = 2'b00; + op0_idx = 2'b00; + op1_idx = 2'b00; + write_d = 9'b000000011; + #5 + w_idx = 2'b01; + #5 + w_idx = 2'b10; + #5 + w_idx = 2'b11; + #5 + reset = 0; + w_idx = 2'b00; + op0_idx = 2'b10; + op1_idx = 2'b11; + write_d = 9'b001111000; + #5 + reset = 0; + w_idx = 2'b01; + op0_idx = 2'b00; + op1_idx = 2'b01; + write_d = 9'b000001111; + #5 + reset = 0; + w_idx = 2'b10; + op0_idx = 2'b00; + op1_idx = 2'b10; + write_d = 9'b111000001; + #5 + reset = 0; + w_idx = 2'b11; + op0_idx = 2'b11; + op1_idx = 2'b10; + write_d = 9'b100110001; + #5 + reset = 1; + w_idx = 2'b00; + #5 + w_idx = 2'b10; + #5 + w_idx = 2'b01; + #5 + w_idx = 2'b11; + #5 + $finish; end endmodule \ No newline at end of file diff --git a/lab2CA.xpr b/lab2CA.xpr index 764c63b..ab16619 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -31,7 +31,7 @@