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Changed datamemory

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This commit is contained in:
Johannes
2019-03-24 12:47:18 -04:00
parent c85ad153dc
commit 90d9d69885
14 changed files with 121 additions and 144 deletions
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2
lab2CA.srcs/sources_1/new/ControlUnit.v
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@@ -124,7 +124,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b1;
end
4'b1010: begin
4'b1100: begin
aluOut <= 4'b0000;
FU <= 3'b110; // branch
RegEn <= 1'b1;

9
lab2CA.srcs/sources_1/new/instructionMemory.v
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@@ -26,14 +26,15 @@ module instructionMemory(
memory[11] <= 9'b111011001; //and
memory[12] <= 9'b111111000; //sll
memory[13] <= 9'b111111001; //srl
// memory[14] <= 9'b100101100; //j
memory[14] <= 9'b110001001; //beq
memory[15] <= 9'b100001000; //jr
// memory[14] <= 9'b100100010; //j
memory[14] <= 9'b010001000; //zero
memory[15] <= 9'b110001101; //beq
memory[16] <= 9'b100001000; //jr
memory[16] <= 9'b000000000;
memory[17] <= 9'b100111100; //j
end