diff --git a/README.md b/README.md index d4c4a24..9bb1414 100644 --- a/README.md +++ b/README.md @@ -1,17 +1,5 @@ # ECE 3570 Lab -## Fixes To Be Implemented +## Unknown Status of Fixes -* Get rid of the double zero for the enable on the registers - * Make decoder for it -* Redo simulations with other registers using internal signals -* Fix simulation waveforms for Registers, as we are currently changing inputs too quickly (multiple times within a clock cycle) -* Only two registers are being written to, first two within simulation is not being written to -* Need to allow for signed numbers -* Remove subtraction from ALU -* Have arithmetic shift left and right -* Uncomment all testbenches (We can have multiple testbenches active at once) -* Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only -* Comparator needed -* Make subtraction more efficient -* Need to verify that FetchUnit is working properly as Martin had some concerns that it probably wasn't functioning properly \ No newline at end of file +* Only two registers are being written to, first two within simulation is not being written to \ No newline at end of file diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index c4ce280..1719a79 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,17 +17,18 @@ This means code written to parse this file will need to be revisited each subseq + - + - + - - + + @@ -36,67 +37,76 @@ This means code written to parse this file will need to be revisited each subseq + - - - + + + - + - - + + - + - + + + + + + - + - + + + - - + + - - + + - - + + - - + + + - + - + - + - + - +
diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml index faca896..1d5061e 100644 --- a/lab2CA.runs/impl_1/gen_run.xml +++ b/lab2CA.runs/impl_1/gen_run.xml @@ -1,10 +1,8 @@ - - @@ -18,11 +16,8 @@ - - - @@ -31,25 +26,8 @@ - - - - - - - - - - - - - - - - - diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml index 60496de..afce82b 100644 --- a/lab2CA.runs/synth_1/gen_run.xml +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -4,8 +4,6 @@ - - diff --git a/lab2CA.sim/sim_1/behav/xsim/comparator_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/comparator_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/comparator_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/comparator_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/comparator_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/comparator_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/slt_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/slt_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/slt_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/slt_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/slt_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/slt_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou index dcabd11..bd2c0bb 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 27 11:47:34 2019 -# Process ID: 6784 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +# Start of session at: Tue Mar 12 20:38:16 2019 +# Process ID: 15148 +# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_10344.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_10344.backup.jou deleted file mode 100644 index d926d13..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_10344.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 20 11:30:13 2019 -# Process ID: 10344 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_1408.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_1408.backup.jou deleted file mode 100644 index 29a40e1..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_1408.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 27 11:43:09 2019 -# Process ID: 1408 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_14864.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_14864.backup.jou deleted file mode 100644 index 6e967bd..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_14864.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 27 11:39:16 2019 -# Process ID: 14864 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_16620.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_16620.backup.jou deleted file mode 100644 index 11d2a60..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_16620.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Thu Feb 21 14:46:02 2019 -# Process ID: 16620 -# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/REPOSITORIES/Educational/Western -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_18368.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_18368.backup.jou new file mode 100644 index 0000000..3562bda --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_18368.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Tue Mar 12 19:51:55 2019 +# Process ID: 18368 +# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_4236.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_4236.backup.jou new file mode 100644 index 0000000..d7df5f9 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_4236.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Tue Mar 12 19:44:30 2019 +# Process ID: 4236 +# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_5116.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_5116.backup.jou new file mode 100644 index 0000000..22cdfd2 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_5116.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Tue Mar 12 19:52:36 2019 +# Process ID: 5116 +# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_6512.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_6512.backup.jou new file mode 100644 index 0000000..22bd10f --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_6512.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Tue Mar 12 19:46:24 2019 +# Process ID: 6512 +# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_6516.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_6516.backup.jou deleted file mode 100644 index 4eb8fc3..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_6516.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Thu Feb 21 14:24:16 2019 -# Process ID: 6516 -# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/JoseIgnacio/CA -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou deleted file mode 100644 index bbb2a8d..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 27 11:36:59 2019 -# Process ID: 7276 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_7548.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_7548.backup.jou new file mode 100644 index 0000000..c21a117 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_7548.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Tue Mar 12 20:36:54 2019 +# Process ID: 7548 +# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index 5862552..1355cf6 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xelab.pb and b/lab2CA.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/Compile_Options.txt index 17cfe5c..23a3e38 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/Compile_Options.txt +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/Compile_Options.txt @@ -1 +1 @@ --wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "add9bit_tb_behav" "xil_defaultlib.add9bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "add9bit_tb_behav" "xil_defaultlib.add9bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml index 18d283b..08ecd8b 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -1,16 +1,16 @@ - +
- + - - + + @@ -19,11 +19,11 @@
- + - +
@@ -35,9 +35,8 @@
- - - + +
diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..587f4a9 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,31 @@ +webtalk_init -webtalk_dir C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Tue Mar 12 19:53:25 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "fe5d421c9f2b5ebc958da28a6d468b09" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.09_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "5696_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3522894383 -regid "" -xml C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/xsim.mem index 5434136..65490dd 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/xsim.mem and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..d1d11d7 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "comparator_tb_behav" "xil_defaultlib.comparator_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..33373a1 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/obj/xsim_1.c @@ -0,0 +1,107 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_3(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_8(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[13] = {(funcp)execute_3, (funcp)execute_9, (funcp)execute_10, (funcp)execute_8, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 13; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/comparator_tb_behav/xsim.reloc", (void **)funcTab, 13); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/comparator_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/comparator_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/comparator_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/comparator_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/comparator_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..56321de --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,43 @@ + + +
+
+ + + + + + + + + + + + + + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/xsim.mem new file mode 100644 index 0000000..2832b04 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..1e4d769 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "slt_tb_behav" "xil_defaultlib.slt_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..271491f --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/obj/xsim_1.c @@ -0,0 +1,109 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[15] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 15; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/slt_tb_behav/xsim.reloc", (void **)funcTab, 15); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/slt_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/slt_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/slt_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/slt_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/slt_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..f4f5b9a --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,43 @@ + + +
+
+ + + + + + + + + + + + + + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..37c147e --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,31 @@ +webtalk_init -webtalk_dir C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Tue Mar 12 19:52:40 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "fe5d421c9f2b5ebc958da28a6d468b09" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "8" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runtime -value "40 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.01_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "5472_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3382459669 -regid "" -xml C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/xsim.mem new file mode 100644 index 0000000..61c7e52 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb index bf58768..64a000f 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb and b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/lab2CA.srcs/sources_1/bd/design_1/design_1.bd b/lab2CA.srcs/sources_1/bd/design_1/design_1.bd new file mode 100644 index 0000000..1eeb2fe --- /dev/null +++ b/lab2CA.srcs/sources_1/bd/design_1/design_1.bd @@ -0,0 +1,11 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x0", + "name": "design_1", + "synth_flow_mode": "Hierarchical", + "tool_version": "2018.3" + }, + "design_tree": {} + } +} \ No newline at end of file diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v index 664cd6e..efd2842 100644 --- a/lab2CA.srcs/sources_1/new/ALU.v +++ b/lab2CA.srcs/sources_1/new/ALU.v @@ -1,54 +1,74 @@ `timescale 1ns / 1ps module ALU( - input wire [2:0] opcode, // NOT the same as the instruction set opcode + input wire [3:0] opcode, // NOT the same as the instruction set opcode input wire [8:0] operand0, input wire [8:0] operand1, output wire [8:0] result ); // Wires for connecting the modules to the mux - wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H; + wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P; - // A (000) - Add + // A (0000) - Add add_9bit add0( .A(operand0), .B(operand1), .Cin(1'b0), .Sum(result_A)); - // B (001) - Subtract + // B (0001) - Subtract sub_9bit sub0( .A(operand0), .B(operand1), .C(result_B)); - // C (010) - OR + // C (0010) - OR or_9bit or0( .A(operand0), .B(operand1), .C(result_C)); - // D (011) - NOR + // D (0011) - NOR nor_9bit nor0( .A(operand0), .B(operand1), .C(result_D)); - // E (100) - AND + // E (0100) - AND and_9bit and0( .A(operand0), .B(operand1), .C(result_E)); - // F (101) - Shift Logical Left - shift_logical_left sll( + // F (0101) - Shift Left + shift_left sl( .A(operand0), .B(result_F)); - // G (110) - Shift Logical Right - shift_logical_right slr( + // G (0110) - Shift Right Logical + shift_right_logical srl( .A(operand0), .B(result_G)); - // H (111) - + // H (0111) - Shift Right Arithmetic + shift_right_arithmetic sra( + .A(operand0), + .B(result_H)); + // I (1000) - NOT + not_9bit not0( + .A(operand0), + .B(result_I)); + // J (1001) - Less Than + less_than less0( + .A(operand0), + .B(operand1), + .C(result_J)); + // K (1010) - Zero + zero zero0( + .A(operand0), + .B(result_K)); + // L (1011) + // M (1100) + // N (1101) + // O (1110) + // P (1111) // MUX chooses which result to show based on the ALU's opcode - mux_8_1 mux0( + mux_16_1 mux0( .switch(opcode), .A(result_A), .B(result_B), @@ -58,6 +78,14 @@ module ALU( .F(result_F), .G(result_G), .H(result_H), + .I(result_I), + .J(result_J), + .K(result_K), + .L(result_L), + .M(result_M), + .N(result_N), + .O(result_O), + .P(result_P), .out(result)); endmodule @@ -66,7 +94,7 @@ endmodule module alu_tb(); reg [8:0] a; reg [8:0] b; - reg [2:0] c; + reg [3:0] c; wire [8:0] d; ALU alu0( @@ -78,29 +106,29 @@ module alu_tb(); initial begin a = 9'b000000111; b = 9'b000111000; - c = 3'b000; + c = 4'b0000; #5 a = 9'b000011000; b = 9'b000011000; - c = 3'b001; + c = 4'b0001; #5 a = 9'b101010100; b = 9'b010101011; - c = 3'b010; + c = 4'b0010; #5 a = 9'b101010100; b = 9'b010101000; - c = 3'b011; + c = 4'b0011; #5 a = 9'b000110000; b = 9'b000111000; - c = 3'b100; + c = 4'b0100; #5 a = 9'b01011000; - c = 3'b101; + c = 4'b0101; #5 a = 9'b00001010; - c = 3'b110; + c = 4'b0110; #5 $finish; diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index a4ea6c7..d3660e4 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -172,92 +172,12 @@ module add9bit_tb(); end endmodule -module and_1bit( - input wire A, - input wire B, - output wire C); - - assign C = A & B; - -endmodule - -//testbench -module and1bit_tb(); - reg a,b; - wire c; - - and_1bit and0( - .A(a), - .B(b), - .C(c)); - - initial begin - a = 0; - b = 0; - #5 - a = 0; - b = 1; - #5 - a = 1; - b = 0; - #5 - a = 1; - b = 1; - #5 - $finish; - - end -endmodule - module and_9bit( input wire [8:0] A, input wire [8:0] B, output wire [8:0] C); - and_1bit and0( - .A(A[0]), - .B(B[0]), - .C(C[0])); - - and_1bit and1( - .A(A[1]), - .B(B[1]), - .C(C[1])); - - and_1bit and2( - .A(A[2]), - .B(B[2]), - .C(C[2])); - - and_1bit and3( - .A(A[3]), - .B(B[3]), - .C(C[3])); - - and_1bit and4( - .A(A[4]), - .B(B[4]), - .C(C[4])); - - and_1bit and5( - .A(A[5]), - .B(B[5]), - .C(C[5])); - - and_1bit and6( - .A(A[6]), - .B(B[6]), - .C(C[6])); - - and_1bit and7( - .A(A[7]), - .B(B[7]), - .C(C[7])); - - and_1bit and8( - .A(A[8]), - .B(B[8]), - .C(C[8])); + assign C = A & B; endmodule @@ -295,6 +215,49 @@ module and9bit_tb(); end endmodule +module comparator ( + input wire [8:0] A, + input wire [8:0] B, + output wire [8:0] C); + + assign C = (~A & ~B) | (A & B); + +endmodule + +//testbench +module comparator_tb(); + reg [8:0] a,b; + wire [8:0] c; + + comparator comparator0( + .A(a), + .B(b), + .C(c)); + + initial begin + a = 9'b000000000; + b = 9'b000000000; + #5 + a = 9'b000000000; + b = 9'b000000001; + #5 + a = 9'b000000001; + b = 9'b000000000; + #5 + a = 9'b000000001; + b = 9'b000000001; + #5 + a = 9'b000100001; + b = 9'b000000001; + #5 + a = 9'b000100001; + b = 9'b000100001; + #5 + $finish; + + end +endmodule + module decoder ( input wire en, input wire [1:0] index, @@ -351,6 +314,22 @@ module gen_clock(); end endmodule +module less_than( + input wire [8:0] A,B, + output wire [8:0] C); + + wire [8:0] D; + + sub_9bit sub0( + .A(A), + .B(B), + .C(D)); + + assign C = {8'b00000000,D[8]}; + // 1 if A is less than B + // 0 if B is greater than or equal to A +endmodule + module mux_2_1( input wire switch, input wire [8:0] A,B, @@ -535,39 +514,108 @@ module mux_8_1_tb(); end endmodule -module nor_1bit( - input wire A, - input wire B, - output wire C); - - //assign C = A |~ B; - assign C = ~(A | B); - +module mux_16_1( + input wire [3:0] switch, + input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P, + output reg [8:0] out); + + always @(A,B,C,D,E,F,G,H,switch) begin + case (switch) + 4'b0000 : out = A; + 4'b0001 : out = B; + 4'b0010 : out = C; + 4'b0011 : out = D; + 4'b0100 : out = E; + 4'b0101 : out = F; + 4'b0110 : out = G; + 4'b0111 : out = H; + 4'b1000 : out = I; + 4'b1001 : out = J; + 4'b1010 : out = K; + 4'b1011 : out = L; + 4'b1100 : out = M; + 4'b1101 : out = N; + 4'b1110 : out = O; + 4'b1111 : out = P; + default : out = 9'bxxxxxxxxx; + endcase + end endmodule //testbench -module nor_1bit_tb(); - reg a; - reg b; - wire c; +module mux_16_1_tb(); + reg [2:0] switch; + reg [8:0] a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p; + wire [8:0] out; - nor_1bit nor0( + mux_16_1 tb0( + .switch(switch), .A(a), .B(b), - .C(c)); + .C(c), + .D(d), + .E(e), + .F(f), + .G(g), + .H(h), + .I(i), + .J(j), + .K(k), + .L(l), + .M(m), + .N(n), + .O(o), + .P(p), + .out(out)); initial begin - a = 0; - b = 0; + switch = 4'b0000; + a = 9'b000000101; + b = 9'b000111100; + c = 9'b001001001; + d = 9'b100110000; + e = 9'b010000101; + f = 9'b010111100; + g = 9'b011001001; + h = 9'b111000000; + i = 9'b100100101; + j = 9'b000001100; + k = 9'b001001001; + l = 9'b100110011; + m = 9'b010111101; + n = 9'b010110100; + o = 9'b100101001; + p = 9'b111001100; #5 - a = 0; - b = 1; + switch = 4'b0001; #5 - a = 1; - b = 0; + switch = 4'b0010; #5 - a = 1; - b = 1; + switch = 4'b0011; + #5 + switch = 4'b0100; + #5 + switch = 4'b0101; + #5 + switch = 4'b0110; + #5 + switch = 4'b0111; + #5 + switch = 4'b1000; + #5 + switch = 4'b1001; + #5 + switch = 4'b1010; + #5 + switch = 4'b1011; + #5 + switch = 4'b1100; + #5 + switch = 4'b1101; + #5 + switch = 4'b1110; + #5 + switch = 4'b1111; #5 $finish; @@ -579,50 +627,7 @@ module nor_9bit( input wire [8:0] B, output wire [8:0] C); - nor_1bit nor0( - .A(A[0]), - .B(B[0]), - .C(C[0])); - - nor_1bit nor1( - .A(A[1]), - .B(B[1]), - .C(C[1])); - - nor_1bit nor2( - .A(A[2]), - .B(B[2]), - .C(C[2])); - - nor_1bit nor3( - .A(A[3]), - .B(B[3]), - .C(C[3])); - - nor_1bit nor4( - .A(A[4]), - .B(B[4]), - .C(C[4])); - - nor_1bit nor5( - .A(A[5]), - .B(B[5]), - .C(C[5])); - - nor_1bit nor6( - .A(A[6]), - .B(B[6]), - .C(C[6])); - - nor_1bit nor7( - .A(A[7]), - .B(B[7]), - .C(C[7])); - - nor_1bit nor8( - .A(A[8]), - .B(B[8]), - .C(C[8])); + assign C = ~(A | B); endmodule @@ -661,73 +666,11 @@ module nor_9bit_tb(); end endmodule - -module not_1bit( - input wire A, - output wire B); - - assign B = ~A; - -endmodule - -//testbench -module not_1bit_tb(); - reg a; - wire b; - - not_1bit not0( - .A(a), - .B(b)); - - initial begin - a = 0; - #5 - a = 1; - #5 - $finish; - - end -endmodule - module not_9bit( input wire [8:0] A, output wire [8:0] B); - not_1bit not0( - .A(A[0]), - .B(B[0])); - - not_1bit not1( - .A(A[1]), - .B(B[1])); - - not_1bit not2( - .A(A[2]), - .B(B[2])); - - not_1bit not3( - .A(A[3]), - .B(B[3])); - - not_1bit not4( - .A(A[4]), - .B(B[4])); - - not_1bit not5( - .A(A[5]), - .B(B[5])); - - not_1bit not6( - .A(A[6]), - .B(B[6])); - - not_1bit not7( - .A(A[7]), - .B(B[7])); - - not_1bit not8( - .A(A[8]), - .B(B[8])); + assign B = ~A; endmodule @@ -760,93 +703,12 @@ module not_9bit_tb(); end endmodule -module or_1bit( - input wire A, - input wire B, - output wire C); - - assign C = A | B; - -endmodule - -//testbench -module or_1bit_tb(); - reg a; - reg b; - wire c; - - or_1bit or0( - .A(a), - .B(b), - .C(c)); - - initial begin - a = 0; - b = 0; - #5 - a = 0; - b = 1; - #5 - a = 1; - b = 0; - #5 - a = 1; - b = 1; - #5 - $finish; - - end -endmodule - module or_9bit( input wire [8:0] A, input wire [8:0] B, output wire [8:0] C); - or_1bit or0( - .A(A[0]), - .B(B[0]), - .C(C[0])); - - or_1bit or1( - .A(A[1]), - .B(B[1]), - .C(C[1])); - - or_1bit or2( - .A(A[2]), - .B(B[2]), - .C(C[2])); - - or_1bit or3( - .A(A[3]), - .B(B[3]), - .C(C[3])); - - or_1bit or4( - .A(A[4]), - .B(B[4]), - .C(C[4])); - - or_1bit or5( - .A(A[5]), - .B(B[5]), - .C(C[5])); - - or_1bit or6( - .A(A[6]), - .B(B[6]), - .C(C[6])); - - or_1bit or7( - .A(A[7]), - .B(B[7]), - .C(C[7])); - - or_1bit or8( - .A(A[8]), - .B(B[8]), - .C(C[8])); + assign C = A | B; endmodule @@ -970,7 +832,7 @@ module register_tb(); end endmodule -module shift_logical_left( +module shift_left( input wire [8:0] A, output wire [8:0] B); @@ -979,11 +841,11 @@ module shift_logical_left( endmodule //testbench -module shift_logical_left_tb(); +module shift_left_tb(); reg [8:0] a; wire [8:0] b; - shift_logical_left tb0( + shift_left tb0( .A(a), .B(b)); @@ -1007,7 +869,7 @@ module shift_logical_left_tb(); end endmodule -module shift_logical_right( +module shift_right_logical( input wire [8:0] A, output wire [8:0] B); @@ -1016,11 +878,48 @@ module shift_logical_right( endmodule //testbench -module shift_logical_right_tb(); +module shift_right_logical_tb(); reg [8:0] a; wire [8:0] b; - shift_logical_right tb0( + shift_right_logical tb0( + .A(a), + .B(b)); + + initial begin + a = 9'b000000000; + #5 + a = 9'b000000001; + #5 + a = 9'b000111000; + #5 + a = 9'b010101010; + #5 + a = 9'b101010101; + #5 + a = 9'b111111111; + #5 + a = 9'b100000001; + #5 + $finish; + + end +endmodule + +module shift_right_arithmetic( + input wire [8:0] A, + output wire [8:0] B); + + assign B = {A[8],A[8:1]}; + +endmodule + +//testbench +module shift_right_arithmetic_tb(); + reg [8:0] a; + wire [8:0] b; + + shift_right_arithmetic tb0( .A(a), .B(b)); @@ -1152,4 +1051,13 @@ module twos_compliment_tb(); $finish; end +endmodule + +module zero( + input wire [8:0] A, + output wire [8:0] B); + + assign B = {8'b00000000, A[8] | A[7] | A[6] | A[5] | A[4] | A[3] | A[2] | A[1] | A[0]}; + // 0 if zero + // 1 if non-zero endmodule \ No newline at end of file diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v index f158e15..1a71d31 100644 --- a/lab2CA.srcs/sources_1/new/CPU9bits.v +++ b/lab2CA.srcs/sources_1/new/CPU9bits.v @@ -5,43 +5,127 @@ module CPU9bits(input wire [8:0] instr, output reg done ); - wire [8:0] op1, op2; + wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut; + wire [2:0] FU, aluOp; + wire addiS, RegEn, loadS; RegFile RF( .clk(clk), .reset(reset), - .enable(), - .write_index(), - .op0_idx(), - .op1_idx(), - .write_data(), + .enable(RegEn), + .write_index(instr[4:3]), + .op0_idx(instr[4:3]), + .op1_idx(instr[2:1]), + .write_data(RFIn), .op0(op0), .op1(op1) ); - FetchUnit FU( + FetchUnit FetchU( .clk(clk), .reset(reset), - .op_idx(), - .AddrIn(), - .AddrOut() + .op_idx(FU[0]), + .AddrIn(FUAddr), + .AddrOut(PCout) ); ALU alu( - .opcode(), + .opcode(aluOp), .operand0(op0), .operand1(op1), - .result() + .result(AluOut) ); - //Make control unit here + ControlUnit CU( + .instIn(instr[8:5]), + .functBit(instr[0]), + .aluOut(aluOp), + .FU(FU), + .addi(addiS), + .mem(loadS), + .load(loadMux) + ); - always @(instr) begin - case (instr) - 9'b000000000: //something - endcase - end - //------------------------------ + //-----------------------Fetch Unit Stuff + + add_9bit JBAdder( + .A(PCout), + .B(JBRes), + .Cin(9'b000000000), + .Sum(FUJB)); + + mux_2_1 mux1( + .A(op1), + .B(FUJB), + .out(FUAddr), + .switch(FU[1])); + + mux_2_1 mux2( + .A({4'b0000,instr[4:0]}), + .B({6'b000000,instr[2:0]}), + .out(JBRes), + .switch(FU[2])); + + ///--------------------------Addi Stuff + + add_9bit Addier( + .A({6'b000000,instr[2:0]}), + .B(op1), + .Cin(9'b000000000), + .Sum(AddiOut)); + + mux_2_1 mux3( + .A(AluOut), + .B(AddiOut), + .out(loadMux), + .switch(addiS)); + + mux_2_1 mux4( + .A(loadMux), + .B(dataMemOut), + .out(RFIn), + .switch(loadS)); + endmodule + +module CPU9bits_tb(); + reg [8:0] instruction; + reg clk, reset; + wire done; + + initial begin + clk = 1'b0; + end + always begin + #5 clk = ~clk; // Period to be determined + end + + CPU9bits CPU9bits0( + .instr(instruction), + .reset(reset), + .clk(clk), + .done(done)); + + initial begin + reset = 0; + #10 + reset = 1; + #10 + instruction = 000100000; + #10 + instruction = 000101001; + #10 + instruction = 010100010; + #10 + instruction = 111100000; + #10 + instruction = 111100000; + #10 + instruction = 000000000; + #10 + $finish; + + end +endmodule \ No newline at end of file diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v new file mode 100644 index 0000000..90d7f1a --- /dev/null +++ b/lab2CA.srcs/sources_1/new/ControlUnit.v @@ -0,0 +1,135 @@ +`timescale 1ns / 1ps + +module ControlUnit( + input wire [3:0] instIn, + input wire functBit, + output reg [3:0] aluOut, + output reg [2:0] FU, + output reg addi, + output reg mem, + output reg load, + output reg RegEn); + + always @(instIn)begin + case(instIn) + 4'b0101: + if(functBit == 1) begin + aluOut <= 4'b0001; //sub + RegEn <= 1'b0; + end + else begin + aluOut <= 4'b0000; //Add + RegEn <= 1'b0; + end + 4'b1101: begin + aluOut <= 4'b0011; //nor + RegEn <= 1'b0; + end + 4'b1110: + if(functBit == 1) begin + aluOut <= 4'b0100; //and + RegEn <= 1'b0; + end + else begin + aluOut <= 4'b0010; //or + RegEn <= 1'b0; + end + 4'b1111: + if(functBit == 1) begin + aluOut <= 4'b0110; //srl + RegEn <= 1'b0; + end + else begin + aluOut <= 4'b0101; //shift left + RegEn <= 1'b0; + end + 4'b0111: begin + aluOut <= 4'b1001; //Less than + RegEn <= 1'b0; + end + 4'b0110: begin + addi <= 1'b1; // addi + RegEn <= 1'b0; + end + 4'b1001: begin + FU <= 3'b010; // jump + RegEn <= 1'b1; + end + 4'b1100: begin + FU <= 3'b011; // branch + RegEn <= 1'b1; + end + 4'b1000: begin + FU <= 3'b001; // jumpreg + RegEn <= 1'b1; + end + 4'b0001: begin + mem <= 1'b0; // load + RegEn <= 1'b0; + end + 4'b0010: begin + mem <= 1'b1; // store + RegEn <= 1'b1; + end + default: aluOut <= 4'bxxxx; + endcase + end +endmodule + + +module ControlUnit_tb(); + reg [3:0] instruction; + reg functionB; + wire [3:0] aluOutput; + wire [2:0] FetchUnit; + wire addImmediate; + wire memory; + wire loadIt; + wire RegEnable; + + + ControlUnit ControlUnit0( + .instIn(instruction), + .functBit(functionB), + .aluOut(aluOutput), + .FU(FetchUnit), + .addi(addImmediate), + .mem(memory), + .load(loadIt), + .RegEn(RegEnable) + ); + + initial begin + functionB = 1'b0; + instruction = 4'b0101; + #5 + functionB = 1'b1; + #5 + functionB = 1'b0; + instruction = 4'b1110; + #5 + functionB = 1'b1; + #5 + functionB = 1'b0; + instruction = 4'b1111; + #5 + functionB = 1'b1; + #5 + instruction = 4'b0111; + #5 + instruction = 4'b0110; + #5 + instruction = 4'b1001; + #5 + instruction = 4'b1100; + #5 + instruction = 4'b1000; + #5 + instruction = 4'b0001; + #5 + instruction = 4'b0010; + #5 + $finish; + + end +endmodule diff --git a/lab2CA.srcs/sources_1/new/FetchUnit.v b/lab2CA.srcs/sources_1/new/FetchUnit.v index 5647473..2087d03 100644 --- a/lab2CA.srcs/sources_1/new/FetchUnit.v +++ b/lab2CA.srcs/sources_1/new/FetchUnit.v @@ -1,7 +1,7 @@ `timescale 1ns / 1ps module FetchUnit(input wire clk, reset, - input wire [1:0] op_idx, + input wire op_idx, input wire [8:0] AddrIn, output wire [8:0] AddrOut); diff --git a/lab2CA.xpr b/lab2CA.xpr index d9ef102..3099e78 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - +