From 460fc3e4ed89297abc8aa42b29fcac76ef5915e2 Mon Sep 17 00:00:00 2001 From: Johannes Date: Sun, 10 Mar 2019 16:32:25 -0400 Subject: [PATCH 01/20] CPU LOTS --- lab2CA.cache/wt/webtalk_pa.xml | 62 ++++++++++-------- lab2CA.srcs/sources_1/new/ALU.v | 2 +- lab2CA.srcs/sources_1/new/CPU9bits.v | 84 +++++++++++++++++++------ lab2CA.srcs/sources_1/new/ControlUnit.v | 74 ++++++++++++++++++++++ lab2CA.srcs/sources_1/new/FetchUnit.v | 2 +- lab2CA.xpr | 28 +++++---- 6 files changed, 191 insertions(+), 61 deletions(-) create mode 100644 lab2CA.srcs/sources_1/new/ControlUnit.v diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 50c4710..697bd6c 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,17 +17,18 @@ This means code written to parse this file will need to be revisited each subseq + - + - + - - + + @@ -36,67 +37,74 @@ This means code written to parse this file will need to be revisited each subseq + - - + + - + - - + + - + - + + + + + - + - + + - - + + - - + + - - + + - - + + + - + - + - + - + - +
diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v index 664cd6e..c5589c5 100644 --- a/lab2CA.srcs/sources_1/new/ALU.v +++ b/lab2CA.srcs/sources_1/new/ALU.v @@ -44,7 +44,7 @@ module ALU( shift_logical_right slr( .A(operand0), .B(result_G)); - // H (111) + // H (111) //slt // MUX chooses which result to show based on the ALU's opcode diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v index f158e15..9b9826f 100644 --- a/lab2CA.srcs/sources_1/new/CPU9bits.v +++ b/lab2CA.srcs/sources_1/new/CPU9bits.v @@ -5,43 +5,87 @@ module CPU9bits(input wire [8:0] instr, output reg done ); - wire [8:0] op1, op2; + wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut; + wire [2:0] FU, aluOp; + wire addiS, RegEn, loadS; RegFile RF( .clk(clk), .reset(reset), - .enable(), - .write_index(), - .op0_idx(), - .op1_idx(), - .write_data(), + .enable(RegEn), + .write_index(instr[4:3]), + .op0_idx(instr[4:3]), + .op1_idx(instr[2:1]), + .write_data(RFIn), .op0(op0), .op1(op1) ); - FetchUnit FU( + FetchUnit FetchU( .clk(clk), .reset(reset), - .op_idx(), - .AddrIn(), - .AddrOut() + .op_idx(FU[0]), + .AddrIn(FUAddr), + .AddrOut(PCout) ); ALU alu( - .opcode(), + .opcode(aluOp), .operand0(op0), .operand1(op1), - .result() + .result(AluOut) ); - //Make control unit here + ControlUnit CU( + .instIn(instr[8:5]), + .functBit(instr[0]), + .aluOut(aluOp), + .FU(FU), + .addi(addiS), + .mem(loadS), + .load(loadMux) + ); - always @(instr) begin - case (instr) - 9'b000000000: //something - endcase - end - //------------------------------ + //-----------------------Fetch Unit Stuff + + add_9bit JBAdder( + .A(PCout), + .B(JBRes), + .Cin(9'b000000000), + .Sum(FUJB)); + + mux_2_1 mux1( + .A(op1), + .B(FUJB), + .out(FUAddr), + .switch(FU[1])); + + mux_2_1 mux2( + .A({4'b0000,instr[4:0]}), + .B({6'b000000,instr[2:0]}), + .out(JBRes), + .switch(FU[2])); + + ///--------------------------Addi Stuff + + add_9bit Addier( + .A({6'b000000,instr[2:0]}), + .B(op1), + .Cin(9'b000000000), + .Sum(AddiOut)); + + mux_2_1 mux3( + .A(AluOut), + .B(AddiOut), + .out(loadMux), + .switch(addiS)); + + mux_2_1 mux4( + .A(loadMux), + .B(dataMemOut), + .out(RFIn), + .switch(loadS)); + -endmodule +endmodule \ No newline at end of file diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v new file mode 100644 index 0000000..b5c8f8c --- /dev/null +++ b/lab2CA.srcs/sources_1/new/ControlUnit.v @@ -0,0 +1,74 @@ +`timescale 1ns / 1ps + +module ControlUnit( + input wire [3:0] instIn, + input wire functBit, + output reg [2:0] aluOut, + output reg [2:0] FU, + output reg addi, + output reg mem, + output reg load, + output reg RegEn + ); + + always @(instIn)begin + case(instIn) + 4'b0101: + if(functBit == 1) begin + aluOut <= 3'b001; //sub + RegEn <= 1'b0; + end + else begin + aluOut <= 3'b000; //Add + RegEn <= 1'b0; + end + 4'b0111: begin + aluOut <= 3'b111; //nor + RegEn <= 1'b0; + end + 4'b1110: + if(functBit == 1) begin + aluOut <= 3'b100; //and + RegEn <= 1'b0; + end + else begin + aluOut <= 3'b010; //or + RegEn <= 1'b0; + end + 4'b1111: + if(functBit == 1) begin + aluOut <= 3'b110; //srl + RegEn <= 1'b0; + end + else begin + aluOut <= 3'b101; //sll + RegEn <= 1'b0; + end + 4'b0110: begin + addi <= 1'b1; // addi + RegEn <= 1'b0; + end + 4'b1001: begin + FU <= 3'b010; // jump + RegEn <= 1'b1; + end + 4'b1100: begin + FU <= 3'b011; // branch + RegEn <= 1'b1; + end + 4'b1000: begin + FU <= 3'b001; // jumpreg + RegEn <= 1'b1; + end + 4'b0001: begin + mem <= 1'b0; // load + RegEn <= 1'b0; + end + 4'b0010: begin + mem <= 1'b1; // store + RegEn <= 1'b1; + end + default: aluOut <= 3'bxxxx; + endcase + end + endmodule diff --git a/lab2CA.srcs/sources_1/new/FetchUnit.v b/lab2CA.srcs/sources_1/new/FetchUnit.v index 5647473..2087d03 100644 --- a/lab2CA.srcs/sources_1/new/FetchUnit.v +++ b/lab2CA.srcs/sources_1/new/FetchUnit.v @@ -1,7 +1,7 @@ `timescale 1ns / 1ps module FetchUnit(input wire clk, reset, - input wire [1:0] op_idx, + input wire op_idx, input wire [8:0] AddrIn, output wire [8:0] AddrOut); diff --git a/lab2CA.xpr b/lab2CA.xpr index d9ef102..5c02702 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - +