diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v index 14e02a7..4e77cc8 100644 --- a/lab2CA.srcs/sources_1/new/ControlUnit.v +++ b/lab2CA.srcs/sources_1/new/ControlUnit.v @@ -15,9 +15,73 @@ module ControlUnit( always @(instIn, functBit)begin case(instIn) - 4'b0101: - if(functBit == 1) begin - aluOut <= 4'b0001; //sub + 4'b0000: // Halt/NOP + begin + halt <= 1'b1; + RegEn <= 1'b1; + FU <= 3'b001; // Disable Branching + addi <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0001: // Load Byte + begin + aluOut <= 4'b0000; + mem <= 1'b1; + dataMemEn <= 1'b0; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + addi <= 1'b0; + halt <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0010: // Store Byte + begin + aluOut <= 4'b0000; + mem <= 1'b0; + dataMemEn <= 1'b1; + RegEn <= 1'b1; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0011: // Link + begin + halt <= 1'b0; + RegEn <= 1'b0; + FU <= 3'b001; + addi <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b0; + dataMemEn <= 1'b0; + link <= 1'b1; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0100: // Zero + begin + aluOut <= 4'b1011; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0101: // Add/Subtract + if(functBit == 1) begin // Subtract + aluOut <= 4'b0001; RegEn <= 1'b0; FU <= 3'b001; halt <= 1'b0; @@ -28,8 +92,8 @@ module ControlUnit( bank <= 2'b10; js <= 1'b0; end - else begin - aluOut <= 4'b0000; //Add + else begin // Add + aluOut <= 4'b0000; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching halt <= 1'b0; @@ -40,33 +104,22 @@ module ControlUnit( bank <= 2'b10; js <= 1'b0; end - 4'b1101: begin - aluOut <= 4'b0011; //nor - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b0100: begin - aluOut <= 4'b1011; //zero - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b1110: - if(functBit == 1) begin - aluOut <= 4'b0100; //and + 4'b0110: // Add Immediate + begin + aluOut <= 4'b1010; + addi <= 1'b1; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b0111: // Set if Less Than + begin + aluOut <= 4'b1001; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching halt <= 1'b0; @@ -77,8 +130,100 @@ module ControlUnit( bank <= 2'b10; js <= 1'b0; end - else begin - aluOut <= 4'b0010; //or + 4'b1000: // Jump to Register + begin + aluOut <= 4'b0000; + FU <= 3'b000; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b1001: // Jump Forward + begin + aluOut <= 4'b0000; + FU <= 3'b010; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b1010: // Bank Load/Bank Store + begin + halt <= 1'b0; + RegEn <= !functBit; + FU <= 3'b001; // Disable Branching + addi <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b0; + link <= 1'b0; + bank <= {functBit,functBit}; + js <= 1'b0; + end + 4'b1011: // Jump Backward + begin + aluOut <= 4'b0000; + FU <= 3'b010; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b1; + end + 4'b1100: // Branch if Zero + begin + aluOut <= 4'b1010; + FU <= 3'b110; + RegEn <= 1'b1; + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b1101: // NOR + begin + aluOut <= 4'b0011; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + 4'b1110: // OR/AND + if(functBit == 1) // AND + begin + aluOut <= 4'b0100; + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + dataMemEn <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; + end + else // OR + begin + aluOut <= 4'b0010; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching halt <= 1'b0; @@ -89,9 +234,10 @@ module ControlUnit( bank <= 2'b10; js <= 1'b0; end - 4'b1111: - if(functBit == 1) begin - aluOut <= 4'b0110; //srl + 4'b1111: // Shift Right Logical/Shift Left Logical + if(functBit == 1) // Shift Right Logical + begin + aluOut <= 4'b0110; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching halt <= 1'b0; @@ -102,8 +248,9 @@ module ControlUnit( bank <= 2'b10; js <= 1'b0; end - else begin - aluOut <= 4'b0101; //shift left + else // Shift Left Logical + begin + aluOut <= 4'b0101; RegEn <= 1'b0; FU <= 3'b001; // Disable Branching halt <= 1'b0; @@ -114,161 +261,31 @@ module ControlUnit( bank <= 2'b10; js <= 1'b0; end - 4'b0111: begin - aluOut <= 4'b1001; //Less than - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; + default: + begin + halt <= 1'b1; + RegEn <= 1'b1; + FU <= 3'b001; + addi <= 1'b0; + aluOut <= 4'b0000; + mem <= 1'b0; + link <= 1'b0; + bank <= 2'b10; + js <= 1'b0; end - 4'b0110: begin - aluOut <= 4'b1010; - addi <= 1'b1; // addi - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b1001: begin - aluOut <= 4'b0000; - FU <= 3'b010; // jf - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b1011: begin - aluOut <= 4'b0000; - FU <= 3'b010; // jb - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b1; - end - 4'b0011: begin // link - halt <= 1'b0; - RegEn <= 1'b0; - FU <= 3'b001; - addi <= 1'b0; - aluOut <= 4'b0000; - mem <= 1'b0; - dataMemEn <= 1'b0; - link <= 1'b1; - bank <= 2'b10; - js <= 1'b0; - end - 4'b1100: begin - aluOut <= 4'b1010; - FU <= 3'b110; // branch - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b1000: begin - aluOut <= 4'b0000; - FU <= 3'b000; // jumpreg - RegEn <= 1'b1; - halt <= 1'b0; - addi <= 1'b0; - mem <= 1'b0; - dataMemEn <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b0001: begin - aluOut <= 4'b0000; - mem <= 1'b1; // load - dataMemEn <= 1'b0; - RegEn <= 1'b0; - FU <= 3'b001; // Disable Branching - addi <= 1'b0; - halt <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b0010: begin - aluOut <= 4'b0000; - mem <= 1'b0; // store - dataMemEn <= 1'b1; - RegEn <= 1'b1; - FU <= 3'b001; // Disable Branching - halt <= 1'b0; - addi <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - 4'b1010: begin - halt <= 1'b0; // bank - RegEn <= !functBit; - FU <= 3'b001; // Disable Branching - addi <= 1'b0; - aluOut <= 4'b0000; - mem <= 1'b0; - link <= 1'b0; - bank <= {functBit,functBit}; - js <= 1'b0; - end - 4'b0000: begin - halt <= 1'b1; // halt - RegEn <= 1'b1; - FU <= 3'b001; // Disable Branching - addi <= 1'b0; - aluOut <= 4'b0000; - mem <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end - default: begin - halt <= 1'b1; - RegEn <= 1'b1; - FU <= 3'b001; - addi <= 1'b0; - aluOut <= 4'b0000; - mem <= 1'b0; - link <= 1'b0; - bank <= 2'b10; - js <= 1'b0; - end endcase end endmodule - - + + module ControlUnit_tb(); reg [3:0] instruction; reg functionB; + wire [3:0] aluOutput; wire [2:0] FetchUnit; - wire addImmediate; - wire memory; - wire RegEnable; - + wire addImmediate, memory, RegEnable; + ControlUnit ControlUnit0( .instIn(instruction),