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This commit is contained in:
jose.rodriguezlabra
2019-03-24 14:16:03 -04:00
parent bab680ea27
commit 94f0267a13
37 changed files with 2345 additions and 27 deletions
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26
lab2CA.srcs/sources_1/new/CPU9bits.v
View File

@@ -5,11 +5,11 @@ module CPU9bits(
output wire done
);
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP;
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP,jumpNeg;
wire [2:0] FU;
wire [3:0] aluOp;
wire [1:0] bankS;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js;
instructionMemory iM(
.clk(clk),
@@ -74,7 +74,8 @@ module CPU9bits(
.RegEn(RegEn),
.halt(done),
.link(link),
.bank(bankS)
.bank(bankS),
.js(js)
);
@@ -87,12 +88,23 @@ module CPU9bits(
.Sum(FUJB),
.Cout(cout0));
mux_2_1 mux1(
mux_2_1 mux0(
.A(op0),
.B(FUJB),
.out(FUAddr),
.switch(FU[1]));
twos_compliment_9bit two_comp0(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg));
mux_2_1 mux1(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg),
.out(SE2N),
.switch(js));
mux_2_1 mux2(
.A(SE2N), //Jump -- Change with signer module!
.B(SE1N),//Branch -- Change with signer module!
@@ -102,11 +114,7 @@ module CPU9bits(
sign_extend_3bit SE1(
.A(instr[2:0]),
.B(SE1N));
sign_extend_5bit SE2(
.A(instr[4:0]),
.B(SE2N));
bit1_mux_2_1 BranMux( // BEQ MUX
.A(FU[0]),
.B(op0[0]),

35
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -10,7 +10,8 @@ module ControlUnit(
output reg RegEn,
output reg halt,
output reg link,
output reg [1:0] bank);
output reg [1:0] bank,
output reg js);
always @(instIn, functBit)begin
case(instIn)
@@ -24,6 +25,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin
aluOut <= 4'b0000; //Add
@@ -34,6 +36,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1101: begin
aluOut <= 4'b0011; //nor
@@ -44,6 +47,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0100: begin
aluOut <= 4'b1011; //zero
@@ -54,6 +58,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1110:
if(functBit == 1) begin
@@ -65,6 +70,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin
aluOut <= 4'b0010; //or
@@ -75,6 +81,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1111:
if(functBit == 1) begin
@@ -86,6 +93,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin
aluOut <= 4'b0101; //shift left
@@ -96,6 +104,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0111: begin
aluOut <= 4'b1001; //Less than
@@ -106,6 +115,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0110: begin
aluOut <= 4'b0000;
@@ -116,16 +126,29 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1001: begin
aluOut <= 4'b0000;
FU <= 3'b010; // jump
FU <= 3'b010; // jf
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1011: begin
aluOut <= 4'b0000;
FU <= 3'b010; // jb
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
end
4'b0011: begin // link
halt <= 1'b0;
@@ -136,6 +159,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
end
4'b1100: begin
aluOut <= 4'b0000;
@@ -146,6 +170,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1000: begin
aluOut <= 4'b0000;
@@ -156,6 +181,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0001: begin
aluOut <= 4'b0000;
@@ -166,6 +192,7 @@ module ControlUnit(
halt <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0010: begin
aluOut <= 4'b0000;
@@ -176,6 +203,7 @@ module ControlUnit(
addi <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1010: begin
halt <= 1'b0; // bank
@@ -186,6 +214,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= {functBit,functBit};
js <= 1'b0;
end
4'b0000: begin
halt <= 1'b1; // halt
@@ -196,6 +225,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
default: begin
halt <= 1'b1;
@@ -206,6 +236,7 @@ module ControlUnit(
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
endcase
end