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This commit is contained in:
jose.rodriguezlabra
2019-03-24 14:16:03 -04:00
parent bab680ea27
commit 94f0267a13
37 changed files with 2345 additions and 27 deletions
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26
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -5,11 +5,11 @@ module CPU9bits(
output wire done
);
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP;
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP,jumpNeg;
wire [2:0] FU;
wire [3:0] aluOp;
wire [1:0] bankS;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js;
instructionMemory iM(
.clk(clk),
@@ -74,7 +74,8 @@ module CPU9bits(
.RegEn(RegEn),
.halt(done),
.link(link),
.bank(bankS)
.bank(bankS),
.js(js)
);
@@ -87,12 +88,23 @@ module CPU9bits(
.Sum(FUJB),
.Cout(cout0));
mux_2_1 mux1(
mux_2_1 mux0(
.A(op0),
.B(FUJB),
.out(FUAddr),
.switch(FU[1]));
twos_compliment_9bit two_comp0(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg));
mux_2_1 mux1(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg),
.out(SE2N),
.switch(js));
mux_2_1 mux2(
.A(SE2N), //Jump -- Change with signer module!
.B(SE1N),//Branch -- Change with signer module!
@@ -102,11 +114,7 @@ module CPU9bits(
sign_extend_3bit SE1(
.A(instr[2:0]),
.B(SE1N));
sign_extend_5bit SE2(
.A(instr[4:0]),
.B(SE2N));
bit1_mux_2_1 BranMux( // BEQ MUX
.A(FU[0]),
.B(op0[0]),