From 9519460187345fad4cbbb91cb047753151c06ee0 Mon Sep 17 00:00:00 2001
From: WilliamMiceli <git@williammiceli.me>
Date: Tue, 12 Mar 2019 10:43:16 -0400
Subject: [PATCH] AND is bitwise, so simplified, removing 1-bit modules

---
 lab2CA.srcs/sources_1/new/BasicModules.v | 82 +-----------------------
 1 file changed, 1 insertion(+), 81 deletions(-)

diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index a4ea6c7..6ba51a9 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -172,92 +172,12 @@ module add9bit_tb();
     end
 endmodule
 
-module and_1bit(
-    input wire A,
-    input wire B,
-    output wire C);
-
-    assign C = A & B;
-
-endmodule
-
-//testbench
-module and1bit_tb();
-    reg a,b;
-    wire c;
-
-    and_1bit and0(
-        .A(a),
-        .B(b),
-        .C(c));
-    
-    initial begin
-        a = 0;
-        b = 0;
-        #5
-        a = 0;
-        b = 1;
-        #5
-        a = 1;
-        b = 0;
-        #5
-        a = 1;
-        b = 1;
-        #5
-        $finish;
-
-    end
-endmodule
-
 module and_9bit(
     input wire [8:0] A,
     input wire [8:0] B,
     output wire [8:0] C);
 
-    and_1bit and0(
-        .A(A[0]),
-        .B(B[0]),
-        .C(C[0]));
-
-    and_1bit and1(
-        .A(A[1]),
-        .B(B[1]),
-        .C(C[1]));
-        
-    and_1bit and2(
-        .A(A[2]),
-        .B(B[2]),
-        .C(C[2]));
-        
-    and_1bit and3(
-        .A(A[3]),
-        .B(B[3]),
-        .C(C[3]));
-        
-    and_1bit and4(
-        .A(A[4]),
-        .B(B[4]),
-        .C(C[4]));
-    
-    and_1bit and5(
-        .A(A[5]),
-        .B(B[5]),
-        .C(C[5]));
-        
-    and_1bit and6(
-        .A(A[6]),
-        .B(B[6]),
-        .C(C[6]));
-        
-    and_1bit and7(
-        .A(A[7]),
-        .B(B[7]),
-        .C(C[7]));
-        
-    and_1bit and8(
-        .A(A[8]),
-        .B(B[8]),
-        .C(C[8]));
+    assign C = A & B;
 
 endmodule