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WilliamMiceli
2019-02-19 21:15:27 -05:00
parent 54cccd419f
commit 962374d58f
2 changed files with 0 additions and 110 deletions
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26
lab2CA.srcs/sources_1/new/fetchFile.v
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@@ -1,26 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/08/2019 06:21:32 PM
// Design Name:
// Module Name: fetchFile
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fetchFile(
);
endmodule

84
lab2CA.srcs/sources_1/new/lab2testing.v
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@@ -1,84 +0,0 @@
`timescale 1ns / 1ps
module lab2testing();
endmodule
module regFile(input wire clk, reset,
input wire [1:0] write_index, op0_idx, op1_idx,
input wire [8:0] write_data,
output wire [8:0] op0, op1);
wire [8:0] r0_out, r1_out, r2_out, r3_out;
// To select a register En input must be 2'b00
register r0(
.clk(clk),
.reset(reset),
.En({write_index[0], write_index[1]}),
.Din(write_data),
.Dout(r0_out));
register r1(
.clk(clk),
.reset(reset),
.En({write_index[0], ~write_index[1]}),
.Din(write_data),
.Dout(r1_out));
register r2(
.clk(clk),
.reset(reset),
.En({~write_index[0], write_index[1]}),
.Din(write_data),
.Dout(r2_out));
register r3(
.clk(clk),
.reset(reset),
.En({~write_index[0], ~write_index[1]}),
.Din(write_data),
.Dout(r3_out));
Mux m0(
.A(r0_out),
.B(r1_out),
.C(r2_out),
.D(r3_out),
.switch(op0_idx));
Mux m1(
.A(r0_out),
.B(r1_out),
.C(r2_out),
.D(r3_out),
.switch(op1_idx));
<<<<<<< Updated upstream
endmodule
=======
endmodule
module register(input wire clk, reset,
input wire [1:0] En,
input wire [7:0] Din,
output reg [7:0] Dout);
endmodule
module MUX();
endmodule
module fetchUnit(input wire clk, reset, write_en);
register progcount(
.clk(clk),
.reset(reset),
.En(),
.Din(),
.Dout());
endmodule
>>>>>>> Stashed changes