From 97433c36910f1a4b4940607100d3ad1e730acb59 Mon Sep 17 00:00:00 2001
From: WilliamMiceli <git@williammiceli.me>
Date: Tue, 12 Mar 2019 11:17:03 -0400
Subject: [PATCH] Shift right arithmetic implemented into ALU

---
 lab2CA.srcs/sources_1/new/ALU.v          | 12 +++++++-
 lab2CA.srcs/sources_1/new/BasicModules.v | 37 ++++++++++++++++++++++++
 2 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v
index d5fa0c8..388bdba 100644
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -45,7 +45,17 @@ module ALU(
         .A(operand0),
         .B(result_G));
     // H (0111) - Shift Right Arithmetic
-    
+    shift_right_arithmetic sra(
+        .A(operand0),
+        .B(result_H));
+    // I (1000)
+    // J (1001)
+    // K (1010)
+    // L (1011)
+    // M (1100)
+    // N (1101)
+    // O (1110)
+    // P (1111)
     
     // MUX chooses which result to show based on the ALU's opcode
     mux_16_1 mux0(
diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index 109a95d..0f81f0b 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -847,6 +847,43 @@ module shift_right_logical_tb();
     end
 endmodule
 
+module shift_right_arithmetic(
+    input wire [8:0] A,
+    output wire [8:0] B);
+    
+    assign B = {A[8],A[8:1]};
+
+endmodule
+
+//testbench
+module shift_right_arithmetic_tb();
+    reg [8:0] a;
+    wire [8:0] b;
+
+    shift_right_arithmetic tb0(
+        .A(a),
+        .B(b));
+
+    initial begin
+        a = 9'b000000000;
+        #5
+        a = 9'b000000001;
+        #5
+        a = 9'b000111000;
+        #5
+        a = 9'b010101010;
+        #5
+        a = 9'b101010101;
+        #5
+        a = 9'b111111111;
+        #5
+        a = 9'b100000001;
+        #5
+        $finish;
+
+    end
+endmodule
+
 module sub_9bit(
     input wire [8:0] A,
     input wire [8:0] B,