From 9ac8963fb0547b2637e319a257b9e29b65694f95 Mon Sep 17 00:00:00 2001
From: WilliamMiceli <git@williammiceli.me>
Date: Tue, 12 Mar 2019 11:12:21 -0400
Subject: [PATCH] ALU now fully has 4-bit opcode

---
 lab2CA.srcs/sources_1/new/ALU.v | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v
index 813ef54..bac2489 100644
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -8,7 +8,7 @@ module ALU(
     );
     
     // Wires for connecting the modules to the mux
-    wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H;
+    wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P;
     
     // A (0000) - Add
     add_9bit add0(
@@ -48,7 +48,7 @@ module ALU(
     
     
     // MUX chooses which result to show based on the ALU's opcode
-    mux_8_1 mux0(
+    mux_16_1 mux0(
         .switch(opcode),
         .A(result_A),
         .B(result_B),
@@ -58,6 +58,14 @@ module ALU(
         .F(result_F),
         .G(result_G),
         .H(result_H),
+        .I(result_I),
+        .J(result_J),
+        .K(result_K),
+        .L(result_L),
+        .M(result_M),
+        .N(result_N),
+        .O(result_O),
+        .P(result_P),
         .out(result));
 
 endmodule