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This commit is contained in:
goochey
2019-02-20 11:40:43 -05:00
parent 6550b48599
commit 9ba63880bd
33 changed files with 234 additions and 197 deletions
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BIN
lab2CA.runs/synth_1/FetchUnit.dcp
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4
lab2CA.runs/synth_1/FetchUnit.tcl
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@@ -17,10 +17,6 @@ proc create_report { reportName command } {
send_msg_id runtcl-5 warning "$msg"
}
}
set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2460-DESKTOP-8QFGS52/incrSyn
set_msg_config -id {Common 17-41} -limit 10000000
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
create_project -in_memory -part xc7k160tifbg484-2L
set_param project.singleFileAddWarning.threshold 0

57
lab2CA.runs/synth_1/FetchUnit.vds
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 17:27:36 2019
# Process ID: 2948
# Start of session at: Wed Feb 20 11:35:49 2019
# Process ID: 8280
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds
@@ -15,9 +15,9 @@ Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 2932
INFO: Helper process launched with PID 5464
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.449 ; gain = 101.293
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.242 ; gain = 98.211
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
@@ -26,28 +26,30 @@ INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:53]
WARNING: [Synth 8-350] instance 'PCAdder' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:17]
WARNING: [Synth 8-350] instance 'PCAdder' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:18]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:312]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:312]
WARNING: [Synth 8-689] width (2) of port connection 'switch' does not match port width (1) of module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:28]
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
WARNING: [Synth 8-3331] design FetchUnit has unconnected port op_idx[1]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.078 ; gain = 156.922
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.078 ; gain = 156.922
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.078 ; gain = 156.922
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Synth 8-5544] ROM "Dout" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.078 ; gain = 156.922
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -105,8 +107,9 @@ No constraint files found.
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
WARNING: [Synth 8-3331] design FetchUnit has unconnected port op_idx[1]
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.293 ; gain = 323.137
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.582 ; gain = 320.551
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -119,7 +122,7 @@ No constraint files found.
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.293 ; gain = 323.137
Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.582 ; gain = 320.551
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -131,7 +134,7 @@ Report RTL Partitions:
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.293 ; gain = 323.137
Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.582 ; gain = 320.551
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -155,7 +158,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137
Finished IO Insertion : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
---------------------------------------------------------------------------------
Report Check Netlist:
@@ -168,7 +171,7 @@ Report Check Netlist:
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137
Finished Renaming Generated Instances : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -180,25 +183,25 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137
Finished Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137
Finished Renaming Generated Nets : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -234,25 +237,25 @@ Report Instance Areas:
|2 | PC |register | 29|
+------+---------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137
Finished Writing Synthesis Report : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137
Synthesis Optimization Complete : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137
Synthesis finished with 0 errors, 0 critical warnings and 4 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
Synthesis Optimization Complete : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 680.656 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.250 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
19 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
19 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 680.656 ; gain = 430.656
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 680.656 ; gain = 0.000
synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 682.250 ; gain = 421.219
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.250 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 17:28:01 2019...
INFO: [Common 17-206] Exiting Vivado at Wed Feb 20 11:36:14 2019...

2
lab2CA.runs/synth_1/FetchUnit_utilization_synth.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:28:01 2019
| Date : Wed Feb 20 11:36:14 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb
| Design : FetchUnit

10
lab2CA.runs/synth_1/gen_run.xml
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@@ -1,11 +1,14 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550356053">
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550680547">
<File Type="PA-TCL" Name="FetchUnit.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="FetchUnit_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
<File Type="RDS-RDS" Name="FetchUnit.vds"/>
<File Type="RDS-UTIL" Name="FetchUnit_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="FetchUnit_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="FetchUnit.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="FetchUnit_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="FetchUnit_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
@@ -22,7 +25,7 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
<File Path="$PSRCDIR/sources_1/new/ALU.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -30,7 +33,7 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ALU.v">
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -41,7 +44,6 @@
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="FetchUnit"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">

4
lab2CA.runs/synth_1/vivado.jou
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 17:27:36 2019
# Process ID: 2948
# Start of session at: Wed Feb 20 11:35:49 2019
# Process ID: 8280
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds

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lab2CA.runs/synth_1/vivado.pb
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