From 9db4c1253b69ef859e8e863a413af7c6b6f51768 Mon Sep 17 00:00:00 2001
From: WilliamMiceli <git@williammiceli.me>
Date: Fri, 29 Mar 2019 17:22:06 -0400
Subject: [PATCH] Fixed unconnected wires/ports

---
 lab2CA.srcs/sources_1/new/BasicModules.v | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index d033266..f1f476a 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -851,7 +851,7 @@ module register_tb();
 endmodule 
     
 module shift_left(
-    input wire [8:0] A,
+    input wire [7:0] A,
     output wire [8:0] B);
     
     assign B = {A[7:0],1'b0};
@@ -887,20 +887,20 @@ module shift_left_tb();
     end
 endmodule
 
-module shift_right_logical(
-    input wire [8:0] A,
+module shift_right_arithmetic(
+    input wire [8:1] A,
     output wire [8:0] B);
     
-    assign B = {1'b0,A[8:1]};
+    assign B = {A[8],A[8:1]};
 
 endmodule
 
 //testbench
-module shift_right_logical_tb();
+module shift_right_arithmetic_tb();
     reg [8:0] a;
     wire [8:0] b;
 
-    shift_right_logical tb0(
+    shift_right_arithmetic tb0(
         .A(a),
         .B(b));
 
@@ -924,21 +924,21 @@ module shift_right_logical_tb();
     end
 endmodule
 
-module shift_right_arithmetic(
-    input wire [8:0] A,
+module shift_right_logical(
+    input wire [8:1] A,
     output wire [8:0] B);
     
-    assign B = {A[8],A[8:1]};
+    assign B = {1'b0,A[8:1]};
+    
 
 endmodule
 
-
 //testbench
-module shift_right_arithmetic_tb();
+module shift_right_logical_tb();
     reg [8:0] a;
     wire [8:0] b;
 
-    shift_right_arithmetic tb0(
+    shift_right_logical tb0(
         .A(a),
         .B(b));