diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v
index c5589c5..95b0519 100644
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -36,12 +36,12 @@ module ALU(
         .A(operand0),
         .B(operand1),
         .C(result_E));
-    // F (101) - Shift Logical Left
-    shift_logical_left sll(
+    // F (101) - Shift Left
+    shift_left sl(
         .A(operand0),
         .B(result_F));
     // G (110) - Shift Logical Right
-    shift_logical_right slr(
+    shift_right_logical srl(
         .A(operand0),
         .B(result_G));
     // H (111) //slt
diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index 4ffd16f..aefd1e7 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -665,7 +665,7 @@ module register_tb();
     end
 endmodule 
     
-module shift_logical_left(
+module shift_left(
     input wire [8:0] A,
     output wire [8:0] B);
     
@@ -674,11 +674,11 @@ module shift_logical_left(
 endmodule
 
 //testbench
-module shift_logical_left_tb();
+module shift_left_tb();
     reg [8:0] a;
     wire [8:0] b;
 
-    shift_logical_left tb0(
+    shift_left tb0(
         .A(a),
         .B(b));
     
@@ -702,7 +702,7 @@ module shift_logical_left_tb();
     end
 endmodule
 
-module shift_logical_right(
+module shift_right_logical(
     input wire [8:0] A,
     output wire [8:0] B);
     
@@ -711,11 +711,11 @@ module shift_logical_right(
 endmodule
 
 //testbench
-module shift_logical_right_tb();
+module shift_right_logical_tb();
     reg [8:0] a;
     wire [8:0] b;
 
-    shift_logical_right tb0(
+    shift_right_logical tb0(
         .A(a),
         .B(b));