diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 697bd6c..326266f 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,7 +17,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -25,10 +25,10 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -39,14 +39,14 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + @@ -55,56 +55,56 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + - - + + - - + + - - + + - - + + - + - + - + - + - +
diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index 0e266f7..e9c85c5 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -943,46 +943,6 @@ module shift_right_arithmetic_tb(); end endmodule -module slt ( - input wire en, - input wire [8:0] inA, inB, - output reg [8:0] outA); - - always @(inA, inB)begin - if (inA < inB) begin - outA = 9'b000000001; - end - else begin - outA = 9'b000000000; - end - end -endmodule - -//testbench -module slt_tb(); - reg [8:0] indexA; - reg [8:0] indexB; - wire outputA; - - slt slt0( - .inA(indexA), - .inB(indexB), - .outA(outputA)); - - initial begin - indexA = 9'b000000000; - indexB = 9'b000000000; - #10 - indexA = 9'b000000000; - indexB = 9'b111100000; - #10 - indexA = 9'b000001111; - indexB = 9'b000000000; - #10 - $finish; - end -endmodule - module sub_9bit( input wire [8:0] A, input wire [8:0] B, diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v index 59bdf83..90d7f1a 100644 --- a/lab2CA.srcs/sources_1/new/ControlUnit.v +++ b/lab2CA.srcs/sources_1/new/ControlUnit.v @@ -44,7 +44,7 @@ module ControlUnit( RegEn <= 1'b0; end 4'b0111: begin - aluOut <= 4'b1001; //slt + aluOut <= 4'b1001; //Less than RegEn <= 1'b0; end 4'b0110: begin