diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index ea30b71..ed7a182 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -263,7 +263,7 @@ module decoder (
     input wire En,
     output reg [3:0] regOut);
     
-    always @ (index)
+    always @ (index, En)
     if (En == 0) begin
         case(index) 
             2'b00: regOut <= 4'b1110; 
diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v
index c46d55c..6c48962 100644
--- a/lab2CA.srcs/sources_1/new/CPU9bits.v
+++ b/lab2CA.srcs/sources_1/new/CPU9bits.v
@@ -4,8 +4,7 @@ module CPU9bits(
     input wire reset, clk,
     output wire [8:0] result,
     output wire done
-    );
-
+        );
     
     wire [8:0] RFIn,FUAddr;
     wire [1:0] instr;
@@ -85,7 +84,7 @@ module CPU9bits_tb();
     	reset = 1'b1;
     	#10
     	reset = 1'b0;
-    	#50
+    	#50000
         $finish;
         
     end
diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v
index a41e2ae..c5b4f75 100644
--- a/lab2CA.srcs/sources_1/new/ControlUnit.v
+++ b/lab2CA.srcs/sources_1/new/ControlUnit.v
@@ -6,7 +6,8 @@ module ControlUnit(
     output reg [3:0] aluOut,
     output reg [2:0] FU,
     output reg [1:0] bank,
-    output reg addi, mem, dataMemEn, RegEn, halt, link, js);
+    output reg addi, mem, dataMemEn, RegEn, halt, link, js
+        );
     
     always @(instIn, functBit)
     begin
diff --git a/lab2CA.srcs/sources_1/new/FetchUnit.v b/lab2CA.srcs/sources_1/new/FetchUnit.v
index 17440c3..08088a7 100644
--- a/lab2CA.srcs/sources_1/new/FetchUnit.v
+++ b/lab2CA.srcs/sources_1/new/FetchUnit.v
@@ -1,9 +1,8 @@
 `timescale 1ns / 1ps
 
 module FetchUnit(
-    input wire clk, reset, 
-    input wire op_idx,
     input wire [8:0] AddrIn,
+    input wire clk, reset, op_idx,
     output wire [8:0] AddrOut
         );