From b2dfc05db8e390ef4312f5bf6b0a56ddb79674ca Mon Sep 17 00:00:00 2001
From: WilliamMiceli <git@williammiceli.io>
Date: Fri, 15 Feb 2019 17:09:44 -0500
Subject: [PATCH] Renamed some things; adder is now implemented in ALU

---
 lab2CA.srcs/sources_1/new/ALU.v | 23 ++++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v
index 8182a07..b6b50c4 100644
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -8,9 +8,14 @@ module ALU(
     );
     
     // Wires for connecting the modules to the mux
-    wire [8:0] A,B,C,D,E,F,G,H;
+    wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H;
     
     // A (000) - Add
+    adder_9bit(
+        .A(operand0),
+        .B(operand1),
+        .Cin(1'b0),
+        .Sum(result_A));
     // B (001) - Subtract
     // C (010) - OR
     // D (011) - NOR
@@ -23,14 +28,14 @@ module ALU(
     // MUX chooses which result to show based on the OPCODE
     mux_8_1 mux_result(
         .switch(opcode),
-        .A(A),
-        .B(B),
-        .C(C),
-        .D(D),
-        .E(E),
-        .F(F),
-        .G(G),
-        .H(H),
+        .A(result_A),
+        .B(result_B),
+        .C(result_C),
+        .D(result_D),
+        .E(result_E),
+        .F(result_F),
+        .G(result_G),
+        .H(result_H),
         .out(result));
 
 endmodule