Fetch Unit Again

I think I did it wrong

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -168,6 +168,20 @@ module gen_clock();
 
 endmodule
 
+module mux_2_1(input wire switch,
+           input wire [8:0] A,B,
+           output reg [8:0] out);
+           
+    always @(A,B,switch) begin
+        case (switch)
+            2'b00 : out = A;
+            2'b01 : out = B;
+            default : out = 9'bxxxxxxxxx;
+        endcase
+    end
+
+endmodule
+
 module mux_4_1(input wire [1:0] switch,
            input wire [8:0] A,B,C,D,
            output reg [8:0] out);