diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index 122e393..f1f476a 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -259,32 +259,43 @@ module comparator_tb();
 endmodule
 
 module decoder (
+    input wire en,
     input wire [1:0] index,
     output reg [3:0] regOut);
     
-    always @ (index)
-    case(index) 
-        2'b00: regOut <= 4'b1110; 
-        2'b01: regOut <= 4'b1101;
-        2'b10: regOut <= 4'b1011;
-        2'b11: regOut <= 4'b0111;
-        default: regOut <= 4'b1111; 
-    endcase
+    always @(en, index)begin
+        if(en == 0)begin
+            case(index) 
+            2'b00: regOut <= 4'b1110; 
+            2'b01: regOut <= 4'b1101;
+            2'b10: regOut <= 4'b1011;
+            2'b11: regOut <= 4'b0111;
+            default: regOut <= 4'b1111; 
+            endcase 
+        end
+        else begin
+            regOut <= 4'b1111; 
+        end
+    end
 endmodule
 
 //testbench
 module decoder_tb();
+    reg enable;
     reg [1:0] indexIn;
     wire [3:0] regOut;
 
     decoder dec0(
+        .en(enable),
         .index(indexIn),
-        .regOut(regOut)
-    );
+        .regOut(regOut));
     
     initial begin
+        enable = 0;
         indexIn = 2'b00;
         #5
+        enable = 1;
+        #5
         indexIn = 2'b01;
         #5
         indexIn = 2'b10;
diff --git a/lab2CA.srcs/sources_1/new/RegFile.v b/lab2CA.srcs/sources_1/new/RegFile.v
index ccd17e3..de3ea8e 100644
--- a/lab2CA.srcs/sources_1/new/RegFile.v
+++ b/lab2CA.srcs/sources_1/new/RegFile.v
@@ -1,6 +1,6 @@
 `timescale 1ns / 1ps
 
-module RegFile(input wire clk, reset,
+module RegFile(input wire clk, reset, enable,
                 input wire [1:0] write_index, op0_idx, op1_idx,
                 input wire [8:0] write_data,
                 output wire [8:0] op0, op1);
@@ -11,6 +11,7 @@ module RegFile(input wire clk, reset,
     // To select a register En input must be 2'b00
     
     decoder d0(
+        .en(enable),
         .index(write_index),
         .regOut(decOut)
     );
@@ -66,7 +67,7 @@ endmodule
 module regFile_tb();
     reg [8:0] write_d;
     reg [1:0] w_idx, op0_idx, op1_idx;
-    reg reset,clk;
+    reg reset,clk, enable;
     wire [8:0] op0,op1;
 
     initial begin
@@ -78,6 +79,7 @@ module regFile_tb();
 
     RegFile regFile0(
         .clk(clk),
+        .enable(enable),
         .reset(reset),
         .write_index(w_idx),
         .op0_idx(op0_idx),
@@ -92,6 +94,7 @@ module regFile_tb();
         reset = 1;
         #5
         reset = 0;
+        enable = 1;
         w_idx = 2'b00;
         op0_idx = 2'b00;
         op1_idx = 2'b00;