diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index d9cd128..81904af 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -992,6 +992,321 @@ module sign_extend_2bit_tb();
     end
 endmodule
 
+module sign_extend_3bit(
+    input wire [2:0] A,
+    output wire [8:0] B);
+
+    assign B = {{6{A[2]}},A};
+
+endmodule
+
+//testbench
+module sign_extend_3bit_tb();
+    reg [2:0] A;
+    wire [8:0] B;
+
+    sign_extend_3bit tb0(
+        .A(A),
+        .B(B));
+
+    initial begin
+        A = 3'b000;
+        #5
+        A = 3'b001;
+        #5
+        A = 3'b010;
+        #5
+        A = 3'b011;
+        #5
+        A = 3'b100;
+        #5
+        A = 3'b101;
+        #5
+        A = 3'b110;
+        #5
+        A = 3'b111;
+        #5
+        $finish;
+
+    end
+endmodule
+
+module sign_extend_4bit(
+    input wire [3:0] A,
+    output wire [8:0] B);
+
+    assign B = {{5{A[3]}},A};
+
+endmodule
+
+//testbench
+module sign_extend_4bit_tb();
+    reg [3:0] A;
+    wire [8:0] B;
+
+    sign_extend_4bit tb0(
+        .A(A),
+        .B(B));
+
+    initial begin
+        A = 4'b0000;
+        #5
+        A = 4'b0001;
+        #5
+        A = 4'b0010;
+        #5
+        A = 4'b0011;
+        #5
+        A = 4'b0100;
+        #5
+        A = 4'b0101;
+        #5
+        A = 4'b0110;
+        #5
+        A = 4'b0111;
+        #5
+        A = 4'b1000;
+        #5
+        A = 4'b1001;
+        #5
+        A = 4'b1010;
+        #5
+        A = 4'b1011;
+        #5
+        A = 4'b1100;
+        #5
+        A = 4'b1101;
+        #5
+        A = 4'b1110;
+        #5
+        A = 4'b1111;
+        #5
+        $finish;
+
+    end
+endmodule
+
+module sign_extend_5bit(
+    input wire [4:0] A,
+    output wire [8:0] B);
+
+    assign B = {{4{A[4]}},A};
+
+endmodule
+
+//testbench
+module sign_extend_5bit_tb();
+    reg [4:0] A;
+    wire [8:0] B;
+
+    sign_extend_5bit tb0(
+        .A(A),
+        .B(B));
+
+    initial begin
+        A = 5'b00000;
+        #5
+        A = 5'b00010;
+        #5
+        A = 5'b00100;
+        #5
+        A = 5'b00110;
+        #5
+        A = 5'b01000;
+        #5
+        A = 5'b01010;
+        #5
+        A = 5'b01100;
+        #5
+        A = 5'b01110;
+        #5
+        A = 5'b10000;
+        #5
+        A = 5'b10010;
+        #5
+        A = 5'b10100;
+        #5
+        A = 5'b10110;
+        #5
+        A = 5'b11000;
+        #5
+        A = 5'b11010;
+        #5
+        A = 5'b11100;
+        #5
+        A = 5'b11110;
+        #5
+        $finish;
+
+    end
+endmodule
+
+module sign_extend_6bit(
+    input wire [5:0] A,
+    output wire [8:0] B);
+
+    assign B = {{3{A[5]}},A};
+
+endmodule
+
+//testbench
+module sign_extend_6bit_tb();
+    reg [5:0] A;
+    wire [8:0] B;
+
+    sign_extend_6bit tb0(
+        .A(A),
+        .B(B));
+
+    initial begin
+        A = 6'b000000;
+        #5
+        A = 6'b000100;
+        #5
+        A = 6'b001000;
+        #5
+        A = 6'b001100;
+        #5
+        A = 6'b010000;
+        #5
+        A = 6'b010100;
+        #5
+        A = 6'b011000;
+        #5
+        A = 6'b011100;
+        #5
+        A = 6'b100000;
+        #5
+        A = 6'b100100;
+        #5
+        A = 6'b101000;
+        #5
+        A = 6'b101100;
+        #5
+        A = 6'b110000;
+        #5
+        A = 6'b110100;
+        #5
+        A = 6'b111000;
+        #5
+        A = 6'b111100;
+        #5
+        $finish;
+
+    end
+endmodule
+
+module sign_extend_7bit(
+    input wire [6:0] A,
+    output wire [8:0] B);
+
+    assign B = {{2{A[6]}},A};
+
+endmodule
+
+//testbench
+module sign_extend_7bit_tb();
+    reg [6:0] A;
+    wire [8:0] B;
+
+    sign_extend_7bit tb0(
+        .A(A),
+        .B(B));
+
+    initial begin
+        A = 7'b0000000;
+        #5
+        A = 7'b0001000;
+        #5
+        A = 7'b0010000;
+        #5
+        A = 7'b0011000;
+        #5
+        A = 7'b0100000;
+        #5
+        A = 7'b0101000;
+        #5
+        A = 7'b0110000;
+        #5
+        A = 7'b0111000;
+        #5
+        A = 7'b1000000;
+        #5
+        A = 7'b1001000;
+        #5
+        A = 7'b1010000;
+        #5
+        A = 7'b1011000;
+        #5
+        A = 7'b1100000;
+        #5
+        A = 7'b1101000;
+        #5
+        A = 7'b1110000;
+        #5
+        A = 7'b1111000;
+        #5
+        $finish;
+
+    end
+endmodule
+
+module sign_extend_8bit(
+    input wire [7:0] A,
+    output wire [8:0] B);
+
+    assign B = {A[7],A};
+
+endmodule
+
+//testbench
+module sign_extend_8bit_tb();
+    reg [7:0] A;
+    wire [8:0] B;
+
+    sign_extend_8bit tb0(
+        .A(A),
+        .B(B));
+
+    initial begin
+        A = 8'b00000000;
+        #5
+        A = 8'b00010000;
+        #5
+        A = 8'b00100000;
+        #5
+        A = 8'b00110000;
+        #5
+        A = 8'b01000000;
+        #5
+        A = 8'b01010000;
+        #5
+        A = 8'b01100000;
+        #5
+        A = 8'b01110000;
+        #5
+        A = 8'b10000000;
+        #5
+        A = 8'b10010000;
+        #5
+        A = 8'b10100000;
+        #5
+        A = 8'b10110000;
+        #5
+        A = 8'b11000000;
+        #5
+        A = 8'b11010000;
+        #5
+        A = 8'b11100000;
+        #5
+        A = 8'b11110000;
+        #5
+        $finish;
+
+    end
+endmodule
+
+
 module sub_9bit(
     input wire [8:0] A,
     input wire [8:0] B,