diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..0ec2e1b --- /dev/null +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -0,0 +1,65 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git a/lab2CA.srcs/sources_1/new/lab2testing.v b/lab2CA.srcs/sources_1/new/lab2testing.v new file mode 100644 index 0000000..9e5a151 --- /dev/null +++ b/lab2CA.srcs/sources_1/new/lab2testing.v @@ -0,0 +1,69 @@ +`timescale 1ns / 1ps + + + +module lab2testing(); + +endmodule + +module regFile(input wire clk, reset, + input wire [1:0] write_index, op0_idx, op1_idx, + input wire [8:0] write_data, + output wire [8:0] op0, op1); + + wire [8:0] r0_out, r1_out, r2_out, r3_out; + + register r0( + .clk(clk), + .reset(reset), + .En({write_index[0], write_index[1]}), + .Din(write_data), + .Dout(r0_out)); + + register r1( + .clk(clk), + .reset(reset), + .En({write_index[0], ~write_index[1]}), + .Din(write_data), + .Dout(r1_out)); + + register r2( + .clk(clk), + .reset(reset), + .En({~write_index[0], write_index[1]}), + .Din(write_data), + .Dout(r2_out)); + + register r3( + .clk(clk), + .reset(reset), + .En({~write_index[0], ~write_index[1]}), + .Din(write_data), + .Dout(r3_out)); + + Mux m0( + .A(r0_out), + .B(r1_out), + .C(r2_out), + .D(r3_out), + .switch(op0_idx)); + + Mux m1( + .A(r0_out), + .B(r1_out), + .C(r2_out), + .D(r3_out), + .switch(op1_idx)); + +endmodule + +module register(input wire clk, reset, + input wire [1:0] En, + input wire [7:0] Din, + output reg [7:0] Dout); + +endmodule + +module MUX(); + +endmodule diff --git a/lab2CA.xpr b/lab2CA.xpr new file mode 100644 index 0000000..a2e2a22 --- /dev/null +++ b/lab2CA.xpr @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + + + +