Added bank to CPU9bits
This commit is contained in:
jose.rodriguezlabra
Binary file not shown.
@@ -17,26 +17,28 @@ proc create_report { reportName command } {
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send_msg_id runtcl-5 warning "$msg"
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}
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}
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set_msg_config -id {Synth 8-256} -limit 10000
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set_msg_config -id {Synth 8-638} -limit 10000
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create_project -in_memory -part xc7k160tifbg484-2L
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set_param project.singleFileAddWarning.threshold 0
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set_param project.compositeFile.enableAutoGeneration 0
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set_param synth.vivado.isSynthRun true
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set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
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set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
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set_property webtalk.parent_dir {C:/Users/JoseIgnacio/CA Lab/lab2CA.cache/wt} [current_project]
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set_property parent.project_path {C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr} [current_project]
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set_property default_lib xil_defaultlib [current_project]
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set_property target_language Verilog [current_project]
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set_property ip_output_repo c:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
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set_property ip_output_repo {c:/Users/JoseIgnacio/CA Lab/lab2CA.cache/ip} [current_project]
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set_property ip_cache_permissions {read write} [current_project]
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read_verilog -library xil_defaultlib {
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/instructionMemory.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v}
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}
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# Mark all dcp files as not used in implementation to prevent them from being
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# stitched into the results of this synthesis run. Any black boxes in the
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@@ -2,12 +2,12 @@
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Wed Mar 20 10:53:36 2019
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# Process ID: 12136
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# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
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# Start of session at: Sun Mar 24 12:08:28 2019
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# Process ID: 6500
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# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
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# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
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# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
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# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds
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# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
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#-----------------------------------------------------------
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source CPU9bits.tcl -notrace
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Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L
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@@ -15,101 +15,96 @@ Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 8176
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INFO: Helper process launched with PID 12896
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WARNING: [Synth 8-1958] event expressions must result in a singular type [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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---------------------------------------------------------------------------------
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Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.945 ; gain = 102.359
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Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 377.188 ; gain = 114.703
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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WARNING: [Synth 8-567] referenced signal 'clk' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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WARNING: [Synth 8-567] referenced signal 'memory' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
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INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
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INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
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INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
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INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
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INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
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INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
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INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
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INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
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INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
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INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
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INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
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INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
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INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
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INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
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INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
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INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
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INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
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INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
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INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
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INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
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INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
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INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
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INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
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WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:965]
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INFO: [Synth 8-6155] done synthesizing module 'sign_extend_2bit' (25#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:965]
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WARNING: [Synth 8-689] width (3) of port connection 'A' does not match port width (2) of module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:89]
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INFO: [Synth 8-6157] synthesizing module 'sign_extend_4bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1035]
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INFO: [Synth 8-6155] done synthesizing module 'sign_extend_4bit' (26#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1035]
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WARNING: [Synth 8-689] width (5) of port connection 'A' does not match port width (4) of module 'sign_extend_4bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:93]
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INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
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INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (27#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
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WARNING: [Synth 8-689] width (3) of port connection 'A' does not match port width (2) of module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:112]
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INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (28#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
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INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
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INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
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INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
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INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
|
||||
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
|
||||
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
|
||||
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
|
||||
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
|
||||
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
|
||||
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
|
||||
WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sign_extend_5bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1090]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_5bit' (26#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1090]
|
||||
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (27#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (28#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
|
||||
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
|
||||
WARNING: [Synth 8-3331] design instructionMemory has unconnected port clk
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.844 ; gain = 158.258
|
||||
Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 414.457 ; gain = 151.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.844 ; gain = 158.258
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 414.457 ; gain = 151.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k160tifbg484-2L
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.844 ; gain = 158.258
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 414.457 ; gain = 151.973
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[15]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[14]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[13]" won't be mapped to RAM because it is too sparse
|
||||
@@ -126,27 +121,27 @@ INFO: [Synth 8-5546] ROM "memory_reg[3]" won't be mapped to RAM because it is to
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[2]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[1]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[0]" won't be mapped to RAM because it is too sparse
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[15]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[14]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[13]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[12]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[11]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[10]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[9]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[8]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[7]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[6]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[5]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[4]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[3]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[2]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[1]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[0]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[15]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[14]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[13]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[12]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[11]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[10]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[9]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[8]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[7]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[6]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[5]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[4]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[3]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[2]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[1]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[0]' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 446.785 ; gain = 189.199
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 447.438 ; gain = 184.953
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_2bit) to 'SE3'
|
||||
INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_3bit) to 'SE3'
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
@@ -161,20 +156,19 @@ Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 144
|
||||
+---Registers :
|
||||
9 Bit Registers := 5
|
||||
9 Bit Registers := 9
|
||||
+---Muxes :
|
||||
7 Input 9 Bit Muxes := 1
|
||||
2 Input 9 Bit Muxes := 22
|
||||
4 Input 9 Bit Muxes := 2
|
||||
2 Input 4 Bit Muxes := 1
|
||||
4 Input 4 Bit Muxes := 1
|
||||
15 Input 4 Bit Muxes := 1
|
||||
2 Input 9 Bit Muxes := 23
|
||||
4 Input 9 Bit Muxes := 4
|
||||
2 Input 4 Bit Muxes := 2
|
||||
4 Input 4 Bit Muxes := 2
|
||||
16 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
15 Input 3 Bit Muxes := 1
|
||||
16 Input 1 Bit Muxes := 16
|
||||
16 Input 3 Bit Muxes := 1
|
||||
16 Input 2 Bit Muxes := 1
|
||||
16 Input 1 Bit Muxes := 21
|
||||
2 Input 1 Bit Muxes := 17
|
||||
3 Input 1 Bit Muxes := 16
|
||||
15 Input 1 Bit Muxes := 5
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
@@ -182,10 +176,6 @@ Finished RTL Component Statistics
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module instructionMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
7 Input 9 Bit Muxes := 1
|
||||
Module dataMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
@@ -217,10 +207,11 @@ Detailed RTL Component Info :
|
||||
Module ControlUnit
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
15 Input 4 Bit Muxes := 1
|
||||
16 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
15 Input 3 Bit Muxes := 1
|
||||
15 Input 1 Bit Muxes := 5
|
||||
16 Input 3 Bit Muxes := 1
|
||||
16 Input 2 Bit Muxes := 1
|
||||
16 Input 1 Bit Muxes := 5
|
||||
Module bit1_mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
@@ -242,6 +233,64 @@ No constraint files found.
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-3886] merging instance 'Bank/r2/Dout_reg[5]' (FDRE) to 'Bank/r3/Dout_reg[5]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bank/r3/Dout_reg[5] )
|
||||
INFO: [Synth 8-3886] merging instance 'Bank/r2/Dout_reg[6]' (FDRE) to 'Bank/r3/Dout_reg[6]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bank/r3/Dout_reg[6] )
|
||||
INFO: [Synth 8-3886] merging instance 'Bank/r2/Dout_reg[7]' (FDRE) to 'Bank/r3/Dout_reg[7]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bank/r3/Dout_reg[7] )
|
||||
INFO: [Synth 8-3886] merging instance 'Bank/r2/Dout_reg[8]' (FDRE) to 'Bank/r3/Dout_reg[8]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bank/r3/Dout_reg[8] )
|
||||
INFO: [Synth 8-3886] merging instance 'Bank/r2/Dout_reg[3]' (FDRE) to 'Bank/r3/Dout_reg[3]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bank/r3/Dout_reg[3] )
|
||||
INFO: [Synth 8-3886] merging instance 'Bank/r2/Dout_reg[4]' (FDRE) to 'Bank/r3/Dout_reg[4]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bank/r3/Dout_reg[4] )
|
||||
INFO: [Synth 8-3886] merging instance 'Bank/r2/Dout_reg[2]' (FDRE) to 'Bank/r3/Dout_reg[2]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bank/r3/Dout_reg[2] )
|
||||
INFO: [Synth 8-3886] merging instance 'Bank/r2/Dout_reg[1]' (FDRE) to 'Bank/r3/Dout_reg[1]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bank/r3/Dout_reg[1] )
|
||||
INFO: [Synth 8-3886] merging instance 'Bank/r2/Dout_reg[0]' (FDRE) to 'Bank/r3/Dout_reg[0]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bank/r3/Dout_reg[0] )
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 666.957 ; gain = 404.473
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
ROM:
|
||||
+------------------+------------+---------------+----------------+
|
||||
|Module Name | RTL Object | Depth x Width | Implemented As |
|
||||
+------------------+------------+---------------+----------------+
|
||||
|instructionMemory | p_0_out | 32x9 | LUT |
|
||||
|CPU9bits | p_0_out | 32x9 | LUT |
|
||||
+------------------+------------+---------------+----------------+
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 666.957 ; gain = 404.473
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[8]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[7]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[6]) is unused and will be removed from module CPU9bits.
|
||||
@@ -344,32 +393,7 @@ WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][0]) is unused and w
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[5][8]) is unused and will be removed from module CPU9bits.
|
||||
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 666.957 ; gain = 404.473
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -393,7 +417,7 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 666.957 ; gain = 404.473
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -406,7 +430,7 @@ Report Check Netlist:
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 666.957 ; gain = 404.473
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -418,25 +442,25 @@ Report RTL Partitions:
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 666.957 ; gain = 404.473
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 666.957 ; gain = 404.473
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 666.957 ; gain = 404.473
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 666.957 ; gain = 404.473
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -453,42 +477,44 @@ Report Cell Usage:
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |LUT2 | 1|
|
||||
|3 |LUT3 | 2|
|
||||
|4 |LUT4 | 1|
|
||||
|5 |FDRE | 3|
|
||||
|6 |IBUF | 2|
|
||||
|7 |OBUF | 1|
|
||||
|2 |LUT1 | 1|
|
||||
|3 |LUT2 | 1|
|
||||
|4 |LUT3 | 1|
|
||||
|5 |LUT4 | 1|
|
||||
|6 |LUT5 | 2|
|
||||
|7 |FDRE | 5|
|
||||
|8 |IBUF | 2|
|
||||
|9 |OBUF | 1|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+----------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+----------+------+
|
||||
|1 |top | | 11|
|
||||
|2 | FetchU |FetchUnit | 7|
|
||||
|3 | PC |register | 7|
|
||||
|1 |top | | 15|
|
||||
|2 | FetchU |FetchUnit | 11|
|
||||
|3 | PC |register | 11|
|
||||
+------+---------+----------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 666.957 ; gain = 404.473
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 185 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 181 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 666.957 ; gain = 404.473
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 666.957 ; gain = 404.473
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.789 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 688.945 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
87 Infos, 132 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
104 Infos, 128 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 681.789 ; gain = 431.723
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.789 ; gain = 0.000
|
||||
synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 688.945 ; gain = 439.730
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 688.945 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Mar 20 10:54:03 2019...
|
||||
INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 12:09:01 2019...
|
||||
|
||||
Binary file not shown.
@@ -1,8 +1,8 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Mar 20 10:54:03 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Date : Sun Mar 24 12:09:01 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
| Design : CPU9bits
|
||||
| Device : 7k160tifbg484-2L
|
||||
@@ -30,11 +30,11 @@ Table of Contents
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 2 | 0 | 101400 | <0.01 |
|
||||
| LUT as Logic | 2 | 0 | 101400 | <0.01 |
|
||||
| Slice LUTs* | 3 | 0 | 101400 | <0.01 |
|
||||
| LUT as Logic | 3 | 0 | 101400 | <0.01 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| Slice Registers | 3 | 0 | 202800 | <0.01 |
|
||||
| Register as Flip Flop | 3 | 0 | 202800 | <0.01 |
|
||||
| Slice Registers | 5 | 0 | 202800 | <0.01 |
|
||||
| Register as Flip Flop | 5 | 0 | 202800 | <0.01 |
|
||||
| Register as Latch | 0 | 0 | 202800 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
|
||||
@@ -57,7 +57,7 @@ Table of Contents
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 3 | Yes | Reset | - |
|
||||
| 5 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@@ -151,12 +151,14 @@ Table of Contents
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 3 | Flop & Latch |
|
||||
| LUT3 | 2 | LUT |
|
||||
| FDRE | 5 | Flop & Latch |
|
||||
| LUT5 | 2 | LUT |
|
||||
| IBUF | 2 | IO |
|
||||
| OBUF | 1 | IO |
|
||||
| LUT4 | 1 | LUT |
|
||||
| LUT3 | 1 | LUT |
|
||||
| LUT2 | 1 | LUT |
|
||||
| LUT1 | 1 | LUT |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
@@ -1,9 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553093608">
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553443705">
|
||||
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="CPU9bits.vds"/>
|
||||
<File Type="RDS-UTIL" Name="CPU9bits_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="CPU9bits_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="CPU9bits.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="CPU9bits_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="CPU9bits_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
|
||||
@@ -2,11 +2,11 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Wed Mar 20 10:53:36 2019
|
||||
# Process ID: 12136
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Start of session at: Sun Mar 24 12:08:28 2019
|
||||
# Process ID: 6500
|
||||
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds
|
||||
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source CPU9bits.tcl -notrace
|
||||
|
||||
Binary file not shown.
Reference in New Issue
Block a user