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Added bank to CPU9bits

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jose.rodriguezlabra
2019-03-24 12:11:12 -04:00
parent 191ca46f2d
commit bab680ea27
59 changed files with 629 additions and 2560 deletions
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20
lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
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@@ -1,8 +1,8 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 20 10:54:03 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Date : Sun Mar 24 12:09:01 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits
| Device : 7k160tifbg484-2L
@@ -30,11 +30,11 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 2 | 0 | 101400 | <0.01 |
| LUT as Logic | 2 | 0 | 101400 | <0.01 |
| Slice LUTs* | 3 | 0 | 101400 | <0.01 |
| LUT as Logic | 3 | 0 | 101400 | <0.01 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 3 | 0 | 202800 | <0.01 |
| Register as Flip Flop | 3 | 0 | 202800 | <0.01 |
| Slice Registers | 5 | 0 | 202800 | <0.01 |
| Register as Flip Flop | 5 | 0 | 202800 | <0.01 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
@@ -57,7 +57,7 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 3 | Yes | Reset | - |
| 5 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -151,12 +151,14 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 3 | Flop & Latch |
| LUT3 | 2 | LUT |
| FDRE | 5 | Flop & Latch |
| LUT5 | 2 | LUT |
| IBUF | 2 | IO |
| OBUF | 1 | IO |
| LUT4 | 1 | LUT |
| LUT3 | 1 | LUT |
| LUT2 | 1 | LUT |
| LUT1 | 1 | LUT |
| BUFG | 1 | Clock |
+----------+------+---------------------+