William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added bank to CPU9bits

Browse Source
This commit is contained in:
jose.rodriguezlabra
2019-03-24 12:11:12 -04:00
parent 191ca46f2d
commit bab680ea27
59 changed files with 629 additions and 2560 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
lab2CA.srcs/sources_1/new/CPU9bits.v
View File

@@ -5,9 +5,10 @@ module CPU9bits(
output wire done
);
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N;
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP;
wire [2:0] FU;
wire [3:0] aluOp;
wire [1:0] bankS;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link;
instructionMemory iM(
@@ -36,6 +37,18 @@ module CPU9bits(
.op1(op1)
);
RegFile Bank(
.clk(clk),
.reset(reset),
.enable(bankS[1]),
.write_index(instr[2:1]),
.op0_idx(instr[2:1]),
.op1_idx(2'b00),//Doesn't matter
.write_data(op0),
.op0(bankOP),
.op1()
);
FetchUnit FetchU(
.clk(clk),
.reset(reset),
@@ -60,7 +73,8 @@ module CPU9bits(
.mem(loadS),
.RegEn(RegEn),
.halt(done),
.link(link)
.link(link),
.bank(bankS)
);
@@ -85,11 +99,11 @@ module CPU9bits(
.out(JBRes),
.switch(FU[2]));
sign_extend_2bit SE1(
sign_extend_3bit SE1(
.A(instr[2:0]),
.B(SE1N));
sign_extend_4bit SE2(
sign_extend_5bit SE2(
.A(instr[4:0]),
.B(SE2N));
@@ -108,7 +122,7 @@ module CPU9bits(
.Sum(AddiOut),
.Cout(cout1));
sign_extend_2bit SE3(
sign_extend_3bit SE3(
.A(instr[2:0]),
.B(SE3N));
@@ -123,13 +137,21 @@ module CPU9bits(
mux_2_1 mux4(
.A(linkData),
.B(9'b000000001), // This is DATA MEM
.out(RFIn),
.B(dataMemOut), // This is DATA MEM
.out(bankData),
.switch(loadS));
///--------------------------Bank stuff
mux_2_1 mux5(
.A(bankData),
.B(bankOP),
.out(RFIn),
.switch(bankS[0]));
///--------------------------Link Stuff
mux_2_1 mux5(
mux_2_1 mux6(
.A(loadMux),
.B(PCout),
.out(linkData),