William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added bank to CPU9bits

Browse Source
This commit is contained in:
jose.rodriguezlabra
2019-03-24 12:11:12 -04:00
parent 191ca46f2d
commit bab680ea27
59 changed files with 629 additions and 2560 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -9,7 +9,8 @@ module ControlUnit(
output reg mem,
output reg RegEn,
output reg halt,
output reg link);
output reg link,
output reg [1:0] bank);
always @(instIn, functBit)begin
case(instIn)
@@ -22,6 +23,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
else begin
aluOut <= 4'b0000; //Add
@@ -31,6 +33,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b1101: begin
aluOut <= 4'b0011; //nor
@@ -40,6 +43,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0100: begin
aluOut <= 4'b1011; //zero
@@ -49,6 +53,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b1110:
if(functBit == 1) begin
@@ -59,6 +64,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
else begin
aluOut <= 4'b0010; //or
@@ -68,6 +74,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b1111:
if(functBit == 1) begin
@@ -78,6 +85,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
else begin
aluOut <= 4'b0101; //shift left
@@ -87,6 +95,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0111: begin
aluOut <= 4'b1001; //Less than
@@ -96,15 +105,17 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0110: begin
aluOut <= 4'b0000;
addi <= 1'b1; // addi
RegEn <= 1'b1;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b1001: begin
aluOut <= 4'b0000;
@@ -114,6 +125,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0011: begin // link
halt <= 1'b0;
@@ -123,6 +135,7 @@ module ControlUnit(
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b1;
bank <= 2'b10;
end
4'b1100: begin
aluOut <= 4'b0000;
@@ -132,6 +145,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b1000: begin
aluOut <= 4'b0000;
@@ -141,6 +155,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0001: begin
aluOut <= 4'b0000;
@@ -150,6 +165,7 @@ module ControlUnit(
addi <= 1'b0;
halt <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0010: begin
aluOut <= 4'b0000;
@@ -159,8 +175,19 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0000: begin // regs should initialize at 0, so we shouldn't need to declare it everywhere
4'b1010: begin
halt <= 1'b0; // bank
RegEn <= !functBit;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= {functBit,functBit};
end
4'b0000: begin
halt <= 1'b1; // halt
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
@@ -168,6 +195,7 @@ module ControlUnit(
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
default: begin
halt <= 1'b1;
@@ -177,6 +205,7 @@ module ControlUnit(
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
endcase
end