Added bank to CPU9bits

lab2CA.srcs/sources_1/new/instructionMemory.v

@@ -25,16 +25,25 @@ module instructionMemory(
         memory[10] <= 9'b111011000; //or
         memory[11] <= 9'b111011001; //and
         memory[12] <= 9'b111111000; //sll
-        memory[13] <= 9'b111111001; //srl
+        //memory[13] <= 9'b111111001; //srl
+        //------------------------------
+        memory[13] <= 9'b010000000; //zero
+        memory[14] <= 9'b011000011; //addi
+        memory[15] <= 9'b101000000; //banks
+        memory[16] <= 9'b010000000; //zero
+        memory[17] <= 9'b101000001; //bankl
+        memory[18] <= 9'b010000000; //zero
+        memory[19] <= 9'b101000000; //banks
    //     memory[14] <= 9'b100100010; //j
-        memory[14] <= 9'b010001000; //zero
-        memory[15] <= 9'b110001101; //beq
-        memory[16] <= 9'b100001000; //jr
+        //memory[18] <= 9'b010001000; //zero
+        //memory[19] <= 9'b110001101; //beq
+        //memory[20] <= 9'b100001000; //jr
         
         
         
         
-        memory[17] <= 9'b100111100; //j
+        //memory[17] <= 9'b100111100; //j
+        memory[20] <= 9'b000000000;
         
         
     end