diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 2329f08..a37847f 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,10 +3,17 @@ +<<<<<<< HEAD
+======= + +
+ + +>>>>>>> 5458d273919a21255992a22a8e59ccb89544f780
@@ -18,6 +25,7 @@ This means code written to parse this file will need to be revisited each subseq +<<<<<<< HEAD @@ -58,6 +66,61 @@ This means code written to parse this file will need to be revisited each subseq +======= + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>>>>>>> 5458d273919a21255992a22a8e59ccb89544f780
diff --git a/lab2CA.runs/.jobs/vrs_config_1.xml b/lab2CA.runs/.jobs/vrs_config_1.xml index 99b94d7..22462ac 100644 --- a/lab2CA.runs/.jobs/vrs_config_1.xml +++ b/lab2CA.runs/.jobs/vrs_config_1.xml @@ -1,6 +1,10 @@ +<<<<<<< HEAD +======= + +>>>>>>> 5458d273919a21255992a22a8e59ccb89544f780 diff --git a/lab2CA.runs/.jobs/vrs_config_2.xml b/lab2CA.runs/.jobs/vrs_config_2.xml index ff57e1f..0f2a75f 100644 --- a/lab2CA.runs/.jobs/vrs_config_2.xml +++ b/lab2CA.runs/.jobs/vrs_config_2.xml @@ -1,6 +1,10 @@ +<<<<<<< HEAD +======= + +>>>>>>> 5458d273919a21255992a22a8e59ccb89544f780 diff --git a/lab2CA.runs/.jobs/vrs_config_3.xml b/lab2CA.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v new file mode 100644 index 0000000..9d5deb4 --- /dev/null +++ b/lab2CA.srcs/sources_1/new/ALU.v @@ -0,0 +1,64 @@ +`timescale 1ns / 1ps + +module ALU( + input wire [2:0] opcode, // NOT the same as the instruction set opcode + input wire [8:0] operand0, + input wire [8:0] operand1, + output wire [8:0] result + ); + + // Wires for connecting the modules to the mux + wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H; + + // A (000) - Add + add_9bit add0( + .A(operand0), + .B(operand1), + .Cin(1'b0), + .Sum(result_A)); + // B (001) - Subtract + sub_9bit sub0( + .A(operand0), + .B(operand1), + .C(result_B)); + // C (010) - OR + or_9bit or0( + .A(operand0), + .B(operand1), + .C(result_C)); + // D (011) - NOR + nor_9bit nor0( + .A(operand0), + .B(operand1), + .C(result_D)); + // E (100) - AND + and_9bit and0( + .A(operand0), + .B(operand1), + .Cin(1'b0), + .Sum(result_E)); + // F (101) - Shift Logical Left + shift_logical_left sll( + .A(operand0), + .B(result_F)); + // G (110) - Shift Logical Right + shift_logical_right slr( + .A(operand0), + .B(result_G)); + // H (111) + + + // MUX chooses which result to show based on the ALU's opcode + mux_8_1 mux0( + .switch(opcode), + .A(result_A), + .B(result_B), + .C(result_C), + .D(result_D), + .E(result_E), + .F(result_F), + .G(result_G), + .H(result_H), + .out(result)); + +endmodule diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index c8775bc..31550a9 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -1,26 +1,157 @@ `timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 02/15/2019 12:18:27 PM -// Design Name: -// Module Name: BasicModules -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// +module add_1bit( + input wire A, + input wire B, + input wire Cin, + output wire S, + output wire Cout); + + assign S = (A ^ B) ^ Cin; + assign Cout = ((A ^ B) & Cin) | (A & B); + +endmodule + +module add_9bit( + input wire [8:0] A, + input wire [8:0] B, + input wire Cin, + output wire [8:0] Sum, + output wire Cout); + + wire C_add0; + wire C_add1; + wire C_add2; + wire C_add3; + wire C_add4; + wire C_add5; + wire C_add6; + wire C_add7; + + add_1bit add0( + .A(A[0]), + .B(B[0]), + .Cin(Cin), + .S(Sum[0]), + .Cout(C_add0)); + + add_1bit add1( + .A(A[1]), + .B(B[1]), + .Cin(C_add0), + .S(Sum[1]), + .Cout(C_add1)); + + add_1bit add2( + .A(A[2]), + .B(B[2]), + .Cin(C_add1), + .S(Sum[2]), + .Cout(C_add2)); + + add_1bit add3( + .A(A[3]), + .B(B[3]), + .Cin(C_add2), + .S(Sum[3]), + .Cout(C_add3)); + + add_1bit add4( + .A(A[4]), + .B(B[4]), + .Cin(C_add3), + .S(Sum[4]), + .Cout(C_add4)); + + add_1bit add5( + .A(A[5]), + .B(B[5]), + .Cin(C_add4), + .S(Sum[5]), + .Cout(C_add5)); + + add_1bit add6( + .A(A[6]), + .B(B[6]), + .Cin(C_add5), + .S(Sum[6]), + .Cout(C_add6)); + + add_1bit add7( + .A(A[7]), + .B(B[7]), + .Cin(C_add6), + .S(Sum[7]), + .Cout(C_add7)); + + add_1bit add8( + .A(A[8]), + .B(B[8]), + .Cin(C_add7), + .S(Sum[8]), + .Cout(Cout)); + +endmodule + +module and_1bit( + input wire A, + input wire B, + output wire C); + + assign C = A & B; + +endmodule + +module and_9bit( + input wire [8:0] A, + input wire [8:0] B, + output wire [8:0] C); + + and_1bit and0( + .A(A[0]), + .B(B[0]), + .C(C[0])); + + and_1bit and1( + .A(A[1]), + .B(B[1]), + .C(C[1])); + + and_1bit and2( + .A(A[2]), + .B(B[2]), + .C(C[2])); + + and_1bit and3( + .A(A[3]), + .B(B[3]), + .C(C[3])); + + and_1bit and4( + .A(A[4]), + .B(B[4]), + .C(C[4])); + + and_1bit and5( + .A(A[5]), + .B(B[5]), + .C(C[5])); + + and_1bit and6( + .A(A[6]), + .B(B[6]), + .C(C[6])); + + and_1bit and7( + .A(A[7]), + .B(B[7]), + .C(C[7])); + + and_1bit and8( + .A(A[8]), + .B(B[8]), + .C(C[8])); -module BasicModules(); endmodule module gen_clock(); @@ -33,7 +164,248 @@ module gen_clock(); end endmodule +<<<<<<< HEAD //To enable register, input 00 to En, register is always outputting contents +======= +module mux_4_1(input wire [1:0] switch, + input wire [8:0] A,B,C,D, + output reg [8:0] out); + + always @(A,B,C,D,switch) begin + case (switch) + 2'b00 : out = A; + 2'b01 : out = B; + 2'b10 : out = C; + 2'b11 : out = D; + default : out = 9'bxxxxxxxxx; + endcase + end + +endmodule + +module mux_8_1( + input wire [2:0] switch, + input wire [8:0] A,B,C,D,E,F,G,H, + output reg [8:0] out); + + always @(A,B,C,D,E,F,G,H,switch) begin + case (switch) + 3'b000 : out = A; + 3'b001 : out = B; + 3'b010 : out = C; + 3'b011 : out = D; + 3'b100 : out = E; + 3'b101 : out = F; + 3'b110 : out = G; + 3'b111 : out = H; + default : out = 9'bxxxxxxxxx; + endcase + end + +endmodule + +module mux_16_1( + input wire [3:0] switch, + input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P, + output reg [8:0] out); + + always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin + case (switch) + 4'b0000 : out = A; + 4'b0001 : out = B; + 4'b0010 : out = C; + 4'b0011 : out = D; + 4'b0100 : out = E; + 4'b0101 : out = F; + 4'b0110 : out = G; + 4'b0111 : out = H; + 4'b1000 : out = I; + 4'b1001 : out = J; + 4'b1010 : out = K; + 4'b1011 : out = L; + 4'b1100 : out = M; + 4'b1101 : out = N; + 4'b1110 : out = O; + 4'b1111 : out = P; + default : out = 9'bxxxxxxxxx; + endcase + end + +endmodule + +module nor_1bit( + input wire A, + input wire B, + output wire C); + + assign C = A |~ B; + +endmodule + +module nor_9bit( + input wire [8:0] A, + input wire [8:0] B, + output wire [8:0] C); + + nor_1bit nor0( + .A(A[0]), + .B(B[0]), + .C(C[0])); + + nor_1bit nor1( + .A(A[1]), + .B(B[1]), + .C(C[1])); + + nor_1bit nor2( + .A(A[2]), + .B(B[2]), + .C(C[2])); + + nor_1bit nor3( + .A(A[3]), + .B(B[3]), + .C(C[3])); + + nor_1bit nor4( + .A(A[4]), + .B(B[4]), + .C(C[4])); + + nor_1bit nor5( + .A(A[5]), + .B(B[5]), + .C(C[5])); + + nor_1bit nor6( + .A(A[6]), + .B(B[6]), + .C(C[6])); + + nor_1bit nor7( + .A(A[7]), + .B(B[7]), + .C(C[7])); + + nor_1bit nor8( + .A(A[8]), + .B(B[8]), + .C(C[8])); + +endmodule + +module not_1bit( + input wire A, + output wire B); + + assign B = ~A; + +endmodule + +module not_9bit( + input wire [8:0] A, + output wire [8:0] B); + + not_1bit not0( + .A(A[0]), + .B(B[0])); + + not_1bit not1( + .A(A[1]), + .B(B[1])); + + not_1bit not2( + .A(A[2]), + .B(B[2])); + + not_1bit not3( + .A(A[3]), + .B(B[3])); + + not_1bit not4( + .A(A[4]), + .B(B[4])); + + not_1bit not5( + .A(A[5]), + .B(B[5])); + + not_1bit not6( + .A(A[6]), + .B(B[6])); + + not_1bit not7( + .A(A[7]), + .B(B[7])); + + not_1bit not8( + .A(A[8]), + .B(B[8])); + +endmodule + +module or_1bit( + input wire A, + input wire B, + output wire C); + + assign C = A | B; + +endmodule + +module or_9bit( + input wire [8:0] A, + input wire [8:0] B, + output wire [8:0] C); + + or_1bit or0( + .A(A[0]), + .B(B[0]), + .C(C[0])); + + or_1bit or1( + .A(A[1]), + .B(B[1]), + .C(C[1])); + + or_1bit or2( + .A(A[2]), + .B(B[2]), + .C(C[2])); + + or_1bit or3( + .A(A[3]), + .B(B[3]), + .C(C[3])); + + or_1bit or4( + .A(A[4]), + .B(B[4]), + .C(C[4])); + + or_1bit or5( + .A(A[5]), + .B(B[5]), + .C(C[5])); + + or_1bit or6( + .A(A[6]), + .B(B[6]), + .C(C[6])); + + or_1bit or7( + .A(A[7]), + .B(B[7]), + .C(C[7])); + + or_1bit or8( + .A(A[8]), + .B(B[8]), + .C(C[8])); + +endmodule + +>>>>>>> 5458d273919a21255992a22a8e59ccb89544f780 module register(input wire clk, reset, input wire [1:0] En, input wire [8:0] Din, @@ -53,6 +425,7 @@ module register(input wire clk, reset, endmodule +<<<<<<< HEAD //Mux follows intuitive switching module mux(input wire [1:0] switch, input wire [8:0] A,B,C,D, @@ -75,6 +448,57 @@ module mux(input wire [1:0] switch, out = "ZZZZZZZZZ"; end end +======= +module shift_logical_left( + input wire [8:0] A, + output wire [8:0] B); + + assign B = {A[7:0],A[8]}; +>>>>>>> 5458d273919a21255992a22a8e59ccb89544f780 endmodule +module shift_logical_right( + input wire [8:0] A, + output wire [8:0] B); + + assign B = {A[0],A[8:1]}; + +endmodule + +module sub_9bit( + input wire [8:0] A, + input wire [8:0] B, + output wire [8:0] C); + + wire [8:0] D; + + twos_compliment_9bit two_comp0( + .A(B), + .C(D)); + + add_9bit add0( + .A(A), + .B(D), + .Cin(1'b0), + .Sum(C)); + +endmodule + +module twos_compliment_9bit( + input wire [8:0] A, + output wire [8:0] B); + + wire [8:0] C; + + not_9bit not0( + .A(A), + .B(C)); + + add_9bit add0( + .A(C), + .B(9'b000000000), + .Cin(1'b1), + .Sum(B)); + +endmodule \ No newline at end of file diff --git a/lab2CA.srcs/sources_1/new/RegFile.v b/lab2CA.srcs/sources_1/new/RegFile.v index b1c1386..3721957 100644 --- a/lab2CA.srcs/sources_1/new/RegFile.v +++ b/lab2CA.srcs/sources_1/new/RegFile.v @@ -1,24 +1,4 @@ `timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 02/15/2019 12:21:16 PM -// Design Name: -// Module Name: RegFile -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - module RegFile(input wire clk, reset, input wire [1:0] write_index, op0_idx, op1_idx, @@ -57,18 +37,20 @@ module RegFile(input wire clk, reset, .Din(write_data), .Dout(r3_out)); - mux m0( + mux_4_1 m0( .A(r0_out), .B(r1_out), .C(r2_out), .D(r3_out), + .out(op0), .switch(op0_idx)); - mux m1( + mux_4_1 m1( .A(r0_out), .B(r1_out), .C(r2_out), .D(r3_out), + .out(op1), .switch(op1_idx)); endmodule diff --git a/lab2CA.xpr b/lab2CA.xpr index 6c8cb34..aa81c74 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - +