From 337bf5cf13a14300fdea7145afcef31fd503544b Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 14:34:59 -0500 Subject: [PATCH 01/26] Removed comment blocks --- lab2CA.srcs/sources_1/new/BasicModules.v | 20 -------------------- lab2CA.srcs/sources_1/new/RegFile.v | 20 -------------------- 2 files changed, 40 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index dab1d73..808c0ab 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -1,24 +1,4 @@ `timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 02/15/2019 12:18:27 PM -// Design Name: -// Module Name: BasicModules -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - module BasicModules(); endmodule diff --git a/lab2CA.srcs/sources_1/new/RegFile.v b/lab2CA.srcs/sources_1/new/RegFile.v index b1c1386..903c32c 100644 --- a/lab2CA.srcs/sources_1/new/RegFile.v +++ b/lab2CA.srcs/sources_1/new/RegFile.v @@ -1,24 +1,4 @@ `timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 02/15/2019 12:21:16 PM -// Design Name: -// Module Name: RegFile -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - module RegFile(input wire clk, reset, input wire [1:0] write_index, op0_idx, op1_idx, From cdb52f35bd6d8d76f96d01ac5acbce74cb93556c Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 14:46:08 -0500 Subject: [PATCH 02/26] Converted MUX to use case statement --- lab2CA.srcs/sources_1/new/BasicModules.v | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index 808c0ab..b0b58d7 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -41,19 +41,12 @@ module mux(input wire [1:0] switch, output reg [8:0] out); always @(A,B,C,D,switch) begin - if (switch == 2'b00) begin - out = A; - end - else if (switch == 2'b01) begin - out = B; - end - else if (switch == 2'b11) begin - out = C; - end - else begin - out = D; - end + case (switch) + 2'b00 : out = A; + 2'b01 : out = B; + 2'b10 : out = C; + default: out = D; + endcase end - endmodule From 4421b1a9d6955817425be699f92554df5840effc Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 14:48:57 -0500 Subject: [PATCH 03/26] Reordered into alphabetical order --- lab2CA.srcs/sources_1/new/BasicModules.v | 34 +++++++++++------------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index b0b58d7..dab2489 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -1,8 +1,5 @@ `timescale 1ns / 1ps -module BasicModules(); -endmodule - module gen_clock(); reg clk; @@ -17,6 +14,20 @@ module gen_clock(); endmodule +module mux(input wire [1:0] switch, + input wire [8:0] A,B,C,D, + output reg [8:0] out); + + always @(A,B,C,D,switch) begin + case (switch) + 2'b00 : out = A; + 2'b01 : out = B; + 2'b10 : out = C; + default: out = D; + endcase + end +endmodule + module register(input wire clk, reset, input wire [1:0] En, input wire [8:0] Din, @@ -34,19 +45,4 @@ module register(input wire clk, reset, end end -endmodule - -module mux(input wire [1:0] switch, - input wire [8:0] A,B,C,D, - output reg [8:0] out); - - always @(A,B,C,D,switch) begin - case (switch) - 2'b00 : out = A; - 2'b01 : out = B; - 2'b10 : out = C; - default: out = D; - endcase - end -endmodule - +endmodule \ No newline at end of file From 8d78924c047f34d2852918bca1fd2f4bf53d8f1a Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 14:50:42 -0500 Subject: [PATCH 04/26] Added inverter --- lab2CA.srcs/sources_1/new/BasicModules.v | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index dab2489..bccd814 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -14,6 +14,13 @@ module gen_clock(); endmodule +module inverter( + input wire A, + output wire B); + + assign B = ~A; +endmodule + module mux(input wire [1:0] switch, input wire [8:0] A,B,C,D, output reg [8:0] out); From 3d8ae740f035629b3b1ead78c45438805a02e80a Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 14:55:11 -0500 Subject: [PATCH 05/26] Added 1-bit adder --- lab2CA.cache/wt/webtalk_pa.xml | 90 +++--------------------- lab2CA.srcs/sources_1/new/BasicModules.v | 14 ++++ 2 files changed, 23 insertions(+), 81 deletions(-) diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index ef11cd9..d858caf 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,13 +3,9 @@ -<<<<<<< Updated upstream - -======= - ->>>>>>> Stashed changes +
- +
@@ -21,87 +17,19 @@ This means code written to parse this file will need to be revisited each subseq -<<<<<<< Updated upstream - - - - -======= - - - ->>>>>>> Stashed changes - - + + -<<<<<<< Updated upstream - - -======= - - - - ->>>>>>> Stashed changes - - - - -<<<<<<< Updated upstream - - - -======= - - ->>>>>>> Stashed changes - - - - - - - - - - - - -<<<<<<< Updated upstream - -======= - - ->>>>>>> Stashed changes - + + + - - - - - - - -<<<<<<< Updated upstream - - - - + - -======= - - - - - - - - ->>>>>>> Stashed changes +
diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index bccd814..a433e4b 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -1,5 +1,17 @@ `timescale 1ns / 1ps +module adder_1bit( + input wire A, + input wire B, + input wire Cin, + output wire S, + output wire Cout); + + assign S = (A ^ B) ^ Cin; + assign Cout = ((A ^ B) & Cin) | (A & B); + +endmodule + module gen_clock(); reg clk; @@ -19,6 +31,7 @@ module inverter( output wire B); assign B = ~A; + endmodule module mux(input wire [1:0] switch, @@ -33,6 +46,7 @@ module mux(input wire [1:0] switch, default: out = D; endcase end + endmodule module register(input wire clk, reset, From 9eec4cdc761104372d1c511ed8358c1975951d35 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 14:56:34 -0500 Subject: [PATCH 06/26] Renamed mux in case we need different kinds later on --- lab2CA.srcs/sources_1/new/BasicModules.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index a433e4b..135d394 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -34,7 +34,7 @@ module inverter( endmodule -module mux(input wire [1:0] switch, +module mux_4_1(input wire [1:0] switch, input wire [8:0] A,B,C,D, output reg [8:0] out); From 81cdf3c62b731805ffde0276656ac524d05ea1f2 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 14:59:38 -0500 Subject: [PATCH 07/26] Added AND gate module --- lab2CA.srcs/sources_1/new/BasicModules.v | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index 135d394..a4bed4b 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -12,6 +12,15 @@ module adder_1bit( endmodule +module and_gate( + input wire A, + input wire B, + output wire C); + + assign C = A & B; + +endmodule + module gen_clock(); reg clk; From 2a84458894cf530bf3e7f064ab7cff486a2f516b Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 15:07:25 -0500 Subject: [PATCH 08/26] Added 9-bit adder --- lab2CA.srcs/sources_1/new/BasicModules.v | 81 ++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index a4bed4b..4997250 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -12,6 +12,87 @@ module adder_1bit( endmodule +module adder_9bit( + input wire [8:0] A, + input wire [8:0] B, + input wire Cin, + output wire [8:0] Sum, + output wire Cout); + + wire C_add0; + wire C_add1; + wire C_add2; + wire C_add3; + wire C_add4; + wire C_add5; + wire C_add6; + wire C_add7; + + adder_1bit add0( + .A(A[0]) + .B(B[0]) + .Cin(Cin) + .S(Sum[0]) + .Cout(C_add0)); + + adder_1bit add1( + .A(A[0]) + .B(B[0]) + .Cin(C_add0) + .S(Sum[0]) + .Cout(C_add1)); + + adder_1bit add2( + .A(A[0]) + .B(B[0]) + .Cin(C_add1) + .S(Sum[0]) + .Cout(C_add2)); + + adder_1bit add3( + .A(A[0]) + .B(B[0]) + .Cin(C_add2) + .S(Sum[0]) + .Cout(C_add3)); + + adder_1bit add4( + .A(A[0]) + .B(B[0]) + .Cin(C_add3) + .S(Sum[0]) + .Cout(C_add4)); + + adder_1bit add5( + .A(A[0]) + .B(B[0]) + .Cin(C_add4) + .S(Sum[0]) + .Cout(C_add5)); + + adder_1bit add6( + .A(A[0]) + .B(B[0]) + .Cin(C_add5) + .S(Sum[0]) + .Cout(C_add6)); + + adder_1bit add7( + .A(A[0]) + .B(B[0]) + .Cin(C_add6) + .S(Sum[0]) + .Cout(C_add7)); + + adder_1bit add8( + .A(A[0]) + .B(B[0]) + .Cin(C_add7) + .S(Sum[0]) + .Cout(Cout)); + +endmodule + module and_gate( input wire A, input wire B, From 8b37bee0879c075a915d89394a9ef94c540e231b Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 15:13:40 -0500 Subject: [PATCH 09/26] Added 9-bit AND module --- lab2CA.srcs/sources_1/new/BasicModules.v | 54 +++++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index 4997250..30f1c9d 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -93,7 +93,7 @@ module adder_9bit( endmodule -module and_gate( +module and_1bit( input wire A, input wire B, output wire C); @@ -102,6 +102,58 @@ module and_gate( endmodule +module and_9bit( + input wire [8:0] A, + input wire [8:0] B, + output wire [8:0] C); + + and_1bit and0( + .A(A[0]) + .B(B[0]) + .C(C[0])); + + and_1bit and1( + .A(A[1]) + .B(B[1]) + .C(C[1])); + + and_1bit and2( + .A(A[2]) + .B(B[2]) + .C(C[2])); + + and_1bit and3( + .A(A[3]) + .B(B[3]) + .C(C[3])); + + and_1bit and4( + .A(A[4]) + .B(B[4]) + .C(C[4])); + + and_1bit and5( + .A(A[5]) + .B(B[5]) + .C(C[5])); + + and_1bit and6( + .A(A[6]) + .B(B[6]) + .C(C[6])); + + and_1bit and7( + .A(A[7]) + .B(B[7]) + .C(C[7])); + + and_1bit and8( + .A(A[8]) + .B(B[8]) + .C(C[8])); + +endmodule + module gen_clock(); reg clk; From cadbc4dd2575532c1c5bda66ffd1d48bea1e93d9 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 15:20:12 -0500 Subject: [PATCH 10/26] Added 9-bit NOT --- lab2CA.srcs/sources_1/new/BasicModules.v | 58 ++++++++++++++++++++---- 1 file changed, 50 insertions(+), 8 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index 30f1c9d..04c2750 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -168,14 +168,6 @@ module gen_clock(); endmodule -module inverter( - input wire A, - output wire B); - - assign B = ~A; - -endmodule - module mux_4_1(input wire [1:0] switch, input wire [8:0] A,B,C,D, output reg [8:0] out); @@ -191,6 +183,56 @@ module mux_4_1(input wire [1:0] switch, endmodule +module not_1bit( + input wire A, + output wire B); + + assign B = ~A; + +endmodule + +module not_9bit( + input wire [8:0] A, + output wire [8:0] B); + + not_1bit not0( + .A(A[0]) + .B(B[0])); + + not_1bit not1( + .A(A[1]) + .B(B[1])); + + not_1bit not2( + .A(A[2]) + .B(B[2])); + + not_1bit not3( + .A(A[3]) + .B(B[3])); + + not_1bit not4( + .A(A[4]) + .B(B[4])); + + not_1bit not5( + .A(A[5]) + .B(B[5])); + + not_1bit not6( + .A(A[6]) + .B(B[6])); + + not_1bit not7( + .A(A[7]) + .B(B[7])); + + not_1bit not8( + .A(A[8]) + .B(B[8])); + +endmodule + module register(input wire clk, reset, input wire [1:0] En, input wire [8:0] Din, From fd22d5c7e6d8536ccb1728953a7c585618032f78 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 15:33:02 -0500 Subject: [PATCH 11/26] Added 16:1 MUX for our ALU --- lab2CA.srcs/sources_1/new/BasicModules.v | 32 +++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index 04c2750..a8a98d4 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -177,7 +177,37 @@ module mux_4_1(input wire [1:0] switch, 2'b00 : out = A; 2'b01 : out = B; 2'b10 : out = C; - default: out = D; + 2'b11 : out = D; + default : out = 9'bxxxxxxxxx; + endcase + end + +endmodule + +module mux_16_1( + input wire [3:0] switch, + input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P, + output reg [8:0] out); + + always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin + case (switch) + 4'b0000 : out = A; + 4'b0001 : out = B; + 4'b0010 : out = C; + 4'b0011 : out = D; + 4'b0100 : out = E; + 4'b0101 : out = F; + 4'b0110 : out = G; + 4'b0111 : out = H; + 4'b1000 : out = I; + 4'b1001 : out = J; + 4'b1010 : out = K; + 4'b1011 : out = L; + 4'b1100 : out = M; + 4'b1101 : out = N; + 4'b1110 : out = O; + 4'b1111 : out = P; + default : out = 9'bxxxxxxxxx; endcase end From 9628b971d70efdf1fc007aa5cd347bc6089c5f1a Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 15:40:20 -0500 Subject: [PATCH 12/26] Fixed a few syntax errors --- lab2CA.srcs/sources_1/new/BasicModules.v | 126 +++++++++++------------ 1 file changed, 63 insertions(+), 63 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index a8a98d4..f4a97c4 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -29,66 +29,66 @@ module adder_9bit( wire C_add7; adder_1bit add0( - .A(A[0]) - .B(B[0]) - .Cin(Cin) - .S(Sum[0]) + .A(A[0]), + .B(B[0]), + .Cin(Cin), + .S(Sum[0]), .Cout(C_add0)); adder_1bit add1( - .A(A[0]) - .B(B[0]) - .Cin(C_add0) - .S(Sum[0]) + .A(A[1]), + .B(B[1]), + .Cin(C_add0), + .S(Sum[1]), .Cout(C_add1)); adder_1bit add2( - .A(A[0]) - .B(B[0]) - .Cin(C_add1) - .S(Sum[0]) + .A(A[2]), + .B(B[2]), + .Cin(C_add1), + .S(Sum[2]), .Cout(C_add2)); adder_1bit add3( - .A(A[0]) - .B(B[0]) - .Cin(C_add2) - .S(Sum[0]) + .A(A[3]), + .B(B[3]), + .Cin(C_add2), + .S(Sum[3]), .Cout(C_add3)); adder_1bit add4( - .A(A[0]) - .B(B[0]) - .Cin(C_add3) - .S(Sum[0]) + .A(A[4]), + .B(B[4]), + .Cin(C_add3), + .S(Sum[4]), .Cout(C_add4)); adder_1bit add5( - .A(A[0]) - .B(B[0]) - .Cin(C_add4) - .S(Sum[0]) + .A(A[5]), + .B(B[5]), + .Cin(C_add4), + .S(Sum[5]), .Cout(C_add5)); adder_1bit add6( - .A(A[0]) - .B(B[0]) - .Cin(C_add5) - .S(Sum[0]) + .A(A[6]), + .B(B[6]), + .Cin(C_add5), + .S(Sum[6]), .Cout(C_add6)); adder_1bit add7( - .A(A[0]) - .B(B[0]) - .Cin(C_add6) - .S(Sum[0]) + .A(A[7]), + .B(B[7]), + .Cin(C_add6), + .S(Sum[7]), .Cout(C_add7)); adder_1bit add8( - .A(A[0]) - .B(B[0]) - .Cin(C_add7) - .S(Sum[0]) + .A(A[8]), + .B(B[8]), + .Cin(C_add7), + .S(Sum[8]), .Cout(Cout)); endmodule @@ -108,48 +108,48 @@ module and_9bit( output wire [8:0] C); and_1bit and0( - .A(A[0]) - .B(B[0]) + .A(A[0]), + .B(B[0]), .C(C[0])); and_1bit and1( - .A(A[1]) - .B(B[1]) + .A(A[1]), + .B(B[1]), .C(C[1])); and_1bit and2( - .A(A[2]) - .B(B[2]) + .A(A[2]), + .B(B[2]), .C(C[2])); and_1bit and3( - .A(A[3]) - .B(B[3]) + .A(A[3]), + .B(B[3]), .C(C[3])); and_1bit and4( - .A(A[4]) - .B(B[4]) + .A(A[4]), + .B(B[4]), .C(C[4])); and_1bit and5( - .A(A[5]) - .B(B[5]) + .A(A[5]), + .B(B[5]), .C(C[5])); and_1bit and6( - .A(A[6]) - .B(B[6]) + .A(A[6]), + .B(B[6]), .C(C[6])); and_1bit and7( - .A(A[7]) - .B(B[7]) + .A(A[7]), + .B(B[7]), .C(C[7])); and_1bit and8( - .A(A[8]) - .B(B[8]) + .A(A[8]), + .B(B[8]), .C(C[8])); endmodule @@ -226,39 +226,39 @@ module not_9bit( output wire [8:0] B); not_1bit not0( - .A(A[0]) + .A(A[0]), .B(B[0])); not_1bit not1( - .A(A[1]) + .A(A[1]), .B(B[1])); not_1bit not2( - .A(A[2]) + .A(A[2]), .B(B[2])); not_1bit not3( - .A(A[3]) + .A(A[3]), .B(B[3])); not_1bit not4( - .A(A[4]) + .A(A[4]), .B(B[4])); not_1bit not5( - .A(A[5]) + .A(A[5]), .B(B[5])); not_1bit not6( - .A(A[6]) + .A(A[6]), .B(B[6])); not_1bit not7( - .A(A[7]) + .A(A[7]), .B(B[7])); not_1bit not8( - .A(A[8]) + .A(A[8]), .B(B[8])); endmodule From 68bb7a87e8ee6f1e536286ca12afa72e35c72420 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 15:57:04 -0500 Subject: [PATCH 13/26] Framework of ALU is pretty much done --- lab2CA.srcs/sim_1/new/ALU.v | 40 +++++++++++++++++++++++++++++++++++++ lab2CA.xpr | 10 +++++++++- 2 files changed, 49 insertions(+), 1 deletion(-) create mode 100644 lab2CA.srcs/sim_1/new/ALU.v diff --git a/lab2CA.srcs/sim_1/new/ALU.v b/lab2CA.srcs/sim_1/new/ALU.v new file mode 100644 index 0000000..95e2828 --- /dev/null +++ b/lab2CA.srcs/sim_1/new/ALU.v @@ -0,0 +1,40 @@ +`timescale 1ns / 1ps + +module ALU( + input wire [8:0] instruction, + output wire [8:0] result + ); + + // Wires for connecting the modules to the mux + wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P; + + // Please place modules in order of OPCODE, to make them easier to find + + + + + + + + // MUX chooses which result to show based on the OPCODE + mux_16_1 mux_result( + .switch(instruction[8:5]), + .A(A), + .B(B), + .C(C), + .D(D), + .E(E), + .F(F), + .G(G), + .H(H), + .I(I), + .J(J), + .K(K), + .L(L), + .M(M), + .N(N), + .O(O), + .P(P), + .out(result)); + +endmodule diff --git a/lab2CA.xpr b/lab2CA.xpr index c1369d1..917a245 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - +