Added forwarding

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -6,13 +6,16 @@ module CPU9bits(
     output wire done
         );
     
-    wire [8:0] RFIn,FUAddr;
-    wire [1:0] instr;
-    wire fetchBranch, RegEn;
-    wire [50:0] FDOut, FDPipOut;
+    wire [8:0] RFIn,FUAddr, op0_ext, op1_ext, wr_ext, op0_sub, op1_sub, op0_zero, op1_zero, op0_and, op1_and, newOp0, newOp1;
+    wire [1:0] instr, op0_idx, op1_idx;
+    wire fetchBranch, RegEn, compare0, compare1;
+    wire [50:0] FDOut, FDPipOut, EMIn;
     wire [61:0] EMOut, EMPipOut;
     
+    
     assign result = RFIn;
+    assign EMIn = {FDPipOut[50:42], newOp0, newOp1, FDPipOut[23:0]};
+
     
     FDModule FD(
         .reset(reset),
@@ -23,7 +26,11 @@ module CPU9bits(
         .AddrIn(FUAddr), 
         .RFIdx(instr),
         .result(FDOut),
-        .done(done)
+        .done(done),
+        .compare0(compare0),
+        .compare1(compare1),
+        .op0_idx(op0_idx),
+        .op1_idx(op1_idx)
      );
      
      fDPipReg pipe1(
@@ -37,7 +44,7 @@ module CPU9bits(
      EMModule EM(
         .reset(reset),
         .clk(clk),
-        .PipIn(FDPipOut),
+        .PipIn(EMIn),
         .PipOut(EMOut)
      );
     
@@ -57,6 +64,70 @@ module CPU9bits(
         .fetchBranch(fetchBranch), 
         .RegEn(RegEn)
      );
+     
+     sign_extend_2bit ext0(
+     .A(op0_idx),
+     .B(op0_ext)
+     );
+     
+     sign_extend_2bit ext1(
+     .A(op1_idx),
+     .B(op1_ext)
+     );
+     
+     sign_extend_2bit ext2(
+     .A(instr),
+     .B(wr_ext)
+     );
+     
+     sub_9bit sub0(
+     .A(op0_ext),
+     .B(wr_ext),
+     .C(op0_sub)
+     );
+     
+     sub_9bit sub1(
+     .A(op1_ext),
+     .B(wr_ext),
+     .C(op1_sub)
+     );
+     
+     BEQ beq0(
+     .A(op0_sub),
+     .B(op0_zero)
+     );
+     
+     BEQ beq1(
+     .A(op1_sub),
+     .B(op1_zero)
+     );
+     
+     and_9bit and0(
+     .A(~op0_zero),
+     .B({8'b00000000,compare0}),
+     .C(op0_and)
+     );
+     
+     and_9bit and1(
+     .A(~op1_zero),
+     .B({8'b00000000,compare1}),
+     .C(op1_and)
+     );
+     
+     mux_2_1 mux0(
+     .switch(op0_and[0]),
+     .A(FDOut[41:33]),
+     .B(EMPipOut[33:25]), //ALUOut
+     .out(newOp0)
+     );
+     
+     mux_2_1 mux1(
+     .switch(op1_and[0]),
+     .A(FDOut[32:24]),
+     .B(EMPipOut[33:25]), //ALUOut
+     .out(newOp1)
+     );
+     
 
 endmodule