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This commit is contained in:
Johannes
2019-04-11 18:36:00 -04:00
parent 42d2bf2d80
commit bc9c02322c
12 changed files with 367 additions and 277 deletions
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49
lab2CA.srcs/sources_1/new/ControlUnit.v
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@@ -6,15 +6,24 @@ module ControlUnit(
output reg [3:0] aluOut,
output reg [2:0] FU,
output reg [1:0] bank,
<<<<<<< Updated upstream
output reg addi, mem, dataMemEn, RegEn, halt, link, js
);
=======
output reg addi, mem, dataMemEn, RegEn, halt, link, js, compare0, compare1
);
>>>>>>> Stashed changes
always @(instIn, functBit)
begin
case(instIn)
4'b0000: // Halt/NOP
begin
<<<<<<< Updated upstream
halt <= functBit;
=======
halt <= ~functBit;
>>>>>>> Stashed changes
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
@@ -24,6 +33,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b0;
compare1 <= 1'b0;
end
4'b0001: // Load Byte
begin
@@ -37,6 +48,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
4'b0010: // Store Byte
begin
@@ -50,6 +63,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
4'b0011: // Link
begin
@@ -63,6 +78,8 @@ module ControlUnit(
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b0;
compare1 <= 1'b0;
end
4'b0100: // Zero
begin
@@ -76,6 +93,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b0;
compare1 <= 1'b0;
end
4'b0101: // Add/Subtract
if(functBit == 1) // Subtract
@@ -90,6 +109,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
else // Add
begin
@@ -103,6 +124,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
4'b0110: // Add Immediate
begin
@@ -116,6 +139,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b0;
end
4'b0111: // Set if Less Than
begin
@@ -129,6 +154,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
4'b1000: // Jump to Register
begin
@@ -142,6 +169,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b0;
end
4'b1001: // Jump Forward
begin
@@ -155,6 +184,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b0;
compare1 <= 1'b0;
end
4'b1010: // Bank Load/Bank Store
begin
@@ -168,6 +199,8 @@ module ControlUnit(
link <= 1'b0;
bank <= {functBit,functBit};
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b0;
end
4'b1011: // Jump Backward
begin
@@ -181,6 +214,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
compare0 <= 1'b0;
compare1 <= 1'b0;
end
4'b1100: // Branch if Zero
begin
@@ -194,6 +229,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b0;
end
4'b1101: // NOR
begin
@@ -207,6 +244,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
4'b1110: // OR/AND
if(functBit == 1) // AND
@@ -221,6 +260,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
else // OR
begin
@@ -234,6 +275,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
4'b1111: // Shift Right Logical/Shift Left Logical
if(functBit == 1) // Shift Right Logical
@@ -248,6 +291,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
else // Shift Left Logical
begin
@@ -261,6 +306,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
default:
begin
@@ -274,6 +321,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b0;
compare1 <= 1'b0;
end
endcase
end