From c047c801aaa02248a5df457daf8ad38097de0911 Mon Sep 17 00:00:00 2001 From: goochey Date: Wed, 27 Feb 2019 12:06:17 -0500 Subject: [PATCH] Lots of changes Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay. --- lab2CA.runs/impl_1/gen_run.xml | 28 ++++- lab2CA.runs/synth_1/gen_run.xml | 2 + lab2CA.sim/sim_1/behav/xsim/decoder_tb.tcl | 11 ++ .../sim_1/behav/xsim/decoder_tb_vlog.prj | 9 ++ lab2CA.sim/sim_1/behav/xsim/webtalk.jou | 14 +-- ...820.backup.jou => webtalk_1408.backup.jou} | 4 +- ...68.backup.jou => webtalk_14864.backup.jou} | 8 +- ...844.backup.jou => webtalk_7276.backup.jou} | 8 +- lab2CA.sim/sim_1/behav/xsim/xelab.pb | Bin 3085 -> 2110 bytes .../decoder_tb_behav/Compile_Options.txt | 1 + .../decoder_tb_behav/TempBreakPointFile.txt | 1 + .../xsim.dir/decoder_tb_behav/obj/xsim_1.c | 108 ++++++++++++++++++ .../webtalk/usage_statistics_ext_xsim.xml | 44 +++++++ .../decoder_tb_behav/webtalk/xsim_webtalk.tcl | 32 ++++++ .../xsim/xsim.dir/decoder_tb_behav/xsim.mem | Bin 0 -> 2961 bytes .../xsim.dir/regFile_tb_behav/obj/xsim_1.c | 21 ++-- .../webtalk/usage_statistics_ext_xsim.xml | 10 +- .../regFile_tb_behav/webtalk/xsim_webtalk.tcl | 28 ++--- .../xsim/xsim.dir/regFile_tb_behav/xsim.mem | Bin 4317 -> 4396 bytes lab2CA.sim/sim_1/behav/xsim/xvlog.pb | Bin 3240 -> 4365 bytes lab2CA.srcs/sources_1/new/BasicModules.v | 52 ++++++++- lab2CA.srcs/sources_1/new/FetchUnit.v | 4 +- lab2CA.srcs/sources_1/new/RegFile.v | 21 +++- lab2CA.xpr | 12 +- regFile_tb_behav.wcfg | 79 +++++++++++++ 25 files changed, 428 insertions(+), 69 deletions(-) create mode 100644 lab2CA.sim/sim_1/behav/xsim/decoder_tb.tcl create mode 100644 lab2CA.sim/sim_1/behav/xsim/decoder_tb_vlog.prj rename lab2CA.sim/sim_1/behav/xsim/{webtalk_11820.backup.jou => webtalk_1408.backup.jou} (91%) rename lab2CA.sim/sim_1/behav/xsim/{webtalk_11568.backup.jou => webtalk_14864.backup.jou} (73%) rename lab2CA.sim/sim_1/behav/xsim/{webtalk_11844.backup.jou => webtalk_7276.backup.jou} (73%) create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/Compile_Options.txt create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/TempBreakPointFile.txt create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/obj/xsim_1.c create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/xsim.mem create mode 100644 regFile_tb_behav.wcfg diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml index f159db5..faca896 100644 --- a/lab2CA.runs/impl_1/gen_run.xml +++ b/lab2CA.runs/impl_1/gen_run.xml @@ -1,14 +1,16 @@ - - + + + + + - @@ -16,8 +18,11 @@ + + + @@ -26,8 +31,25 @@ + + + + + + + + + + + + + + + + + diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml index afce82b..60496de 100644 --- a/lab2CA.runs/synth_1/gen_run.xml +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -4,6 +4,8 @@ + + diff --git a/lab2CA.sim/sim_1/behav/xsim/decoder_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/decoder_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/decoder_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/decoder_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/decoder_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/decoder_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou index c29e915..dcabd11 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Thu Feb 21 15:07:17 2019 -# Process ID: 4960 -# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +# Start of session at: Wed Feb 27 11:47:34 2019 +# Process ID: 6784 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/REPOSITORIES/Educational/Western -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11820.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_1408.backup.jou similarity index 91% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_11820.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_1408.backup.jou index 783e38b..29a40e1 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_11820.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_1408.backup.jou @@ -2,8 +2,8 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 17:37:48 2019 -# Process ID: 11820 +# Start of session at: Wed Feb 27 11:43:09 2019 +# Process ID: 1408 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim # Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11568.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_14864.backup.jou similarity index 73% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_11568.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_14864.backup.jou index 9130792..6e967bd 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_11568.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_14864.backup.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 20 10:48:52 2019 -# Process ID: 11568 +# Start of session at: Wed Feb 27 11:39:16 2019 +# Process ID: 14864 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11844.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou similarity index 73% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_11844.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou index bd6c6c5..bbb2a8d 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_11844.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 20 10:53:42 2019 -# Process ID: 11844 +# Start of session at: Wed Feb 27 11:36:59 2019 +# Process ID: 7276 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index 9b5eda4a19d633755a29ef51856495769f22756e..5862552283ec28710dcc4ef314bda244f0a12bb7 100644 GIT binary patch delta 329 zcmeB`*e5XI1>=i}FO^s}GjYwE%+GjMy(l%^Ei)%Iz9cC=DK#UpOrat(Cq5-LEwMDG zBquXT4=O*Io#}(eZ$>Vy;?$hfu$8#C3XQ0*oMKtP)&ICdQN3v&u1>8<=i(VUJ^+{Fu|4 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yx8U)MlIF@xqvbp|AJS1jFvI=}@R8}zY|z^l@LuSfx%D9c7c9{!9CMMh8-D`Cl(De@ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..3dc91ba --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "decoder_tb_behav" "xil_defaultlib.decoder_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..c836e28 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/obj/xsim_1.c @@ -0,0 +1,108 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[14] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 14; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/decoder_tb_behav/xsim.reloc", (void **)funcTab, 14); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/decoder_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/decoder_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/decoder_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/decoder_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/decoder_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..24e7748 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+
+
+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..c375aa4 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Wed Feb 27 11:44:18 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "25 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6064_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1469323063 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/xsim.mem new file mode 100644 index 0000000000000000000000000000000000000000..951ac9b62661034bf5480e6e82dfc8ee34f9cec2 GIT binary patch literal 2961 zcmeH{eKZql9LJXuy^>x~H0CYo=5^j}b!$k)*)66>p{o~4NNkJ6Zm70!mUJ+q8Cpy>-s*{&WAie|paOo!|HO{Jzigob&me^8f%pulH7e z*R1c^)%xfDTD3-Cjldd#H3I)HfvlC4m2dImR)rtpdsa090F+j>`f7;(;ro~EKg(0! z|MN6O03dpu@chY;eV)6t9T>)>J?R%0jC2@u%@u-9t`*+x{_%4#udF~=UjDd8*OhJKGDAY%XgH@owS%{0@+waXK&;)l!sr` z0}ibav<#`vr6B@1v|Dlmlqs4>hTmUdNZ+Ny>k`4Cqi-7e-tQD_4eL^dzkfZ)u>br7 zn_Vh9OjDJ8n#FV*dq}bDGtB1@?7Y9gIC;0=%f->^>>>qUUArqXL`ZN@F)CcY-DTGM zwxztZW;)$|6c6bSw|T9qfuS!h*X8_jWQ6Be;}4uW-T}dmFBxS^ymyM_2%5y(2opS5 z^;%S3m>q8ORfpB`c+g%c=qr|$7`cAWVhn$*GSQjiU08J0*Q51iJ*rjjgGy&#@|e*< zwO7dk@OS%Q;4HaC%h-Wlcv7WS`2zyC}~d z9x^3{%by^YkQJVn&UYl^Eur*A(Wp*avcm4T(!wdN&gi$16A;5P1K>@d3|?~JQfqey z&~IP2qZxk!OzVwZING>AFxxK^EzIJ_nR}Fysq=BG0)uVZ%dFwY<;I#$k5|v3ag#PK z%P$*BNKDv6*V7Q@-WwF<>80QYpv7%Uw)u z$K}Sk;wb~FsT*~#IvE7c_gkP<$%%AY>l;(?@LdW?Jn#pa9u`~F-je!IE1--ZdtSEm zz#jU{DjP8#?YM%hObK(b^hdM&NHjPDBY5NsXD+3(*@Qc+7VT!|>8M~8AZh<{N zF*2t<-nSX)0G{RdtMtUM-kST@9#y@Fx!{3EuS?b7c=l5vTu^u=-Ae+j>l1m^`(!9F zmu|$9dR7UJk^-4vm90Fk)D@2b;xWVkDXl@9&TP~LnaO$d3ztJM`Aij@)3j=BKJwCg zl3j@y>L%kFU}D=N=7N3mlIp|)`pL^nU!He;bM09QYg-?7USP5}+a><{#+SE)c*SB@&fnXa7GW**I zR?aTnAl^&1lCswAn>b^lVi)pZmK4ctD_EUScT{9qg|knW#tGq`X0Bc7dAE7(@Wck>jkuL#)@^8x)~*B_m1 z%mVY2X1%O=E}Olq1;@(tZLYLJ{UOtRr<>lI+@aQ9+W!oiV(R|;Jmi?QaEw1@NDOK; zCo - +
- + - + @@ -35,8 +35,8 @@
- - + +
diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl index 5396adb..625d097 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl @@ -1,6 +1,6 @@ webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Wed Feb 20 11:30:23 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Wed Feb 27 12:02:56 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" @@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "7" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "17" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" @@ -22,21 +22,11 @@ webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" webtalk_register_client -client xsim -webtalk_add_data -client xsim -key File_Counter -value "3" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Simulation_Image_Code -value "73 KB" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Image_Data -value "4 KB" -context "xsim\\usage" -webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Total_Processes -value "37" -context "xsim\\usage" -webtalk_add_data -client xsim -key Total_Instances -value "9" -context "xsim\\usage" -webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage" -webtalk_add_data -client xsim -key Compiler_Time -value "0.65_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Compiler_Memory -value "38732_KB" -context "xsim\\usage" -webtalk_transmit -clientid 3938710361 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "70 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.08_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6104_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1751969665 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/xsim.mem index 453a28e645839b1cfad54f4b4038de3fe20a9232..14fbda950f8a0aea2239406fdada80b9f4aee0d9 100644 GIT binary patch literal 4396 zcmeHIc{r478}BIO;HV@dBwHj>$IguQM3fpb#*DQ|wvcURjDr)BrO3XFHQCF~j6t?S zN%nQJPR24c7-o$5Ugy+zedqh<`{(0_x*eK?D^-@a{uph&3Adz z>7Va^o_TX zKf}9ckMA!_Fsp|Ub0LtFK6Lc@1IXdZT8K;q2VI`+;=*y5BUj(K_&!TZX3{uW^%psf z(<`>i5w{m2&UFMsogABkrM**)d)zNEtzSYTN4Wh~nyNqL5fuc|Y_3R7F*e|&+6CC5 z8dZ6zzH+4NhBm2sK$`?drb!yR?hkq#X>rb3X0o5-EfF%O?e#3_CI6G*2%L}!=7>%f z#&!tS;-;Q*_E><)7MwJ`=M49}iLCdXEFWsZB)TY16(I|H&5+m>FFah&Eq*~hs$ssn zl2$r)4#w6VZb7~Y-a2yE|4i_>lfC^ey#3X;Ze~d1CKRJ4I$*7@M8IHsiMoy zc*g``01xA;W@G?@Zj^(>+=F+;OGRxqy~tRMAQb z*OVE$c8ET0PgbG}-)b(!5?=~+rWkk)JnVUunNc|qOXe|EUPGx--Ij36MtFBF zEI8U(;2wXh9Ozv>)vpy0*NbBOnsK2DIafMVndHrmEufjv`#nL-s;^}6f!p#3lEZ`;4MmU z`Nqd87owrebH(I!C!T0JRIhgdQ`XLsE6$74L!KX^KO~gUQbnhZ(`>5vs{O!a%oyg& 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z-D$7hZ!JB>5#l%swzrnGA{uF#D?)YXBSDYQL#!Fum2u9gUha*d)&$di#=~EfZI`2K z4(fhuDG1iu*~DSBU;XG!G%DaFn8D|Abx#VMYBSmP{fpAv23K$#hknG&81R|}x4--u z_C{IQqD0;n+nx6-cfId`t0@&B;gY;@6MWwt-1@wm_roCc%Yt4h4|?4dx|q9#RHeCl zi0$r@qP$IsyiEb##SB>hH~rJ{&Mzn2*hK6~KZzX=GBs3Dn+ z73NaYL9y5BoP*oZc=2%==cR z>pywm?O#a6tcz?=w}CjK8SbHBYDX!L_@z4jnY$@x!PKz)=q8+Oz;9W28i0<7;T|PY H#SQN#*$UW7 diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index eaf0013..a4ea6c7 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -295,6 +295,52 @@ module and9bit_tb(); end endmodule +module decoder ( + input wire en, + input wire [1:0] index, + output reg [3:0] regOut); + + always @(en, index)begin + if(en == 1)begin + case(index) + 2'b00: regOut <= 4'b0001; + 2'b01: regOut <= 4'b0010; + 2'b10: regOut <= 4'b0100; + 2'b11: regOut <= 4'b1000; + default: regOut <= 4'bxxxx; + endcase + end + end +endmodule + +//testbench +module decoder_tb(); + reg enable; + reg [1:0] indexIn; + wire [3:0] regOut; + + decoder dec0( + .en(enable), + .index(indexIn), + .regOut(regOut)); + + initial begin + enable = 0; + indexIn = 2'b00; + #5 + enable = 1; + #5 + indexIn = 2'b01; + #5 + indexIn = 2'b10; + #5 + indexIn = 2'b11; + #5 + $finish; + + end +endmodule + module gen_clock(); reg clk; initial begin @@ -305,7 +351,7 @@ module gen_clock(); end endmodule -module mux_2_1 tb0( +module mux_2_1( input wire switch, input wire [8:0] A,B, output reg [8:0] out); @@ -850,7 +896,7 @@ endmodule module register( input wire clk, reset, - input wire [1:0] En, + input wire En, input wire [8:0] Din, output reg [8:0] Dout); @@ -858,7 +904,7 @@ module register( if (reset == 1'b1) begin Dout = 9'b000000000; end - else if (En == 2'b00) begin + else if (En == 1'b0) begin Dout = Din; end else begin diff --git a/lab2CA.srcs/sources_1/new/FetchUnit.v b/lab2CA.srcs/sources_1/new/FetchUnit.v index ac6899c..5647473 100644 --- a/lab2CA.srcs/sources_1/new/FetchUnit.v +++ b/lab2CA.srcs/sources_1/new/FetchUnit.v @@ -11,7 +11,7 @@ module FetchUnit(input wire clk, reset, register PC( .clk(clk), .reset(reset), - .En(2'b00), + .En(1'b0), .Din(result_m), .Dout(progC_out)); //Adds 1 to the program counter @@ -55,7 +55,7 @@ module fetchUnit_tb(); initial begin reset = 0; opidx = 1'b1; - addr_in = 0'b000000000; + addr_in = 9'b000000000; #5 reset = 1; #5 diff --git a/lab2CA.srcs/sources_1/new/RegFile.v b/lab2CA.srcs/sources_1/new/RegFile.v index fa040dd..fd51315 100644 --- a/lab2CA.srcs/sources_1/new/RegFile.v +++ b/lab2CA.srcs/sources_1/new/RegFile.v @@ -1,39 +1,46 @@ `timescale 1ns / 1ps -module RegFile(input wire clk, reset, +module RegFile(input wire clk, reset, enable, input wire [1:0] write_index, op0_idx, op1_idx, input wire [8:0] write_data, output wire [8:0] op0, op1); + wire [3:0] decOut; wire [8:0] r0_out, r1_out, r2_out, r3_out; // To select a register En input must be 2'b00 + decoder d0( + .en(enable), + .index(write_index), + .regOut(decOut) + ); + register r0( .clk(clk), .reset(reset), - .En({write_index[0], write_index[1]}), + .En(decOut[0]), .Din(write_data), .Dout(r0_out)); register r1( .clk(clk), .reset(reset), - .En({write_index[0], ~write_index[1]}), + .En(decOut[1]), .Din(write_data), .Dout(r1_out)); register r2( .clk(clk), .reset(reset), - .En({~write_index[0], write_index[1]}), + .En(decOut[2]), .Din(write_data), .Dout(r2_out)); register r3( .clk(clk), .reset(reset), - .En({~write_index[0], ~write_index[1]}), + .En(decOut[4]), .Din(write_data), .Dout(r3_out)); @@ -59,7 +66,7 @@ endmodule module regFile_tb(); reg [8:0] write_d; reg [1:0] w_idx, op0_idx, op1_idx; - reg reset,clk; + reg reset,clk, enable; wire [8:0] op0,op1; initial begin @@ -71,6 +78,7 @@ module regFile_tb(); RegFile regFile0( .clk(clk), + .enable(enable), .reset(reset), .write_index(w_idx), .op0_idx(op0_idx), @@ -85,6 +93,7 @@ module regFile_tb(); reset = 1; #5 reset = 0; + enable = 1; w_idx = 2'b00; op0_idx = 2'b00; op1_idx = 2'b00; diff --git a/lab2CA.xpr b/lab2CA.xpr index 0c89e60..ab16619 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - +